<div dir="ltr"><div>We'll need stable and quite high sample rate for LTE. </div><div>So I'd like PCIe to communicate with embedded PC board or via something like PCIe fiber optic modules.</div><div>But this might require more powerful FPGA.</div>
</div><div class="gmail_extra"><br clear="all"><div><br>Best regards,<br>Andrey Sviyazov.</div>
<br><br><div class="gmail_quote">2014-04-15 14:59 GMT+04:00 sergey kostanbaev <span dir="ltr"><<a href="mailto:sergey.kostanbaev@gmail.com" target="_blank">sergey.kostanbaev@gmail.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div dir="ltr"><div><div><div><div>Hi guys,<br><br></div>We cannot compare equally B2x0 and UmTRX, since<br></div>- B2x0 has CX3 USB3 interface which has ARM core inside and thus it doesn't need a CPU inside FPGA<br></div>
- Ethernet handling and USB is quite different, it's hard to have much code in common. And SRAM is needed only for Ethernet handling.<br></div><div>- Also we're taking in mind to support PCIe at some time and PCIe needs another handling interface.<br>
</div><div>So I don't think we need to move to B2x0 architecture completely.<br></div><div><br></div>Probably we can grab some good ideas from B2x0, something like this (but I'm not sure that are really good)<div class="">
<br><ul>
<li>Each DSP module has own reconfigurable vita timer. That's plus.<br></li><li>RX/TX control and RX/TX framer are new, DSP(DUC, DDC and so on) the same.</li></ul></div>What do you think about<div class=""><br>Instead of Wishbone bus there used AXI bus.<br>
<div><div><br></div></div></div></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><br><div class="gmail_quote">On Mon, Apr 14, 2014 at 10:02 PM, Andrew Karpenkov <span dir="ltr"><<a href="mailto:plddesigner@gmail.com" target="_blank">plddesigner@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div><div>Hi guys,</div><div><br></div><div>I took a quick look at B2x0 architecture.</div><div>And the results is here:</div>
<div><ul><li>There is no SRAM and utilization of internal block memory at Spartan 6 XC6SLX150 is about 70%. So, either we use external memory, or we need to use a new fpga.<br>
</li><li>2 TRX used about 45% of Spartan 6 XC6SLX150 Slices.<br></li><li>Instead of Wishbone bus there used AXI bus.<br></li><li>There is no CPU at all (hard logic).<br></li><li>I didn't find ICAP module here. But this is very usefull for a far away installations.<br>
</li><li>Each DSP module has own reconfigurable vita timer. That's plus.<br></li><li>RX/TX control and RX/TX framer are new, DSP(DUC, DDC and so on) the same.<br></li><li>There is no second signal from GPS module, only uart.<br>
</li><li>New serial_to_settings module for a working with devices through the I2C bus.<br></li><li>Overall code is very small and look pretty nice.<br></li><li>All required clock limitations are performed with large reserve. Input fpga clock is 40 MHz, internal system bus - 100 MHz, DSP clock frequency is the same with AD9361 DATA_CLK, 64.44MHz.</li>
</ul> Please, correct me, if I'm wrong.<br></div></div><div>
<div><div><br></div><div>I think that we need to use B2x0 architecture sooner or later. But this is huge work for a adding SRAM, Ethernet, CPU, ICAP into FPGA and UHD codes.</div></div><div>May be easier to modify current fpga code than rework B210 code for UmTRX architecture. Don't know..<br>
</div>
<div class="gmail_extra"><br clear="all"><div>Regards,<br>Andrew Karpenkov</div>
<br><br><div class="gmail_quote">2014-04-09 23:07 GMT+04:00 sergey kostanbaev <span dir="ltr"><<a href="mailto:sergey.kostanbaev@gmail.com" target="_blank">sergey.kostanbaev@gmail.com</a>></span>:<div><div>
<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<p>I also haven't had a time to look at. Hopefully I'll look at Friday.</p><div><div>
<div class="gmail_quote">On Apr 9, 2014 10:52 PM, "Andrew Karpenkov" <<a href="mailto:plddesigner@gmail.com" target="_blank">plddesigner@gmail.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div dir="ltr"><div>Ok. I understand. </div><div><br></div><div>I suppose that before make changes in current fpga code, we should make a decision exactly which architecture more suitable for UmTRX, N2x0 or B200?</div><div>
Sergey, Josh, what do you think about this, pro and con?</div><div><br></div><div>Unfortunately, I can look into B200 fpga code only at friday..<br></div><div><div class="gmail_extra"><br clear="all"><div>Regards,<br>Andrew Karpenkov</div>
<br><br><div class="gmail_quote">2014-04-09 20:43 GMT+03:00 Josh Blum <span dir="ltr"><<a href="mailto:josh@joshknows.com" target="_blank">josh@joshknows.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div><div><br>
<br>
On 04/09/2014 03:17 AM, Andrew Karpenkov wrote:<br>
> Josh,<br>
> I'm glad that I answered on most of yours questions. If you need some more<br>
> information, don't hesitate to contact with me.<br>
><br>
> 104MHz fifo bus in -> cross clock fifo to 26 MHz -> vita tx deframer -><br>
>> paced tx dsp -> out to dac<br>
>> in from adc -> paced rx dsp -> vita rx deframer -> cross clock fifo to<br>
>> 104 MHz -> 104 MHz fifo bus out<br>
><br>
><br>
> According to your idea. I think that this is fine, but are you're sure that<br>
> 26MHz is enough for DSP calculations? In N2x0 DSP clock frequency was twice<br>
> higher than CPU clock.<br>
><br>
<br>
</div></div>Well technically, the DSP only needs to run as fast as the ADC/DAC<br>
sample rate. In the current UMTRX design, the DSP calculations<br>
themselves are running at 13 MHz. I'm only suggesting moving the VITA<br>
framer/deframer into the same clock domain as the DSP units (26MHz). The<br>
actual buffering, packet routing, fifo muxing, that sort of stuff will<br>
stay in the 104MHz clock domain (it has to be faster because of<br>
buffering/sending ethernet packets). And the CPU/ZPU/wishbone clock is<br>
independent, and really only for low speed communications -- I would<br>
simply keep this at 52 Mhz, but in fact, its clock rate isnt really<br>
critical.<br>
<span><font color="#888888"><br>
-josh<br>
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