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<div class="moz-cite-prefix">Hi,<br>
<br>
We need a bit more info to see what we can do to avoid at least
cooling fan as it is expensive.<br>
<br>
1. Was that proper temperature chamber measurement or just Rx
on/off?<br>
<br>
2. I think we are talking about two issues called phase error
here.<br>
2.a IQ phase error caused by LMS Tx/Rx PLLs alone<br>
2.b Modulation phase error<br>
<br>
Item 2.a should not be affected by temperature so much In
900/1800MHz frequency region. If we want to get it even better we
can always make a look up table vs temperature to correct IQ phase
error from FPGA. <br>
<br>
Item 2.b is affected by both 2.a and Tx DC cal. Tx DC cal has
already been addressed by Thomas. <br>
<br>
Combining Thomas's idea of DC recalibration and, if necessary,
making look up table for IQ phase error correction vs temperature
should put us in good position to meet the specs.<br>
<br>
<br>
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<![endif]--></o:smarttagtype></o:smarttagtype>On 26/07/2012 06:03,
Alexander Chemeris wrote:<br>
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<blockquote
cite="mid:CABmJbFVf-1yO_G1JU6f_-mm19fNMa=tWi3AkLboyt0TKBjGhDA@mail.gmail.com"
type="cite">
<pre wrap="">Hi all,
Thomas has discovered that DC offset calibration for LMS is drifting a
lot with temperature changes and this has detrimental effect on the
modulation accuracy:
<a class="moz-txt-link-freetext" href="http://code.google.com/p/umtrx/issues/detail?id=31">http://code.google.com/p/umtrx/issues/detail?id=31</a>
One solution proposed by Sylvain is to tune modulation a bit higher
using digital modulation, which should be straightforward with UHD
which has digital mixer in FPGA.
But I wonder what is a recommended solution for this temperature
compensation for LMS in general. Srdjan, could you comment on this?
</pre>
</blockquote>
<br>
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