<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=ISO-8859-1">
</head>
<body bgcolor="#FFFFFF" text="#000000">
Hi all,<br>
<br>
As far as I am aware, you are currently discussing how to improve
LMS6002 PLL phase noise. Below are some inputs from my side which
may help.<br>
<br>
Apart from playing with PLL registers we have two additional
options.<br>
<br>
1. Use clean TCXCO which provides 4 times higher reference followed
by divide by 4 to generate PLL reference clock. Recently, we
experimented with 30.72*4 MHz TCXCO. Dividing its output by 4 before
going into LMS chip we have got improvement of 6dB in phase noise
plateau region.
<br>
<br>
2. Current PLL loop filter has been designed to cover the whole LMS
frequency range hence using kind of mid value for Kvco. We can
customize the loop filter for a particular band. To do that we need
to know frequency range China Mobile is looking for and reference
clock you want to use (26MHz, 26*4/4MHz, ...). Please note that PLL
reference clock does not need to be the same as system clock i.e. we
can also use 30.72MHz, 30.72*4/4MHz etc.
<br>
<br>
Best regards, Srdjan
<div class="moz-signature"><o:smarttagtype
namespaceuri="urn:schemas-microsoft-com:office:smarttags"
name="country-region"><o:smarttagtype
namespaceuri="urn:schemas-microsoft-com:office:smarttags"
name="place"><br>
</o:smarttagtype></o:smarttagtype></div>
</body>
</html>