Which gives ~1.5khz cut-off, that's strange<br><br>Also I'd check GPS VDD and AVDD nosies <br><br><div class="gmail_quote">On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov <span dir="ltr"><<a href="mailto:andrey.sviyazov@fairwaves.ru" target="_blank">andrey.sviyazov@fairwaves.ru</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div>1kOhm resistor and 0.1uF capacitor already exist between DAC and VC input.</div><div>Of course I'll increase capacitance or resistance to be sure about VC pin.</div>
<div class="HOEnZb"><div class="h5"><div><br clear="all">Best regards,<div>Andrey Sviyazov.</div>
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<br><br><div class="gmail_quote">2012/7/19 sergey kostanbaev <span dir="ltr"><<a href="mailto:sergey.kostanbaev@gmail.com" target="_blank">sergey.kostanbaev@gmail.com</a>></span><br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
No :) But it may cause.<div><br></div><div>I'd check all the line from FPGA to DAC to VCTXCO because VC pin is really sensible to any noise.</div><div> - caused by power supply of DAC. </div><div> - output noise of DAC.</div>
<div> - algorithm of changing values</div><div><br></div><div>At first I'd inspect VC pin at VCTXCO and try to filter it with cut-off frequency 1-0.1 Hz<div><div><br><br><div class="gmail_quote">On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov <span dir="ltr"><<a href="mailto:andrey.sviyazov@fairwaves.ru" target="_blank">andrey.sviyazov@fairwaves.ru</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div>Sergey.</div>Is it really so frequently (32k/s updates at 1pps reference)?<div><br clear="all">Best regards,<div>
Andrey Sviyazov.</div>
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<br><br><div class="gmail_quote">2012/7/19 sergey kostanbaev <span dir="ltr"><<a href="mailto:sergey.kostanbaev@gmail.com" target="_blank">sergey.kostanbaev@gmail.com</a>></span><br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br><br><div class="gmail_quote"><div>On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov <span dir="ltr"><<a href="mailto:andrey.sviyazov@fairwaves.ru" target="_blank">andrey.sviyazov@fairwaves.ru</a>></span> wrote:<br>
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Hi all.<div><br></div><div><div>I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset when GPS antenna used and position locked.</div><div>This spurs begin grow up when GPS just near to lock position and after locking spurs stopped to grow as you can see at picture.</div>
<div>If thereafter GPS disconnected then noise coming back to normal plot.</div><div>I think that it is result of 32768Hz clock in the GPS module EB-230, but can't understant how it can impact to 26MHz clock or VCO.</div>
</div></blockquote><div><br></div></div><div>As another idea it can be caused by continues GPS correction lead to DAC changes to the VCTXCO. </div><div><div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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<div>Please tell me something who know.</div></div><div><br></div><div><div>Thomas.</div><div>Was GPS antenna connected when noise measured like on the picture which you sent us (also attached here)?</div><div>I would to know because of anomal peak near to 30kHz offset too.</div>
</div><div><br></div><div>Best regards,<div>Andrey Sviyazov.</div><div><div><br>
<br><br><div class="gmail_quote">2012/7/19 Andrey Sviyazov <span dir="ltr"><<a href="mailto:andrey.sviyazov@fairwaves.ru" target="_blank">andrey.sviyazov@fairwaves.ru</a>></span><br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<span style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">Sorry, that was meant to be </span><span style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">sent to the mailing list</span> :)<div>
<br clear="all">Best regards,<div>Andrey Sviyazov.</div>
<br><div class="gmail_quote"><div>---------- Forwarded message ----------<br>From: <b class="gmail_sendername">Andrey Sviyazov</b> <span dir="ltr"><<a href="mailto:andreysviyaz@gmail.com" target="_blank">andreysviyaz@gmail.com</a>></span><br>
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Date: 2012/7/18<br>Subject: LMS TxLO noise<br><br>Hi Thomas.<div><br></div><div><div>Here forwarded my last e-mail with noise plots when I stopped work around it at first time, please see below.</div><div><br></div><div>
Please try to play around Tx PLL charge pump current (register 0x16) for better RMS phase stability.</div>
<div>I think we should reach 1 degree or below.</div></div><div><br></div><div>Alexander gave me the second UmTRX board and after checking and fixing all known hardware <a href="http://code.google.com/p/umtrx/issues/list?can=1&q=&colspec=ID+Type+Status+Priority+Milestone+Owner+Summary+Modified&cells=tiles" target="_blank">issues</a> I've got roughly the same LO noise plot.</div>
<div><div>Possible Robin had no time to fixing all of our issues, so check them all please.</div><div>And also check please what type of TCXO installed on your board.</div></div><div><br></div></div><div>Best regards,<div>
Andrey Sviyazov.</div>
<div><div><br><div class="gmail_quote"><div>---------- Forwarded message ----------<br>From: <b class="gmail_sendername">Andrey Sviyazov</b> <span dir="ltr"><<a href="mailto:andreysviyaz@gmail.com" target="_blank">andreysviyaz@gmail.com</a>></span><br>
Date: 2012/4/13<br>Subject: Re: LMS TxLO noise<br><br></div><div><div><div><div>Hi all.</div><div><br></div><div>There is progress with LMS PLL :)</div><div>Pictures are attached here.</div><div>t was discovered that 80 kHz spurs come from Ethernet, or rather from the ET1011.</div>
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I unknowingly put the choke between transistor of 1V regulator and analog power 1V.</div><div>As a result, the regulator has become unstable and oscillated 80 kHz with amplitude of 200 mV, which climbed into the LMS PLL.</div>
<div>To correct this problem L46 should be replaced by jumper on all alfa version PCB's.</div><div><br></div><div>Also I just played with current in the PLL loop, shown on the picture for clarity.</div><div>Proved to be the optimal current 1,9 mA (you should write 0x93 in the register of 0x16).</div>
<div>But, I think, for the RxPLL will be better use of the current 2.4 mA, because the nearest noises more important for Rx (you should write 0x98 in the register 0x26).</div><div><br></div><div>Best regards,</div><div>Andrey Sviyazov.</div>
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