umtrx fpga internal clocking
sergey.kostanbaev at gmail.com
Wed Apr 9 19:07:35 UTC 2014
I also haven't had a time to look at. Hopefully I'll look at Friday.
On Apr 9, 2014 10:52 PM, "Andrew Karpenkov" <plddesigner at gmail.com> wrote:
> Ok. I understand.
> I suppose that before make changes in current fpga code, we should make a
> decision exactly which architecture more suitable for UmTRX, N2x0 or B200?
> Sergey, Josh, what do you think about this, pro and con?
> Unfortunately, I can look into B200 fpga code only at friday..
> Andrew Karpenkov
> 2014-04-09 20:43 GMT+03:00 Josh Blum <josh at joshknows.com>:
>> On 04/09/2014 03:17 AM, Andrew Karpenkov wrote:
>> > Josh,
>> > I'm glad that I answered on most of yours questions. If you need some
>> > information, don't hesitate to contact with me.
>> > 104MHz fifo bus in -> cross clock fifo to 26 MHz -> vita tx deframer ->
>> >> paced tx dsp -> out to dac
>> >> in from adc -> paced rx dsp -> vita rx deframer -> cross clock fifo to
>> >> 104 MHz -> 104 MHz fifo bus out
>> > According to your idea. I think that this is fine, but are you're sure
>> > 26MHz is enough for DSP calculations? In N2x0 DSP clock frequency was
>> > higher than CPU clock.
>> Well technically, the DSP only needs to run as fast as the ADC/DAC
>> sample rate. In the current UMTRX design, the DSP calculations
>> themselves are running at 13 MHz. I'm only suggesting moving the VITA
>> framer/deframer into the same clock domain as the DSP units (26MHz). The
>> actual buffering, packet routing, fifo muxing, that sort of stuff will
>> stay in the 104MHz clock domain (it has to be faster because of
>> buffering/sending ethernet packets). And the CPU/ZPU/wishbone clock is
>> independent, and really only for low speed communications -- I would
>> simply keep this at 52 Mhz, but in fact, its clock rate isnt really
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