Multiple DDC chains on UMTRX

[Sylvain Munaut]

Hi,

I was wondering whether there is an FPGA image for the UmTRX which gives 4x
> DDC Rx chains (at the expense of the two DUC chains) like the USRP1
> usrp1_fpga_4rx.rbf. I guess this is unlikely, due to the fact it looks like
> the majority of people are using the UmTRX for OpenBTS! How difficult would
> it be to change the current firmware to support this.
>

It shouldn't be too hard I think, at least for someone familiar with fpga
image. But still not trivial either, maybe a couple days work (depending on
luck / testing /... )



> Another couple of questions, what's the maximum achievable bandwidth
> through a single Rx chain so far and are there any constraints on what
> value of decimation to use (e.g. USRP has the requirement that to use both
> CIC filters decimation factors have to be a factor of 4, otherwise the
> frequency response will be affected)?
>

The hw should support getting the full 26 MHz out, but ethernet bandwidth
might saturate at that point (so may have to go to 8 bits).



> When I increase the sample rate (e.g. 4.333 MHz) I start seeing the
> frequency response affected, the FFT plot seems to 'flicker' between a
> reasonably flat looking response and a poor frequency response (see
> attached files - both taken from the same running instance of a flow graph)
>

The LMS chip has internal low pass filters, these need to be set
appropriately and I'm not sure setting the sample rate is sufficient. (i.e.
you need to set the bandwidth as well, assuming that UHD control of theses
is implemented, to be checked).


Cheers,

    Sylvain
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.osmocom.org/pipermail/umtrx/attachments/20130422/e4ee8a6a/attachment.htm>