LMS6002D support of LTE

Srdjan Milenkovic s.milenkovic at limemicro.com
Sun Oct 14 11:11:43 UTC 2012


Hi Alexander,

You can simply replace 26MHz TCXO with foot print compatible 61.44MHz 
TCXO. Divide by 2 would be required to construct PLL reference below max 
41MHz (61.44/2 = 30.72MHz) while having IQ interface still running at 
61.44MHz which corresponds to 30.72MS/s converters sample rate. This is 
something we usually do with LMS eval board when customers want to 
evaluate more bandwidth demanding modulations such as 20MHz LTE.

Regards, Srdjan

On 14/10/2012 08:47, Alexander Chemeris wrote:
> Hum, good idea for the very first try. We should try this out this week.
>
> But I still want a normal TCXO/OCXO replacement for UmTRX to make it
> easier to rework more UmTRX boards.
>
> On Sun, Oct 14, 2012 at 7:35 AM, sergey kostanbaev
> <sergey.kostanbaev at gmail.com> wrote:
>> Just use our ClockTamer to see how it works :)
>>
>>
>> On Sun, Oct 14, 2012 at 11:30 AM, Alexander Chemeris
>> <alexander.chemeris at gmail.com> wrote:
>>> Hi Robin,
>>>
>>> Do you mean to use ADF4002 to double the frequency?
>>>
>>> Right now I want a simple solution - just replace the TCXO on UmTRX
>>> from 26MHz to 61.44MHz and see how it works. Doubling the frequency
>>> would require PCB rework and is possible for the next generation of
>>> UmTRX only.
>>>
>>> On Sun, Oct 14, 2012 at 4:18 AM, Robin Coxe <coxe at close-haul.com> wrote:
>>>> Something like the attached Taiten VCTCXO @ 30.72 MHz + ADF4002 Phase
>>>> Detector/PLL synthesizer might work.  I have no idea how much the
>>>> oscillator
>>>> costs.  (The Pletronics oscillator on the UmTRX and the GAPfiller GSM900
>>>> isn't available at this frequency.)
>>>>
>>>>
>>>> http://www.analog.com/en/rfif-components/pll-synthesizersvcos/adf4002/products/product.html
>>>>
>>>> -Robin
>>>>
>>>> On Sat, Oct 13, 2012 at 11:54 PM, Alexander Chemeris
>>>> <alexander.chemeris at gmail.com> wrote:
>>>>> John,
>>>>>
>>>>> On Sun, Oct 14, 2012 at 12:24 AM, John Orlando <john at epiqsolutions.com>
>>>>> wrote:
>>>>>> On Sat, Oct 13, 2012 at 4:30 PM, Alexander Chemeris
>>>>>> <alexander.chemeris at gmail.com> wrote:
>>>>>>> Hi John,
>>>>>>>
>>>>>>> On Sat, Oct 13, 2012 at 11:11 PM, John Orlando
>>>>>>> <john at epiqsolutions.com>
>>>>>>> wrote:
>>>>>>>> On Sat, Oct 13, 2012 at 3:47 PM, Alexander Chemeris
>>>>>>>> <alexander.chemeris at gmail.com> wrote:
>>>>>>>>> Hi Srdjan,
>>>>>>>>>
>>>>>>>>> We're looking into re-purposing UmTRX for LTE and there a few
>>>>>>>>> things
>>>>>>>>> which
>>>>>>>>> we need to understand better.
>>>>>>>>>
>>>>>>>>> 1. Is it possible to support 15MHz and 20MHz LTE channel
>>>>>>>>> bandwidths?
>>>>>>>>> To
>>>>>>>>> achieve this we at least need to sample at 23.04Msps and 30.72Msps
>>>>>>>>> respectively. LMS6002D datasheet specifies the maximum I/Q
>>>>>>>>> samplerate
>>>>>>>>> of
>>>>>>>>> 14Msps, which is not enough. But at the same time, datasheet
>>>>>>>>> claims
>>>>>>>>> that ADC
>>>>>>>>> and DAC are specified up to 50Msps. How does this fits together?
>>>>>>>> Alexander,
>>>>>>>> Can you provide a reference to where the datasheet calls out a max
>>>>>>>> I/Q
>>>>>>>> sample rate of 14 Msps?  The analog low pass filters support a max
>>>>>>>> bandwidth of 14 MHz (which leads to 28 MHz RF bandwidth assuming
>>>>>>>> zero-IF operation)...is this what you're referencing?
>>>>>>> The datasheet is not very clear on this topic. I'm referring to the
>>>>>>> following line at the Table 1:
>>>>>>> Baseband Bandwidth       14MHz
>>>>>>>
>>>>>>> Originally I read this line as "digital I/Q bus has limitation of
>>>>>>> 14Msps" and this is what confuses me.
>>>>>> Yes, this refers to the analog baseband filter bandwidth.
>>>>> Ok, thanks for the clarification.
>>>>>
>>>>>>>>   We run the A/D
>>>>>>>> converters in the LMS6002d at sample rates greater than 14 Msps all
>>>>>>>> the time, including 30.72 Msps.
>>>>>>> Just to be sure - do you mean you feed RX_CLK and TX_CLK of LMS6002D
>>>>>>> with 61.44MHz clock? It's divided by 2 internally, so if you feed
>>>>>>> them
>>>>>>> with 30.72MHz clock you actually get only 15.36Msps out of LMS6002D.
>>>>>> Correct, when running the A/D at 30.72 Msps, the RX_CLK signal needs
>>>>>> to run at 61.44 MHz.
>>>>> Great!
>>>>> In case you know a good 61.44 MHz oscillator with a reasonable price -
>>>>> I would appreciate a pointer.
>>>>>
>>>>> --
>>>>> Regards,
>>>>> Alexander Chemeris.
>>>>> CEO, Fairwaves LLC / ООО УмРадио
>>>>> http://fairwaves.ru
>>>>>
>>>>
>>>>
>>>> --
>>>> Robin Coxe  |  Close-Haul Communications, Inc.  |  Boston, MA
>>>> +1-617-470-8825
>>>
>>>
>>> --
>>> Regards,
>>> Alexander Chemeris.
>>> CEO, Fairwaves LLC / ООО УмРадио
>>> http://fairwaves.ru
>>>
>
>





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