Improving LMS6002 phase noise

Srdjan Milenkovic s.milenkovic at limemicro.com
Sun Jul 22 15:38:47 UTC 2012


Hi Alexander,

We usually do chip tests as close to the defaults as possible. All the 
changes from the defaults which lead to significant improvement would be 
recorded and shared with customers. Below is test description. I do not 
see any major changes from the defaults.

We do not have register dump. However, Lime GUI project file used in 
this experiment is attached. You can use GUI File->Open Project option 
to import it. I see Ichp and Ichp offset currents are different from 
defaults but these still do not justify 5-12dB worse PN in your reports. 
You can give it a try though before changing TCXCO.

Best regards, Srdjan

*Test Description:*

  * DC MAX applied through analogue inputs, DACs off

  * TXVGA1 and TXVGA2 at max gain

  * Loop filter redesigned for 100kHz loop bandwidth and 40MHz reference

  * Icp and Icp offset optimized at 25 deg. Same set up used at all
    other temperatures

  * Cap code and VCO picked up by PLL tune routine

  * Span 1kHz to 10 MHz

  * Measure integrated PN

  * Measure PN at decade frequency points

  * Measure LO level

  * Record VCOCAP code

  * Using Tune log, record VCOCAP code range

  * Record VCO and FF divider



Dr Srdjan Milenkovic

On 22/07/2012 15:16, Alexander Chemeris wrote:
> On Sun, Jul 22, 2012 at 3:11 PM, Srdjan Milenkovic
> <s.milenkovic at limemicro.com> wrote:
>> On 21/07/2012 16:28, Alexander Chemeris wrote:
>>> Hi Srdjan,
>>>
>>> On Sat, Jul 21, 2012 at 4:33 PM, Srdjan Milenkovic
>>> <s.milenkovic at limemicro.com> wrote:
>>>> Hi all,
>>>>
>>>> As far as I am aware, you are currently discussing how to improve LMS6002
>>>> PLL phase noise. Below are some inputs from my side which may help.
>>> Yes, here are some pictures of phase noise we have at UmTRX right now:
>>> http://lists.osmocom.org/pipermail/umtrx/2012-July/000030.html
>>>
>>> It looks like they're 5-12dB higher then data I saw in your
>>> temperature measurement report. First thought is that this could be
>>> due to a clock source. Did you use your EVB board for those
>>> measurements?
>> Yes, we used Lime EVB, 30.72MHz TCXCO. However, using 26MHz instead of
>> 30.72MHz TCXCO should not affect phase noise so much (5-12dB). Do you have
>> an alternative 26MHz TCXCO with better PN? As you quite rightly mentioned,
>> you are probably limited by TCXCO PN at the moment.
> Could you please share LMS configuration you used during this test, so
> we could re-create it locally with the EVB we have. A full register
> dump of the chip would be ideal.
>

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[BNDS]
I=1
II=1
III=1
IV=1
V=1
VI=1
VII=1
VIII=1
IX=1
X=1
XI=1
XII=1
XIII=1
XIV=1
[0]
cmbDCCalAddr=0
cmbCalVal=31
LPF_dco_CAL=31
rgrDecode=0
rgrDsmRst=1
chbPwrTopMods=1
chbPwrSoftTx=1
chbPwrSoftRx=0
rgrSpiMode=1
rgrCLKSEL_LPFCAL=1
chbPD_CLKLPFCAL=1
chkLpfCalEnEnf=0
chkLpfCalRst=1
chkLpfCalEn=0
cmbLpfCalCode=0
cmbLpfCalBw=0
chbRxTestModeEn=0
rgrBBLB=0
rgrRFLB=0
rgrRXOUTSW=1
chbSpiClkBuf_0=1
chbSpiClkBuf_1=0
chbSpiClkBuf_2=0
chbSpiClkBuf_3=0
chbSpiClkBuf_4=0
chbSpiClkBuf_5=0
chbSpiClkBuf_6=0
rgrFDDTDD=0
rgrTDDMOD=0
chbPDXCOBUF=0
chbSLFBXCOBUF=1
chbBYPXCOBUF=0
chbPwrLpfCal=1
chbPwrRfLbsw=0
[3]
cmbDCCalAddr=1
cmbCalVal=31
LPF_dco_I=31
LPF_dco_Q=31
cmbLpfBw=0
chbPwrLpfMods=1
rgrDecode=0
rgrLpfByp=0
cmbDCOffset=12
chbTX_DACBUF_EN=1
cmbRcCal=3
chbPwrDCCmpr=1
chbPwrDCDac=1
chbPwrDCRef=1
chbPwrLpf=1
[5]
cmbDCCalAddr=0
cmbCalVal=31
LPF_dco_I=31
LPF_dco_Q=31
cmbLpfBw=0
chbPwrLpfMods=1
rgrDecode=0
rgrLpfByp=0
cmbDCOffset=12
chbTX_DACBUF_EN=0
cmbRcCal=3
chbPwrDCCmpr=1
chbPwrDCDac=1
chbPwrDCRef=1
chbPwrLpf=1
[4]
chbPwrTxRfMods=1
rgrDecode=0
cmbVga1G_u=31
cmbVga1DcI=128
cmbVga1DcQ=128
rgrPA=2
chbPD_DRVAUX=1
chbPD_PKDET=1
cmbVga2G_u=25
cmbENVD=0
cmbENVD2=0
cmbPKDBW=0
rgrLOOPBBEN=0
chbFST_PKDET=0
chbFST_TXHFBIAS=0
cmbICT_TXLOBUF=4
cmbVBCAS_TXDRV=0
cmbICT_TXMIX=12
cmbICT_TXDRV=12
chbPwrVga1_I=1
chbPwrVga1_Q=1
chbPD_TXDRV=0
chbPD_TXLOBUF=0
chbPwrVga2=0
cmbVga1G_t=21
cmbVga2G_t=0
[6]
cmbDCCalAddr=0
cmbCalVal=31
dc_ref=31
dc2a_I=31
dc2a_Q=31
dc2b_I=31
dc2b_Q=31
cmbVCM=12
chbPwrVGA2Mods=1
rgrDecode=0
cmbVga2G_u=1
chbPwrDCCurrR=1
chbPwrDCDACB=1
chbPwrDCCmpB=1
chbPwrDCDACA=1
chbPwrDCCmpA=1
chbPwrBG=1
chbPwrBypAB=1
chbPwrBypB=1
chbPwrBypA=1
chbPwrCurrRef=1
cmbVga2GB_t=0
cmbVga2GA_t=1
[7]
rgrDecode=0
chbPwrRxFeMods=1
cmbIN1SEL_MIX_RXFE=1
cmbDCOFF_I_RXFE=63
chkINLOAD_LNA_RXFE=1
cmbDCOFF_Q_RXFE=63
chkXLOAD_LNA_RXFE=0
cmbIP2TRIM_I_RXFE=63
cmbIP2TRIM_Q_RXFE=63
cmbG_LNA_RXFE=2
cmbLNASEL_RXFE=1
cmbCBE_LNA_RXFE=0
cmbRFB_TIA_RXFE=120
cmbCFB_TIA_RXFE=0
cmbRDLEXT_LNA_RXFE=28
cmbRDLINT_LNA_RXFE=55
cmbICT_MIX_RXFE=7
cmbICT_LNA_RXFE=7
cmbICT_TIA_RXFE=7
cmbICT_MXLOB_RXFE=7
cmbLOBN_MIX_RXFE=3
chkRINEN_MIX_RXFE=0
cmbG_FINE_LNA3_RXFE=0
chkPD_TIA_RXFE=1
chkPD_MXLOB_RXFE=1
chkPD_MIX_RXFE=1
chkPD_LNA_RXFE=1
[1]
txtDesFreq=3.2
chkDITHEN=1
cmbDITHN=0
chbPwrPllMods=1
chbAUTOBYP=0
rgrDecode=0
rgrMODE=0
rgrSELVCO=3
rgrFRANGE=1
cmbSELOUT=1
chbEN_PFD_UP=1
chkOEN_TSTD_SX=0
chkPASSEN_TSTOD_SD=0
cmbICHP=14
chbBYPVCOREG=1
chbPDVCOREG=1
chbFSTVCOBG=1
cmbOFFUP=0
cmbVOVCOREG=5
cmbOFFDOWN=3
cmbVCOCAP=36
cmbBCODE=5
cmbACODE=0
cmbPD_VCOCOMP_SX=0
chkENLOBUF=1
chkENLAMP=1
chkTRI=0
chkPOL=0
chkPFDPD=1
chkENFEEDDIV=1
chkPFDCLKP=1
rgrBCLKSEL=2
rgrBINSEL=0
RefClk=40000000
[2]
txtDesFreq=1.95
chkDITHEN=1
cmbDITHN=0
chbPwrPllMods=1
chbAUTOBYP=0
rgrDecode=0
rgrMODE=0
rgrSELVCO=1
rgrFRANGE=1
cmbSELOUT=1
chbEN_PFD_UP=1
chkOEN_TSTD_SX=0
chkPASSEN_TSTOD_SD=0
cmbICHP=12
chbBYPVCOREG=1
chbPDVCOREG=1
chbFSTVCOBG=1
cmbOFFUP=3
cmbVOVCOREG=5
cmbOFFDOWN=0
cmbVCOCAP=16
cmbBCODE=5
cmbACODE=0
cmbPD_VCOCOMP_SX=1
chkENLOBUF=1
chkENLAMP=1
chkTRI=0
chkPOL=0
chkPFDPD=1
chkENFEEDDIV=1
chkPFDCLKP=1
rgrBCLKSEL=2
rgrBINSEL=0
RefClk=40000000
[15]
chbEN_ADC_DAC=0
rgrDecode=0
cmbDACInternalOutputLoadResistor=2
rgrDACReferenceCurrentResistor=1
cmbDACFullScaleOutputCurrent=0
cmbRefResistorBiasAdj=0
cmbRefBiasUp=0
cmbRefBiasDn=0
cmbRefGainAdj=0
cmbCoomonModeAdj=1
cmbRefBufferBoost=0
chkInputBufferDisable=1
rgrRX_FSYNC_P=0
rgrRX_INTER=0
rgrDAC_CLK_P=1
rgrTX_FSYNC_P=0
rgrTX_INTER=0
cmbADCSamplingPhase=0
cmbClockNonOverlapAdjust=0
rgrADCBiasResistorAdjust=0
cmbMainBiasDN=0
rgrADCAmp1Stage1BasUp=0
rgrADCAmp24Stage1BasUp=0
rgrADCAmp1Stage2BasUp=0
rgrADCAmp24Stage2BasUp=0
rgrQuantizerBiasUp=0
rgrInputBufferBiasUp=0
cmbBandgapTemp=8
cmbBandgapGain=8
cmbRefAmpsBiasAdj=0
cmbRefAmpsBiasUp=0
cmbRefAmpsBiasDn=0
chkEN_DAC=1
chkEN_ADC_I=1
chkEN_ADC_Q=1
chkEN_ADC_REF=1
chkEN_M_REF=1


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