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Alexander Chemeris alexander.chemeris at gmail.comHi Srdjan, On Sat, Jul 21, 2012 at 4:33 PM, Srdjan Milenkovic <s.milenkovic at limemicro.com> wrote: > Hi all, > > As far as I am aware, you are currently discussing how to improve LMS6002 > PLL phase noise. Below are some inputs from my side which may help. Yes, here are some pictures of phase noise we have at UmTRX right now: http://lists.osmocom.org/pipermail/umtrx/2012-July/000030.html It looks like they're 5-12dB higher then data I saw in your temperature measurement report. First thought is that this could be due to a clock source. Did you use your EVB board for those measurements? > Apart from playing with PLL registers we have two additional options. > > 1. Use clean TCXCO which provides 4 times higher reference followed by > divide by 4 to generate PLL reference clock. Recently, we experimented with > 30.72*4 MHz TCXCO. Dividing its output by 4 before going into LMS chip we > have got improvement of 6dB in phase noise plateau region. > > 2. Current PLL loop filter has been designed to cover the whole LMS > frequency range hence using kind of mid value for Kvco. We can customize the > loop filter for a particular band. Well, we're working with GSM and it has only four main bands: GSM-850: 824.2–849.2 UL / 869.2–894.2 DL E-GSM 900: 880.0–915.0 UL / 925.0–960.0 DL DCS-1800: 1,710.2–1,784.8 UL / 1,805.2–1,879.8 DL PCS-1900: 1,850.2–1,909.8 UL / 1,930.2–1,989.8 DL It would be great if we could optimize for the use in these bands -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ООО УмРадио http://fairwaves.ru