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sergey kostanbaev sergey.kostanbaev at gmail.comNo :) But it may cause. I'd check all the line from FPGA to DAC to VCTXCO because VC pin is really sensible to any noise. - caused by power supply of DAC. - output noise of DAC. - algorithm of changing values At first I'd inspect VC pin at VCTXCO and try to filter it with cut-off frequency 1-0.1 Hz On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov < andrey.sviyazov at fairwaves.ru> wrote: > Sergey. > Is it really so frequently (32k/s updates at 1pps reference)? > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 sergey kostanbaev <sergey.kostanbaev at gmail.com> > >> >> >> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov < >> andrey.sviyazov at fairwaves.ru> wrote: >> >>> Hi all. >>> >>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset when >>> GPS antenna used and position locked. >>> This spurs begin grow up when GPS just near to lock position and after >>> locking spurs stopped to grow as you can see at picture. >>> If thereafter GPS disconnected then noise coming back to normal plot. >>> I think that it is result of 32768Hz clock in the GPS module EB-230, but >>> can't understant how it can impact to 26MHz clock or VCO. >>> >> >> As another idea it can be caused by continues GPS correction lead to DAC >> changes to the VCTXCO. >> >> >>> Please tell me something who know. >>> >>> Thomas. >>> Was GPS antenna connected when noise measured like on the picture which >>> you sent us (also attached here)? >>> I would to know because of anomal peak near to 30kHz offset too. >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/19 Andrey Sviyazov <andrey.sviyazov at fairwaves.ru> >>> >>>> Sorry, that was meant to be sent to the mailing list :) >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> ---------- Forwarded message ---------- >>>> From: Andrey Sviyazov <andreysviyaz at gmail.com> >>>> Date: 2012/7/18 >>>> Subject: LMS TxLO noise >>>> >>>> Hi Thomas. >>>> >>>> Here forwarded my last e-mail with noise plots when I stopped work >>>> around it at first time, please see below. >>>> >>>> Please try to play around Tx PLL charge pump current (register 0x16) >>>> for better RMS phase stability. >>>> I think we should reach 1 degree or below. >>>> >>>> Alexander gave me the second UmTRX board and after checking and fixing >>>> all known hardware issues<http://code.google.com/p/umtrx/issues/list?can=1&q=&colspec=ID+Type+Status+Priority+Milestone+Owner+Summary+Modified&cells=tiles>I've got roughly the same LO noise plot. >>>> Possible Robin had no time to fixing all of our issues, so check them >>>> all please. >>>> And also check please what type of TCXO installed on your board. >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> ---------- Forwarded message ---------- >>>> From: Andrey Sviyazov <andreysviyaz at gmail.com> >>>> Date: 2012/4/13 >>>> Subject: Re: LMS TxLO noise >>>> >>>> Hi all. >>>> >>>> There is progress with LMS PLL :) >>>> Pictures are attached here. >>>> t was discovered that 80 kHz spurs come from Ethernet, or rather from >>>> the ET1011. >>>> I unknowingly put the choke between transistor of 1V regulator and >>>> analog power 1V. >>>> As a result, the regulator has become unstable and oscillated 80 kHz >>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>>> To correct this problem L46 should be replaced by jumper on all alfa >>>> version PCB's. >>>> >>>> Also I just played with current in the PLL loop, shown on the picture >>>> for clarity. >>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in the >>>> register of 0x16). >>>> But, I think, for the RxPLL will be better use of the current 2.4 mA, >>>> because the nearest noises more important for Rx (you should write 0x98 in >>>> the register 0x26). >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.osmocom.org/pipermail/umtrx/attachments/20120719/3859b1e8/attachment-0001.htm>