From jsn at bjtpartners.com Mon Jul 2 18:16:33 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Mon, 2 Jul 2012 20:16:33 +0200 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Andrey, I have some news from the fab today and I have a meeting with them tomorrow morning. They sent me the BOM with components price list. This bring me a few questions. 1/ Would you know a distributor for the Murata chokes ? The fab them to have some issue to source these. 2/ Would you suggest a distributor for the GPS chip ? 3/ The CY7C1460AV33-167AXI costs more than 50 Euros on the list ! I know SRAM is expensive but would you know where we could purchase this component at a lower price ? If not, do you think we could use a cheaper but equivalent SRAM chip ? 4/ The M25P64-VMF6 costs more than 20 Euros on the list ! This is huge for a 64M flash. Would you know where we could purchase this component at a lower price ? If not, do you think we could use a cheaper but equivalent flash chip ? Please let me know about this. This would help me a lot to move forward to the next sample production step. Thanks a lot for your help. Best regards. Jean-Samuel. :-) On Mon, Jun 18, 2012 at 11:19 AM, Jean-Samuel Najnudel - BJT PARTNERS SARL < jsn at bjtpartners.com> wrote: > Hi Andrey, > > I sent the files last week. The fab needs a few days to update its pricing > and launch the production process. > Anyway, I just called them today. Work is in progress. They will provide > me with some updates later this week. They confirm this should not take too > much time for production and they will anyway contact me if they need > anything. > I will let you know asap. > > Best regards. > > Jean-Samuel. > :-) > > > > On Mon, Jun 18, 2012 at 9:49 AM, Andrey Sviyazov wrote: > >> Hi Jean-Samuel. >> >> Took another week, but still no news from you. >> Could you please inform us about the progress in the production of >> prototypes. >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/6/13 Andrey Sviyazov >> >>> Hi Jean-Samuel. >>> >>> Please inform us about fabrication progress even there are no issues. >>> >>> Best regards, >>> Andrey Sviyazov. >>> (Sent from my mobile client) >>> 12.06.2012 4:48 ???????????? "Andrey Sviyazov" >>> ???????: >>> >>> Here PcbDoc file @ 12/06/2012 . >>>> So, it all done :) >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> >>>> >>>> 2012/6/12 Andrey Sviyazov >>>> >>>>> Hi all! >>>>> >>>>> Here final project UmTRXv2 @ 12/06/2012 (PcbDoc file will be attached >>>>> to the next e-mail). >>>>> I found an mistake with non-SMD LED's positions in compare to Ettus >>>>> where A-B in left-to-right orientation (see picture). >>>>> Andrew Karpenkov suggested me to change it because of it is not yet >>>>> standard but people accustomed to this. >>>>> It is done. >>>>> >>>>> Also he suggest me to make four test points for RXOUT legs of LMS >>>>> because he work with this now and found it helpfull. >>>>> It is done. >>>>> >>>>> Also test points which without connector now referenced as TST and >>>>> therefore RefDes of some connectors changed. >>>>> >>>>> Jean-Samuel, please find Gerber files, NC drill and layer stack >>>>> desription files which usually required to produce PCB. >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> >>>>> >>>>> 2012/6/10 Andrey Sviyazov >>>>> >>>>>> Hi all! >>>>>> >>>>>> Here final project UmTRXv2 @ 10/06/2012 (PcbDoc file will be attached >>>>>> to the next e-mail). >>>>>> Jean-Samuel, please check SMD LED's placed at the front edge of the >>>>>> PCB. >>>>>> If you agree with this variant then I'll generate Gerber files vs >>>>>> required layers and description to produce PCB. >>>>>> If anybody find any mistake, please inform me immediatelly. >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> >>>>> >>>>> >>>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Mon Jul 2 23:10:54 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Tue, 3 Jul 2012 00:10:54 +0100 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Jean-Samuel, Thank you for the update! Andrey and I have just arrived back to Moscow, hopefully he will be able to answer tomorrow. Few questions from me: 1. Have they started PCB manufacturing already? With 3w of manufacturing time it would be better to start manufacturing asap. 2. Have you contacted Lime to get more LMS chips? Sent from my Android device. -- Regards, Alexander Chemeris CEO, Fairwaves LLC http://fairwaves.ru 02.07.2012 22:16 ???????????? "Jean-Samuel Najnudel - BJT PARTNERS SARL" < jsn at bjtpartners.com> ???????: > Hi Andrey, > > I have some news from the fab today and I have a meeting with them > tomorrow morning. > > They sent me the BOM with components price list. This bring me a few > questions. > > 1/ Would you know a distributor for the Murata chokes ? The fab them to > have some issue to source these. > > 2/ Would you suggest a distributor for the GPS chip ? > > 3/ The CY7C1460AV33-167AXI costs more than 50 Euros on the list ! I know > SRAM is expensive but would you know where we could purchase this component > at a lower price ? If not, do you think we could use a cheaper but > equivalent SRAM chip ? > > 4/ The M25P64-VMF6 costs more than 20 Euros on the list ! This is huge for > a 64M flash. Would you know where we could purchase this component at a > lower price ? If not, do you think we could use a cheaper but equivalent > flash chip ? > > Please let me know about this. This would help me a lot to move forward to > the next sample production step. > > Thanks a lot for your help. > > Best regards. > > Jean-Samuel. > :-) > > > On Mon, Jun 18, 2012 at 11:19 AM, Jean-Samuel Najnudel - BJT PARTNERS SARL > wrote: > >> Hi Andrey, >> >> I sent the files last week. The fab needs a few days to update its >> pricing and launch the production process. >> Anyway, I just called them today. Work is in progress. They will provide >> me with some updates later this week. They confirm this should not take too >> much time for production and they will anyway contact me if they need >> anything. >> I will let you know asap. >> >> Best regards. >> >> Jean-Samuel. >> :-) >> >> >> >> On Mon, Jun 18, 2012 at 9:49 AM, Andrey Sviyazov wrote: >> >>> Hi Jean-Samuel. >>> >>> Took another week, but still no news from you. >>> Could you please inform us about the progress in the production of >>> prototypes. >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/6/13 Andrey Sviyazov >>> >>>> Hi Jean-Samuel. >>>> >>>> Please inform us about fabrication progress even there are no issues. >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> (Sent from my mobile client) >>>> 12.06.2012 4:48 ???????????? "Andrey Sviyazov" >>>> ???????: >>>> >>>> Here PcbDoc file @ 12/06/2012 . >>>>> So, it all done :) >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> >>>>> >>>>> 2012/6/12 Andrey Sviyazov >>>>> >>>>>> Hi all! >>>>>> >>>>>> Here final project UmTRXv2 @ 12/06/2012 (PcbDoc file will be attached >>>>>> to the next e-mail). >>>>>> I found an mistake with non-SMD LED's positions in compare to Ettus >>>>>> where A-B in left-to-right orientation (see picture). >>>>>> Andrew Karpenkov suggested me to change it because of it is not yet >>>>>> standard but people accustomed to this. >>>>>> It is done. >>>>>> >>>>>> Also he suggest me to make four test points for RXOUT legs of LMS >>>>>> because he work with this now and found it helpfull. >>>>>> It is done. >>>>>> >>>>>> Also test points which without connector now referenced as TST and >>>>>> therefore RefDes of some connectors changed. >>>>>> >>>>>> Jean-Samuel, please find Gerber files, NC drill and layer stack >>>>>> desription files which usually required to produce PCB. >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> >>>>>> >>>>>> >>>>>> 2012/6/10 Andrey Sviyazov >>>>>> >>>>>>> Hi all! >>>>>>> >>>>>>> Here final project UmTRXv2 @ 10/06/2012 (PcbDoc file will be >>>>>>> attached to the next e-mail). >>>>>>> Jean-Samuel, please check SMD LED's placed at the front edge of the >>>>>>> PCB. >>>>>>> If you agree with this variant then I'll generate Gerber files vs >>>>>>> required layers and description to produce PCB. >>>>>>> If anybody find any mistake, please inform me immediatelly. >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> >>>>>> >>>>>> >>>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From jsn at bjtpartners.com Tue Jul 3 18:59:28 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Tue, 3 Jul 2012 20:59:28 +0200 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Alexander, Thank you very much for your e-mail. 1/ They did not started the PCB manufacturing yet. They are still waiting for my feedback on the questions I asked to Andrey. Actually, if we need to replace the SRAM and/or the flash to use cheaper equivalent components, we may need to reroute the PCB. This is why I ask them to wait for the feedback from Andrey before starting the PCB production. They can start as soon as we let them know what we do about the SRAM and the flash (with or without PCB files update). Anyway, I was not very worried about the delay. As discussed together last time in Paris, before deploying the UmTRX on the field, we would need OpenBTS to support handover. Even for tests, if I open the network without handover, because of the terrain in Mayotte, there will be so much call drops nobody in Mayotte will accept to use our network anymore in the future. Really, handover is very important in Mayotte. As I understand OpenBTS is under development but it is quite hard work. It will probably not be ready before the end of this summer. This is why I did not feel very worried about the PCB production delay. Anyway, I will do my best to get the UmTRX prototypes ready as soon as possible. I just need a feedback from Andrey because, if it does not lower the UmTRX board performances, we should really try to find an alternative solution to use cheaper SRAM and flash chips. This could improve a lot the cost structure of the UmTRX. 2/ I did not contacted Lime yet but I will do this as soon as possible. I will do my best to get the LMS chips on time. By the way, for both PCB assembly and LMS order, how many UmTRX board would you like the fab makes ? We discussed together about 5 or 10 units but we did not took the final decision yet. It can be any reasonable number between 5 and 10. Please let me know the quantity you would need. I will ask the fab and order the component quantities we need. By the way, the meeting with the fab this morning was fine and they are ready to start the production asap. Andrey, please let me know your feedback about my last e-mail and I will push this to the fab asap. Thanks a lot for your help. Best regards. Jean-Samuel. :-) On 7/3/12, Alexander Chemeris wrote: > Hi Jean-Samuel, > > Thank you for the update! Andrey and I have just arrived back to Moscow, > hopefully he will be able to answer tomorrow. > > Few questions from me: > > 1. Have they started PCB manufacturing already? With 3w of manufacturing > time it would be better to start manufacturing asap. > > 2. Have you contacted Lime to get more LMS chips? > > Sent from my Android device. > > -- > Regards, > Alexander Chemeris > CEO, Fairwaves LLC > http://fairwaves.ru > 02.07.2012 22:16 ???????????? "Jean-Samuel Najnudel - BJT PARTNERS SARL" < > jsn at bjtpartners.com> ???????: > >> Hi Andrey, >> >> I have some news from the fab today and I have a meeting with them >> tomorrow morning. >> >> They sent me the BOM with components price list. This bring me a few >> questions. >> >> 1/ Would you know a distributor for the Murata chokes ? The fab them to >> have some issue to source these. >> >> 2/ Would you suggest a distributor for the GPS chip ? >> >> 3/ The CY7C1460AV33-167AXI costs more than 50 Euros on the list ! I know >> SRAM is expensive but would you know where we could purchase this >> component >> at a lower price ? If not, do you think we could use a cheaper but >> equivalent SRAM chip ? >> >> 4/ The M25P64-VMF6 costs more than 20 Euros on the list ! This is huge >> for >> a 64M flash. Would you know where we could purchase this component at a >> lower price ? If not, do you think we could use a cheaper but equivalent >> flash chip ? >> >> Please let me know about this. This would help me a lot to move forward >> to >> the next sample production step. >> >> Thanks a lot for your help. >> >> Best regards. >> >> Jean-Samuel. >> :-) >> >> >> On Mon, Jun 18, 2012 at 11:19 AM, Jean-Samuel Najnudel - BJT PARTNERS >> SARL >> wrote: >> >>> Hi Andrey, >>> >>> I sent the files last week. The fab needs a few days to update its >>> pricing and launch the production process. >>> Anyway, I just called them today. Work is in progress. They will provide >>> me with some updates later this week. They confirm this should not take >>> too >>> much time for production and they will anyway contact me if they need >>> anything. >>> I will let you know asap. >>> >>> Best regards. >>> >>> Jean-Samuel. >>> :-) >>> >>> >>> >>> On Mon, Jun 18, 2012 at 9:49 AM, Andrey Sviyazov >>> wrote: >>> >>>> Hi Jean-Samuel. >>>> >>>> Took another week, but still no news from you. >>>> Could you please inform us about the progress in the production of >>>> prototypes. >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> >>>> >>>> 2012/6/13 Andrey Sviyazov >>>> >>>>> Hi Jean-Samuel. >>>>> >>>>> Please inform us about fabrication progress even there are no issues. >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> (Sent from my mobile client) >>>>> 12.06.2012 4:48 ???????????? "Andrey Sviyazov" >>>>> >>>>> ???????: >>>>> >>>>> Here PcbDoc file @ 12/06/2012 . >>>>>> So, it all done :) >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> >>>>>> >>>>>> >>>>>> 2012/6/12 Andrey Sviyazov >>>>>> >>>>>>> Hi all! >>>>>>> >>>>>>> Here final project UmTRXv2 @ 12/06/2012 (PcbDoc file will be >>>>>>> attached >>>>>>> to the next e-mail). >>>>>>> I found an mistake with non-SMD LED's positions in compare to Ettus >>>>>>> where A-B in left-to-right orientation (see picture). >>>>>>> Andrew Karpenkov suggested me to change it because of it is not yet >>>>>>> standard but people accustomed to this. >>>>>>> It is done. >>>>>>> >>>>>>> Also he suggest me to make four test points for RXOUT legs of LMS >>>>>>> because he work with this now and found it helpfull. >>>>>>> It is done. >>>>>>> >>>>>>> Also test points which without connector now referenced as TST and >>>>>>> therefore RefDes of some connectors changed. >>>>>>> >>>>>>> Jean-Samuel, please find Gerber files, NC drill and layer stack >>>>>>> desription files which usually required to produce PCB. >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> >>>>>>> >>>>>>> >>>>>>> 2012/6/10 Andrey Sviyazov >>>>>>> >>>>>>>> Hi all! >>>>>>>> >>>>>>>> Here final project UmTRXv2 @ 10/06/2012 (PcbDoc file will be >>>>>>>> attached to the next e-mail). >>>>>>>> Jean-Samuel, please check SMD LED's placed at the front edge of the >>>>>>>> PCB. >>>>>>>> If you agree with this variant then I'll generate Gerber files vs >>>>>>>> required layers and description to produce PCB. >>>>>>>> If anybody find any mistake, please inform me immediatelly. >>>>>>>> >>>>>>>> Best regards, >>>>>>>> Andrey Sviyazov. >>>>>>>> >>>>>>> >>>>>>> >>>>>> >>>> >>> >> > From jsn at bjtpartners.com Tue Jul 3 20:13:12 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Tue, 3 Jul 2012 22:13:12 +0200 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Andrey, I have some updates regarding the M25P64-VMF6. Please confirm the M25P64-VMF6P would be fine. If yes, we can find this at less than 2 Euros. There is no problem. This component is fine and we do not need to replace it on the PCB. If not, please let me know which other part number could be fine. This would help me to find this component at a good price. By the way, just a question, some distributors (eg: mouser) show this component as obsolete. What do you think ? Are you sure we will not have any problem to get this component for volume production in the future ? Please let me know. Best regards. Jean-Samuel. :-) On 7/3/12, Jean-Samuel Najnudel - BJT PARTNERS SARL wrote: > Hi Alexander, > > Thank you very much for your e-mail. > > 1/ They did not started the PCB manufacturing yet. They are still > waiting for my feedback on the questions I asked to Andrey. > > Actually, if we need to replace the SRAM and/or the flash to use > cheaper equivalent components, we may need to reroute the PCB. This is > why I ask them to wait for the feedback from Andrey before starting > the PCB production. They can start as soon as we let them know what we > do about the SRAM and the flash (with or without PCB files update). > > Anyway, I was not very worried about the delay. As discussed together > last time in Paris, before deploying the UmTRX on the field, we would > need OpenBTS to support handover. Even for tests, if I open the > network without handover, because of the terrain in Mayotte, there > will be so much call drops nobody in Mayotte will accept to use our > network anymore in the future. Really, handover is very important in > Mayotte. > > As I understand OpenBTS is under development but it is quite hard > work. It will probably not be ready before the end of this summer. > This is why I did not feel very worried about the PCB production > delay. > > Anyway, I will do my best to get the UmTRX prototypes ready as soon as > possible. I just need a feedback from Andrey because, if it does not > lower the UmTRX board performances, we should really try to find an > alternative solution to use cheaper SRAM and flash chips. This could > improve a lot the cost structure of the UmTRX. > > 2/ I did not contacted Lime yet but I will do this as soon as > possible. I will do my best to get the LMS chips on time. > > By the way, for both PCB assembly and LMS order, how many UmTRX board > would you like the fab makes ? We discussed together about 5 or 10 > units but we did not took the final decision yet. It can be any > reasonable number between 5 and 10. Please let me know the quantity > you would need. I will ask the fab and order the component quantities > we need. > > By the way, the meeting with the fab this morning was fine and they > are ready to start the production asap. > > Andrey, please let me know your feedback about my last e-mail and I > will push this to the fab asap. > > Thanks a lot for your help. > > Best regards. > > Jean-Samuel. > :-) > > > On 7/3/12, Alexander Chemeris wrote: >> Hi Jean-Samuel, >> >> Thank you for the update! Andrey and I have just arrived back to Moscow, >> hopefully he will be able to answer tomorrow. >> >> Few questions from me: >> >> 1. Have they started PCB manufacturing already? With 3w of manufacturing >> time it would be better to start manufacturing asap. >> >> 2. Have you contacted Lime to get more LMS chips? >> >> Sent from my Android device. >> >> -- >> Regards, >> Alexander Chemeris >> CEO, Fairwaves LLC >> http://fairwaves.ru >> 02.07.2012 22:16 ???????????? "Jean-Samuel Najnudel - BJT PARTNERS SARL" >> < >> jsn at bjtpartners.com> ???????: >> >>> Hi Andrey, >>> >>> I have some news from the fab today and I have a meeting with them >>> tomorrow morning. >>> >>> They sent me the BOM with components price list. This bring me a few >>> questions. >>> >>> 1/ Would you know a distributor for the Murata chokes ? The fab them to >>> have some issue to source these. >>> >>> 2/ Would you suggest a distributor for the GPS chip ? >>> >>> 3/ The CY7C1460AV33-167AXI costs more than 50 Euros on the list ! I know >>> SRAM is expensive but would you know where we could purchase this >>> component >>> at a lower price ? If not, do you think we could use a cheaper but >>> equivalent SRAM chip ? >>> >>> 4/ The M25P64-VMF6 costs more than 20 Euros on the list ! This is huge >>> for >>> a 64M flash. Would you know where we could purchase this component at a >>> lower price ? If not, do you think we could use a cheaper but equivalent >>> flash chip ? >>> >>> Please let me know about this. This would help me a lot to move forward >>> to >>> the next sample production step. >>> >>> Thanks a lot for your help. >>> >>> Best regards. >>> >>> Jean-Samuel. >>> :-) >>> >>> >>> On Mon, Jun 18, 2012 at 11:19 AM, Jean-Samuel Najnudel - BJT PARTNERS >>> SARL >>> wrote: >>> >>>> Hi Andrey, >>>> >>>> I sent the files last week. The fab needs a few days to update its >>>> pricing and launch the production process. >>>> Anyway, I just called them today. Work is in progress. They will >>>> provide >>>> me with some updates later this week. They confirm this should not take >>>> too >>>> much time for production and they will anyway contact me if they need >>>> anything. >>>> I will let you know asap. >>>> >>>> Best regards. >>>> >>>> Jean-Samuel. >>>> :-) >>>> >>>> >>>> >>>> On Mon, Jun 18, 2012 at 9:49 AM, Andrey Sviyazov >>>> wrote: >>>> >>>>> Hi Jean-Samuel. >>>>> >>>>> Took another week, but still no news from you. >>>>> Could you please inform us about the progress in the production of >>>>> prototypes. >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> >>>>> >>>>> 2012/6/13 Andrey Sviyazov >>>>> >>>>>> Hi Jean-Samuel. >>>>>> >>>>>> Please inform us about fabrication progress even there are no issues. >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> (Sent from my mobile client) >>>>>> 12.06.2012 4:48 ???????????? "Andrey Sviyazov" >>>>>> >>>>>> ???????: >>>>>> >>>>>> Here PcbDoc file @ 12/06/2012 . >>>>>>> So, it all done :) >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> >>>>>>> >>>>>>> >>>>>>> 2012/6/12 Andrey Sviyazov >>>>>>> >>>>>>>> Hi all! >>>>>>>> >>>>>>>> Here final project UmTRXv2 @ 12/06/2012 (PcbDoc file will be >>>>>>>> attached >>>>>>>> to the next e-mail). >>>>>>>> I found an mistake with non-SMD LED's positions in compare to Ettus >>>>>>>> where A-B in left-to-right orientation (see picture). >>>>>>>> Andrew Karpenkov suggested me to change it because of it is not yet >>>>>>>> standard but people accustomed to this. >>>>>>>> It is done. >>>>>>>> >>>>>>>> Also he suggest me to make four test points for RXOUT legs of LMS >>>>>>>> because he work with this now and found it helpfull. >>>>>>>> It is done. >>>>>>>> >>>>>>>> Also test points which without connector now referenced as TST and >>>>>>>> therefore RefDes of some connectors changed. >>>>>>>> >>>>>>>> Jean-Samuel, please find Gerber files, NC drill and layer stack >>>>>>>> desription files which usually required to produce PCB. >>>>>>>> >>>>>>>> Best regards, >>>>>>>> Andrey Sviyazov. >>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>> 2012/6/10 Andrey Sviyazov >>>>>>>> >>>>>>>>> Hi all! >>>>>>>>> >>>>>>>>> Here final project UmTRXv2 @ 10/06/2012 (PcbDoc file will be >>>>>>>>> attached to the next e-mail). >>>>>>>>> Jean-Samuel, please check SMD LED's placed at the front edge of >>>>>>>>> the >>>>>>>>> PCB. >>>>>>>>> If you agree with this variant then I'll generate Gerber files vs >>>>>>>>> required layers and description to produce PCB. >>>>>>>>> If anybody find any mistake, please inform me immediatelly. >>>>>>>>> >>>>>>>>> Best regards, >>>>>>>>> Andrey Sviyazov. >>>>>>>>> >>>>>>>> >>>>>>>> >>>>>>> >>>>> >>>> >>> >> > From alexander.chemeris at gmail.com Tue Jul 3 20:18:19 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Wed, 4 Jul 2012 00:18:19 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Jean-Samuel, On Tue, Jul 3, 2012 at 10:59 PM, Jean-Samuel Najnudel - BJT PARTNERS SARL wrote: > Hi Alexander, > > Thank you very much for your e-mail. > > 1/ They did not started the PCB manufacturing yet. They are still > waiting for my feedback on the questions I asked to Andrey. > > Actually, if we need to replace the SRAM and/or the flash to use > cheaper equivalent components, we may need to reroute the PCB. This is > why I ask them to wait for the feedback from Andrey before starting > the PCB production. They can start as soon as we let them know what we > do about the SRAM and the flash (with or without PCB files update). > > Anyway, I was not very worried about the delay. As discussed together > last time in Paris, before deploying the UmTRX on the field, we would > need OpenBTS to support handover. Even for tests, if I open the > network without handover, because of the terrain in Mayotte, there > will be so much call drops nobody in Mayotte will accept to use our > network anymore in the future. Really, handover is very important in > Mayotte. > > As I understand OpenBTS is under development but it is quite hard > work. It will probably not be ready before the end of this summer. > This is why I did not feel very worried about the PCB production > delay. We really need to get prototypes ASAP for many reasons - we have to start certification process, we still need to find enclosures, we have other pilots pending, etc. And every week of delay is painful for us. > Anyway, I will do my best to get the UmTRX prototypes ready as soon as > possible. I just need a feedback from Andrey because, if it does not > lower the UmTRX board performances, we should really try to find an > alternative solution to use cheaper SRAM and flash chips. This could > improve a lot the cost structure of the UmTRX. We should be fine with this chip: http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 (with no PCB changes). > 2/ I did not contacted Lime yet but I will do this as soon as > possible. I will do my best to get the LMS chips on time. > > By the way, for both PCB assembly and LMS order, how many UmTRX board > would you like the fab makes ? We discussed together about 5 or 10 > units but we did not took the final decision yet. It can be any > reasonable number between 5 and 10. Please let me know the quantity > you would need. I will ask the fab and order the component quantities > we need. We have only 5 FPGAs left, so I think we should assembly 5 prototypes. I.e. we need 10 LMS chips. But we could safely order more PCBs, because we're pretty sure PCB won't change. > By the way, the meeting with the fab this morning was fine and they > are ready to start the production asap. Please, start PCB manufacturing ASAP. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From jsn at bjtpartners.com Tue Jul 3 20:36:42 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Tue, 3 Jul 2012 22:36:42 +0200 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Alexander, On 7/3/12, Alexander Chemeris wrote: > Hi Jean-Samuel, > > On Tue, Jul 3, 2012 at 10:59 PM, Jean-Samuel Najnudel - BJT PARTNERS > SARL wrote: >> Hi Alexander, >> >> Thank you very much for your e-mail. >> >> 1/ They did not started the PCB manufacturing yet. They are still >> waiting for my feedback on the questions I asked to Andrey. >> >> Actually, if we need to replace the SRAM and/or the flash to use >> cheaper equivalent components, we may need to reroute the PCB. This is >> why I ask them to wait for the feedback from Andrey before starting >> the PCB production. They can start as soon as we let them know what we >> do about the SRAM and the flash (with or without PCB files update). >> >> Anyway, I was not very worried about the delay. As discussed together >> last time in Paris, before deploying the UmTRX on the field, we would >> need OpenBTS to support handover. Even for tests, if I open the >> network without handover, because of the terrain in Mayotte, there >> will be so much call drops nobody in Mayotte will accept to use our >> network anymore in the future. Really, handover is very important in >> Mayotte. >> >> As I understand OpenBTS is under development but it is quite hard >> work. It will probably not be ready before the end of this summer. >> This is why I did not feel very worried about the PCB production >> delay. > > We really need to get prototypes ASAP for many reasons - we have to > start certification process, we still need to find enclosures, we have > other pilots pending, etc. And every week of delay is painful for us. Ok. I will ask the fab to start the production ASAP. > >> Anyway, I will do my best to get the UmTRX prototypes ready as soon as >> possible. I just need a feedback from Andrey because, if it does not >> lower the UmTRX board performances, we should really try to find an >> alternative solution to use cheaper SRAM and flash chips. This could >> improve a lot the cost structure of the UmTRX. > > We should be fine with this chip: > http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 > (with no PCB changes). This looks good. However, this SRAM is 18 MBits instead of 36 MBits. This makes a quite big difference. Are you sure this will be fine ? Andrey, do you confirm this is fine ? Is this chip fully pin compatible ? > >> 2/ I did not contacted Lime yet but I will do this as soon as >> possible. I will do my best to get the LMS chips on time. >> >> By the way, for both PCB assembly and LMS order, how many UmTRX board >> would you like the fab makes ? We discussed together about 5 or 10 >> units but we did not took the final decision yet. It can be any >> reasonable number between 5 and 10. Please let me know the quantity >> you would need. I will ask the fab and order the component quantities >> we need. > > We have only 5 FPGAs left, so I think we should assembly 5 prototypes. > I.e. we need 10 LMS chips. This is fine for me. I will do this. > > But we could safely order more PCBs, because we're pretty sure PCB won't > change. Yes, for sure I will. You are completly right. I asked for the price. There is only about 100 Euros difference in total between 5 and 20 PCB. Moreover, ordering 20 PCB will save us a lot on next batches. It will also save us a lot of valuable time if we need some more prototypes. Actually, the PCB is what makes the production quite long. Anyway, I ask the fab will move toward the production asap. Best regards. Jean-Samuel. :-) > >> By the way, the meeting with the fab this morning was fine and they >> are ready to start the production asap. > > Please, start PCB manufacturing ASAP. > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > From alexander.chemeris at gmail.com Tue Jul 3 20:39:36 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Wed, 4 Jul 2012 00:39:36 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: On Wed, Jul 4, 2012 at 12:36 AM, Jean-Samuel Najnudel - BJT PARTNERS SARL wrote: > Hi Alexander, > > On 7/3/12, Alexander Chemeris wrote: >> Hi Jean-Samuel, >> >> We should be fine with this chip: >> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >> (with no PCB changes). > > This looks good. However, this SRAM is 18 MBits instead of 36 MBits. > This makes a quite big difference. > Are you sure this will be fine ? > Andrey, do you confirm this is fine ? Is this chip fully pin compatible ? 18Mbit is fine, but I was wrong with the pin compatibility. Now looking at other options. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Tue Jul 3 20:59:58 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Wed, 4 Jul 2012 00:59:58 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: On Wed, Jul 4, 2012 at 12:39 AM, Alexander Chemeris wrote: > On Wed, Jul 4, 2012 at 12:36 AM, Jean-Samuel Najnudel - BJT PARTNERS > SARL wrote: >> Hi Alexander, >> >> On 7/3/12, Alexander Chemeris wrote: >>> Hi Jean-Samuel, >>> >>> We should be fine with this chip: >>> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >>> (with no PCB changes). >> >> This looks good. However, this SRAM is 18 MBits instead of 36 MBits. >> This makes a quite big difference. >> Are you sure this will be fine ? >> Andrey, do you confirm this is fine ? Is this chip fully pin compatible ? > > 18Mbit is fine, but I was wrong with the pin compatibility. Now > looking at other options. I apologize again - it _is_ pin-to-pin compatible. A photo at DigiKey messed things for me. But Andrey Sviyazov and Andrew Karpenkov checked with datasheet and confirm that it is a direct replacement. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Tue Jul 3 21:00:53 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Wed, 4 Jul 2012 01:00:53 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: On Wed, Jul 4, 2012 at 12:36 AM, Jean-Samuel Najnudel - BJT PARTNERS SARL wrote: >> But we could safely order more PCBs, because we're pretty sure PCB won't >> change. > > Yes, for sure I will. You are completly right. I asked for the price. > There is only about 100 Euros difference in total between 5 and 20 > PCB. > Moreover, ordering 20 PCB will save us a lot on next batches. It will > also save us a lot of valuable time if we need some more prototypes. > Actually, the PCB is what makes the production quite long. Sounds great. 20 PCBs should be enough for now. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Tue Jul 3 21:10:03 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Wed, 4 Jul 2012 01:10:03 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT PARTNERS SARL wrote: > 1/ Would you know a distributor for the Murata chokes ? The fab them to have > some issue to source these. Andrey is looking into this. > 2/ Would you suggest a distributor for the GPS chip ? Try contacting manufacturer directly: http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 They have a distributor in UK, but I think it might be easier to buy from the manufacturer directly: http://www.castlemicrowave.com/castle-contact.asp This chip is popular in Russia, so it is easy to source them here, shipping them to EU might be a pain in big batches, but I think we could send few chips for this prototyping batch if manufacturer's lead time is too long. Here it costs $14.50/chip for more then 16 chips: http://www.compel.ru/infosheet/TSI/EB-570/ -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Tue Jul 3 21:17:37 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Wed, 4 Jul 2012 01:17:37 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: M25P64-VMF6P is a RoHS version of M25P64-VMF6 and thus is fine. M25P64-VMF6TP should be fine as well (it's a packaging option). Check out p50 of the datasheet: http://www.farnell.com/datasheets/1499242.pdf On Wed, Jul 4, 2012 at 12:13 AM, Jean-Samuel Najnudel - BJT PARTNERS SARL wrote: > Hi Andrey, > > I have some updates regarding the M25P64-VMF6. > Please confirm the M25P64-VMF6P would be fine. > If yes, we can find this at less than 2 Euros. There is no problem. > This component is fine and we do not need to replace it on the PCB. > If not, please let me know which other part number could be fine. This > would help me to find this component at a good price. > > By the way, just a question, some distributors (eg: mouser) show this > component as obsolete. What do you think ? Are you sure we will not > have any problem to get this component for volume production in the > future ? > > Please let me know. > > Best regards. > > Jean-Samuel. > :-) > > > On 7/3/12, Jean-Samuel Najnudel - BJT PARTNERS SARL wrote: >> Hi Alexander, >> >> Thank you very much for your e-mail. >> >> 1/ They did not started the PCB manufacturing yet. They are still >> waiting for my feedback on the questions I asked to Andrey. >> >> Actually, if we need to replace the SRAM and/or the flash to use >> cheaper equivalent components, we may need to reroute the PCB. This is >> why I ask them to wait for the feedback from Andrey before starting >> the PCB production. They can start as soon as we let them know what we >> do about the SRAM and the flash (with or without PCB files update). >> >> Anyway, I was not very worried about the delay. As discussed together >> last time in Paris, before deploying the UmTRX on the field, we would >> need OpenBTS to support handover. Even for tests, if I open the >> network without handover, because of the terrain in Mayotte, there >> will be so much call drops nobody in Mayotte will accept to use our >> network anymore in the future. Really, handover is very important in >> Mayotte. >> >> As I understand OpenBTS is under development but it is quite hard >> work. It will probably not be ready before the end of this summer. >> This is why I did not feel very worried about the PCB production >> delay. >> >> Anyway, I will do my best to get the UmTRX prototypes ready as soon as >> possible. I just need a feedback from Andrey because, if it does not >> lower the UmTRX board performances, we should really try to find an >> alternative solution to use cheaper SRAM and flash chips. This could >> improve a lot the cost structure of the UmTRX. >> >> 2/ I did not contacted Lime yet but I will do this as soon as >> possible. I will do my best to get the LMS chips on time. >> >> By the way, for both PCB assembly and LMS order, how many UmTRX board >> would you like the fab makes ? We discussed together about 5 or 10 >> units but we did not took the final decision yet. It can be any >> reasonable number between 5 and 10. Please let me know the quantity >> you would need. I will ask the fab and order the component quantities >> we need. >> >> By the way, the meeting with the fab this morning was fine and they >> are ready to start the production asap. >> >> Andrey, please let me know your feedback about my last e-mail and I >> will push this to the fab asap. >> >> Thanks a lot for your help. >> >> Best regards. >> >> Jean-Samuel. >> :-) >> >> >> On 7/3/12, Alexander Chemeris wrote: >>> Hi Jean-Samuel, >>> >>> Thank you for the update! Andrey and I have just arrived back to Moscow, >>> hopefully he will be able to answer tomorrow. >>> >>> Few questions from me: >>> >>> 1. Have they started PCB manufacturing already? With 3w of manufacturing >>> time it would be better to start manufacturing asap. >>> >>> 2. Have you contacted Lime to get more LMS chips? >>> >>> Sent from my Android device. >>> >>> -- >>> Regards, >>> Alexander Chemeris >>> CEO, Fairwaves LLC >>> http://fairwaves.ru >>> 02.07.2012 22:16 ???????????? "Jean-Samuel Najnudel - BJT PARTNERS SARL" >>> < >>> jsn at bjtpartners.com> ???????: >>> >>>> Hi Andrey, >>>> >>>> I have some news from the fab today and I have a meeting with them >>>> tomorrow morning. >>>> >>>> They sent me the BOM with components price list. This bring me a few >>>> questions. >>>> >>>> 1/ Would you know a distributor for the Murata chokes ? The fab them to >>>> have some issue to source these. >>>> >>>> 2/ Would you suggest a distributor for the GPS chip ? >>>> >>>> 3/ The CY7C1460AV33-167AXI costs more than 50 Euros on the list ! I know >>>> SRAM is expensive but would you know where we could purchase this >>>> component >>>> at a lower price ? If not, do you think we could use a cheaper but >>>> equivalent SRAM chip ? >>>> >>>> 4/ The M25P64-VMF6 costs more than 20 Euros on the list ! This is huge >>>> for >>>> a 64M flash. Would you know where we could purchase this component at a >>>> lower price ? If not, do you think we could use a cheaper but equivalent >>>> flash chip ? >>>> >>>> Please let me know about this. This would help me a lot to move forward >>>> to >>>> the next sample production step. >>>> >>>> Thanks a lot for your help. >>>> >>>> Best regards. >>>> >>>> Jean-Samuel. >>>> :-) >>>> >>>> >>>> On Mon, Jun 18, 2012 at 11:19 AM, Jean-Samuel Najnudel - BJT PARTNERS >>>> SARL >>>> wrote: >>>> >>>>> Hi Andrey, >>>>> >>>>> I sent the files last week. The fab needs a few days to update its >>>>> pricing and launch the production process. >>>>> Anyway, I just called them today. Work is in progress. They will >>>>> provide >>>>> me with some updates later this week. They confirm this should not take >>>>> too >>>>> much time for production and they will anyway contact me if they need >>>>> anything. >>>>> I will let you know asap. >>>>> >>>>> Best regards. >>>>> >>>>> Jean-Samuel. >>>>> :-) >>>>> >>>>> >>>>> >>>>> On Mon, Jun 18, 2012 at 9:49 AM, Andrey Sviyazov >>>>> wrote: >>>>> >>>>>> Hi Jean-Samuel. >>>>>> >>>>>> Took another week, but still no news from you. >>>>>> Could you please inform us about the progress in the production of >>>>>> prototypes. >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> >>>>>> >>>>>> >>>>>> 2012/6/13 Andrey Sviyazov >>>>>> >>>>>>> Hi Jean-Samuel. >>>>>>> >>>>>>> Please inform us about fabrication progress even there are no issues. >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> (Sent from my mobile client) >>>>>>> 12.06.2012 4:48 ???????????? "Andrey Sviyazov" >>>>>>> >>>>>>> ???????: >>>>>>> >>>>>>> Here PcbDoc file @ 12/06/2012 . >>>>>>>> So, it all done :) >>>>>>>> >>>>>>>> Best regards, >>>>>>>> Andrey Sviyazov. >>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>> 2012/6/12 Andrey Sviyazov >>>>>>>> >>>>>>>>> Hi all! >>>>>>>>> >>>>>>>>> Here final project UmTRXv2 @ 12/06/2012 (PcbDoc file will be >>>>>>>>> attached >>>>>>>>> to the next e-mail). >>>>>>>>> I found an mistake with non-SMD LED's positions in compare to Ettus >>>>>>>>> where A-B in left-to-right orientation (see picture). >>>>>>>>> Andrew Karpenkov suggested me to change it because of it is not yet >>>>>>>>> standard but people accustomed to this. >>>>>>>>> It is done. >>>>>>>>> >>>>>>>>> Also he suggest me to make four test points for RXOUT legs of LMS >>>>>>>>> because he work with this now and found it helpfull. >>>>>>>>> It is done. >>>>>>>>> >>>>>>>>> Also test points which without connector now referenced as TST and >>>>>>>>> therefore RefDes of some connectors changed. >>>>>>>>> >>>>>>>>> Jean-Samuel, please find Gerber files, NC drill and layer stack >>>>>>>>> desription files which usually required to produce PCB. >>>>>>>>> >>>>>>>>> Best regards, >>>>>>>>> Andrey Sviyazov. >>>>>>>>> >>>>>>>>> >>>>>>>>> >>>>>>>>> 2012/6/10 Andrey Sviyazov >>>>>>>>> >>>>>>>>>> Hi all! >>>>>>>>>> >>>>>>>>>> Here final project UmTRXv2 @ 10/06/2012 (PcbDoc file will be >>>>>>>>>> attached to the next e-mail). >>>>>>>>>> Jean-Samuel, please check SMD LED's placed at the front edge of >>>>>>>>>> the >>>>>>>>>> PCB. >>>>>>>>>> If you agree with this variant then I'll generate Gerber files vs >>>>>>>>>> required layers and description to produce PCB. >>>>>>>>>> If anybody find any mistake, please inform me immediatelly. >>>>>>>>>> >>>>>>>>>> Best regards, >>>>>>>>>> Andrey Sviyazov. >>>>>>>>>> >>>>>>>>> >>>>>>>>> >>>>>>>> >>>>>> >>>>> >>>> >>> >> -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From andreysviyaz at gmail.com Tue Jul 3 21:22:10 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Wed, 4 Jul 2012 01:22:10 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Jean-Samuel. Unfortunately I have no internet connection now. Tomorrow I'll check flash and others. Best regards, Andrey Sviyazov. (Sent from my mobile client) 04.07.2012 1:10 ???????????? "Alexander Chemeris" < alexander.chemeris at gmail.com> ???????: > > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT PARTNERS > SARL wrote: > > 1/ Would you know a distributor for the Murata chokes ? The fab them to have > > some issue to source these. > > Andrey is looking into this. > > > 2/ Would you suggest a distributor for the GPS chip ? > > Try contacting manufacturer directly: > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 > > They have a distributor in UK, but I think it might be easier to buy > from the manufacturer directly: > http://www.castlemicrowave.com/castle-contact.asp > > This chip is popular in Russia, so it is easy to source them here, > shipping them to EU might be a pain in big batches, but I think we > could send few chips for this prototyping batch if manufacturer's lead > time is too long. Here it costs $14.50/chip for more then 16 chips: > http://www.compel.ru/infosheet/TSI/EB-570/ > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru -------------- next part -------------- An HTML attachment was scrubbed... URL: From andreysviyaz at gmail.com Tue Jul 3 21:40:48 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Wed, 4 Jul 2012 01:40:48 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Jean-Samuel. Please inform me what actually rf chockes partnumbers are problem to order. Unfortunately MuRata produce few billion pcs and then stopped for a few years. So, possible we have to find some Chinese fab partnumbers to order. Best regards, Andrey Sviyazov. (Sent from my mobile client) 04.07.2012 1:22 ???????????? "Andrey Sviyazov" ???????: > Hi Jean-Samuel. > Unfortunately I have no internet connection now. > Tomorrow I'll check flash and others. > > Best regards, > Andrey Sviyazov. > (Sent from my mobile client) > > 04.07.2012 1:10 ???????????? "Alexander Chemeris" < > alexander.chemeris at gmail.com> ???????: > > > > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT PARTNERS > > SARL wrote: > > > 1/ Would you know a distributor for the Murata chokes ? The fab them > to have > > > some issue to source these. > > > > Andrey is looking into this. > > > > > 2/ Would you suggest a distributor for the GPS chip ? > > > > Try contacting manufacturer directly: > > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 > > > > They have a distributor in UK, but I think it might be easier to buy > > from the manufacturer directly: > > http://www.castlemicrowave.com/castle-contact.asp > > > > This chip is popular in Russia, so it is easy to source them here, > > shipping them to EU might be a pain in big batches, but I think we > > could send few chips for this prototyping batch if manufacturer's lead > > time is too long. Here it costs $14.50/chip for more then 16 chips: > > http://www.compel.ru/infosheet/TSI/EB-570/ > > > > -- > > Regards, > > Alexander Chemeris. > > CEO, Fairwaves LLC / ??? ??????? > > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: From jsn at bjtpartners.com Wed Jul 4 10:24:19 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Wed, 4 Jul 2012 12:24:19 +0200 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Alexander, Thank you very much for your advice. Price looks fine but Compel.ru web site is all in Russian. It is not very easy for me to order. Would you know another online store that would have English order web pages ? Thanks a lot for your help. Best regards. Jean-Samuel. :-) On Tue, Jul 3, 2012 at 11:10 PM, Alexander Chemeris < alexander.chemeris at gmail.com> wrote: > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT PARTNERS > SARL wrote: > > 1/ Would you know a distributor for the Murata chokes ? The fab them to > have > > some issue to source these. > > Andrey is looking into this. > > > 2/ Would you suggest a distributor for the GPS chip ? > > Try contacting manufacturer directly: > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 > > They have a distributor in UK, but I think it might be easier to buy > from the manufacturer directly: > http://www.castlemicrowave.com/castle-contact.asp > > This chip is popular in Russia, so it is easy to source them here, > shipping them to EU might be a pain in big batches, but I think we > could send few chips for this prototyping batch if manufacturer's lead > time is too long. Here it costs $14.50/chip for more then 16 chips: > http://www.compel.ru/infosheet/TSI/EB-570/ > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: From jsn at bjtpartners.com Wed Jul 4 10:28:04 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Wed, 4 Jul 2012 12:28:04 +0200 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Alexander, Thanks a lot for your reply. This is good news. The M25P64-VMF6P costs less than 2 Euros on Avnet Express. By the way, now I understand why the fab quoted me more than 20 Euros for this flash. Farnell France seems to sell this at 21.38 Euros ! Anyway, no problem. I will order through Avnet Express. Best regards. Jean-Samuel. :-) On Tue, Jul 3, 2012 at 11:17 PM, Alexander Chemeris < alexander.chemeris at gmail.com> wrote: > M25P64-VMF6P is a RoHS version of M25P64-VMF6 and thus is fine. > M25P64-VMF6TP should be fine as well (it's a packaging option). Check > out p50 of the datasheet: > http://www.farnell.com/datasheets/1499242.pdf > > On Wed, Jul 4, 2012 at 12:13 AM, Jean-Samuel Najnudel - BJT PARTNERS > SARL wrote: > > Hi Andrey, > > > > I have some updates regarding the M25P64-VMF6. > > Please confirm the M25P64-VMF6P would be fine. > > If yes, we can find this at less than 2 Euros. There is no problem. > > This component is fine and we do not need to replace it on the PCB. > > If not, please let me know which other part number could be fine. This > > would help me to find this component at a good price. > > > > By the way, just a question, some distributors (eg: mouser) show this > > component as obsolete. What do you think ? Are you sure we will not > > have any problem to get this component for volume production in the > > future ? > > > > Please let me know. > > > > Best regards. > > > > Jean-Samuel. > > :-) > > > > > > On 7/3/12, Jean-Samuel Najnudel - BJT PARTNERS SARL > wrote: > >> Hi Alexander, > >> > >> Thank you very much for your e-mail. > >> > >> 1/ They did not started the PCB manufacturing yet. They are still > >> waiting for my feedback on the questions I asked to Andrey. > >> > >> Actually, if we need to replace the SRAM and/or the flash to use > >> cheaper equivalent components, we may need to reroute the PCB. This is > >> why I ask them to wait for the feedback from Andrey before starting > >> the PCB production. They can start as soon as we let them know what we > >> do about the SRAM and the flash (with or without PCB files update). > >> > >> Anyway, I was not very worried about the delay. As discussed together > >> last time in Paris, before deploying the UmTRX on the field, we would > >> need OpenBTS to support handover. Even for tests, if I open the > >> network without handover, because of the terrain in Mayotte, there > >> will be so much call drops nobody in Mayotte will accept to use our > >> network anymore in the future. Really, handover is very important in > >> Mayotte. > >> > >> As I understand OpenBTS is under development but it is quite hard > >> work. It will probably not be ready before the end of this summer. > >> This is why I did not feel very worried about the PCB production > >> delay. > >> > >> Anyway, I will do my best to get the UmTRX prototypes ready as soon as > >> possible. I just need a feedback from Andrey because, if it does not > >> lower the UmTRX board performances, we should really try to find an > >> alternative solution to use cheaper SRAM and flash chips. This could > >> improve a lot the cost structure of the UmTRX. > >> > >> 2/ I did not contacted Lime yet but I will do this as soon as > >> possible. I will do my best to get the LMS chips on time. > >> > >> By the way, for both PCB assembly and LMS order, how many UmTRX board > >> would you like the fab makes ? We discussed together about 5 or 10 > >> units but we did not took the final decision yet. It can be any > >> reasonable number between 5 and 10. Please let me know the quantity > >> you would need. I will ask the fab and order the component quantities > >> we need. > >> > >> By the way, the meeting with the fab this morning was fine and they > >> are ready to start the production asap. > >> > >> Andrey, please let me know your feedback about my last e-mail and I > >> will push this to the fab asap. > >> > >> Thanks a lot for your help. > >> > >> Best regards. > >> > >> Jean-Samuel. > >> :-) > >> > >> > >> On 7/3/12, Alexander Chemeris wrote: > >>> Hi Jean-Samuel, > >>> > >>> Thank you for the update! Andrey and I have just arrived back to > Moscow, > >>> hopefully he will be able to answer tomorrow. > >>> > >>> Few questions from me: > >>> > >>> 1. Have they started PCB manufacturing already? With 3w of > manufacturing > >>> time it would be better to start manufacturing asap. > >>> > >>> 2. Have you contacted Lime to get more LMS chips? > >>> > >>> Sent from my Android device. > >>> > >>> -- > >>> Regards, > >>> Alexander Chemeris > >>> CEO, Fairwaves LLC > >>> http://fairwaves.ru > >>> 02.07.2012 22:16 ???????????? "Jean-Samuel Najnudel - BJT PARTNERS > SARL" > >>> < > >>> jsn at bjtpartners.com> ???????: > >>> > >>>> Hi Andrey, > >>>> > >>>> I have some news from the fab today and I have a meeting with them > >>>> tomorrow morning. > >>>> > >>>> They sent me the BOM with components price list. This bring me a few > >>>> questions. > >>>> > >>>> 1/ Would you know a distributor for the Murata chokes ? The fab them > to > >>>> have some issue to source these. > >>>> > >>>> 2/ Would you suggest a distributor for the GPS chip ? > >>>> > >>>> 3/ The CY7C1460AV33-167AXI costs more than 50 Euros on the list ! I > know > >>>> SRAM is expensive but would you know where we could purchase this > >>>> component > >>>> at a lower price ? If not, do you think we could use a cheaper but > >>>> equivalent SRAM chip ? > >>>> > >>>> 4/ The M25P64-VMF6 costs more than 20 Euros on the list ! This is huge > >>>> for > >>>> a 64M flash. Would you know where we could purchase this component at > a > >>>> lower price ? If not, do you think we could use a cheaper but > equivalent > >>>> flash chip ? > >>>> > >>>> Please let me know about this. This would help me a lot to move > forward > >>>> to > >>>> the next sample production step. > >>>> > >>>> Thanks a lot for your help. > >>>> > >>>> Best regards. > >>>> > >>>> Jean-Samuel. > >>>> :-) > >>>> > >>>> > >>>> On Mon, Jun 18, 2012 at 11:19 AM, Jean-Samuel Najnudel - BJT PARTNERS > >>>> SARL > >>>> wrote: > >>>> > >>>>> Hi Andrey, > >>>>> > >>>>> I sent the files last week. The fab needs a few days to update its > >>>>> pricing and launch the production process. > >>>>> Anyway, I just called them today. Work is in progress. They will > >>>>> provide > >>>>> me with some updates later this week. They confirm this should not > take > >>>>> too > >>>>> much time for production and they will anyway contact me if they need > >>>>> anything. > >>>>> I will let you know asap. > >>>>> > >>>>> Best regards. > >>>>> > >>>>> Jean-Samuel. > >>>>> :-) > >>>>> > >>>>> > >>>>> > >>>>> On Mon, Jun 18, 2012 at 9:49 AM, Andrey Sviyazov > >>>>> wrote: > >>>>> > >>>>>> Hi Jean-Samuel. > >>>>>> > >>>>>> Took another week, but still no news from you. > >>>>>> Could you please inform us about the progress in the production of > >>>>>> prototypes. > >>>>>> > >>>>>> Best regards, > >>>>>> Andrey Sviyazov. > >>>>>> > >>>>>> > >>>>>> > >>>>>> 2012/6/13 Andrey Sviyazov > >>>>>> > >>>>>>> Hi Jean-Samuel. > >>>>>>> > >>>>>>> Please inform us about fabrication progress even there are no > issues. > >>>>>>> > >>>>>>> Best regards, > >>>>>>> Andrey Sviyazov. > >>>>>>> (Sent from my mobile client) > >>>>>>> 12.06.2012 4:48 ???????????? "Andrey Sviyazov" > >>>>>>> > >>>>>>> ???????: > >>>>>>> > >>>>>>> Here PcbDoc file @ 12/06/2012 . > >>>>>>>> So, it all done :) > >>>>>>>> > >>>>>>>> Best regards, > >>>>>>>> Andrey Sviyazov. > >>>>>>>> > >>>>>>>> > >>>>>>>> > >>>>>>>> 2012/6/12 Andrey Sviyazov > >>>>>>>> > >>>>>>>>> Hi all! > >>>>>>>>> > >>>>>>>>> Here final project UmTRXv2 @ 12/06/2012 (PcbDoc file will be > >>>>>>>>> attached > >>>>>>>>> to the next e-mail). > >>>>>>>>> I found an mistake with non-SMD LED's positions in compare to > Ettus > >>>>>>>>> where A-B in left-to-right orientation (see picture). > >>>>>>>>> Andrew Karpenkov suggested me to change it because of it is not > yet > >>>>>>>>> standard but people accustomed to this. > >>>>>>>>> It is done. > >>>>>>>>> > >>>>>>>>> Also he suggest me to make four test points for RXOUT legs of LMS > >>>>>>>>> because he work with this now and found it helpfull. > >>>>>>>>> It is done. > >>>>>>>>> > >>>>>>>>> Also test points which without connector now referenced as TST > and > >>>>>>>>> therefore RefDes of some connectors changed. > >>>>>>>>> > >>>>>>>>> Jean-Samuel, please find Gerber files, NC drill and layer stack > >>>>>>>>> desription files which usually required to produce PCB. > >>>>>>>>> > >>>>>>>>> Best regards, > >>>>>>>>> Andrey Sviyazov. > >>>>>>>>> > >>>>>>>>> > >>>>>>>>> > >>>>>>>>> 2012/6/10 Andrey Sviyazov > >>>>>>>>> > >>>>>>>>>> Hi all! > >>>>>>>>>> > >>>>>>>>>> Here final project UmTRXv2 @ 10/06/2012 (PcbDoc file will be > >>>>>>>>>> attached to the next e-mail). > >>>>>>>>>> Jean-Samuel, please check SMD LED's placed at the front edge of > >>>>>>>>>> the > >>>>>>>>>> PCB. > >>>>>>>>>> If you agree with this variant then I'll generate Gerber files > vs > >>>>>>>>>> required layers and description to produce PCB. > >>>>>>>>>> If anybody find any mistake, please inform me immediatelly. > >>>>>>>>>> > >>>>>>>>>> Best regards, > >>>>>>>>>> Andrey Sviyazov. > >>>>>>>>>> > >>>>>>>>> > >>>>>>>>> > >>>>>>>> > >>>>>> > >>>>> > >>>> > >>> > >> > > > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: From jsn at bjtpartners.com Wed Jul 4 10:37:07 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Wed, 4 Jul 2012 12:37:07 +0200 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Andrey, Thank you very much for your reply. I try to find where to buy the TI160808U601 and TI201209-121 chokes. I do not know where I should find these. Would you know where I should order these components ? By the way, do you confirm the ISSI SRAM is pin compatible with the Cypress chip ? http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 Is this ISSI chip fine for our application ? Is 18 MBit enough ? Do you confirm this ISSI chip is the best value for what we need ? Are you sure we cannot find a lower cost chip with similar performances and/or a better performances chip with similar cost ? Are you sure we will not need to reroute the PCB ? We really need to be sure before starting the PCB production. If both you and Alexander confirm everything is fine, I will ask the fab to start the PCB. Please let me know. Again, thanks a lot for your help. Best regards. Jean-Samuel. :-) On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov wrote: > Jean-Samuel. > > Please inform me what actually rf chockes partnumbers are problem to order. > Unfortunately MuRata produce few billion pcs and then stopped for a few > years. > So, possible we have to find some Chinese fab partnumbers to order. > > Best regards, > Andrey Sviyazov. > (Sent from my mobile client) > 04.07.2012 1:22 ???????????? "Andrey Sviyazov" > ???????: > > Hi Jean-Samuel. >> Unfortunately I have no internet connection now. >> Tomorrow I'll check flash and others. >> >> Best regards, >> Andrey Sviyazov. >> (Sent from my mobile client) >> >> 04.07.2012 1:10 ???????????? "Alexander Chemeris" < >> alexander.chemeris at gmail.com> ???????: >> > >> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT PARTNERS >> > SARL wrote: >> > > 1/ Would you know a distributor for the Murata chokes ? The fab them >> to have >> > > some issue to source these. >> > >> > Andrey is looking into this. >> > >> > > 2/ Would you suggest a distributor for the GPS chip ? >> > >> > Try contacting manufacturer directly: >> > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >> > >> > They have a distributor in UK, but I think it might be easier to buy >> > from the manufacturer directly: >> > http://www.castlemicrowave.com/castle-contact.asp >> > >> > This chip is popular in Russia, so it is easy to source them here, >> > shipping them to EU might be a pain in big batches, but I think we >> > could send few chips for this prototyping batch if manufacturer's lead >> > time is too long. Here it costs $14.50/chip for more then 16 chips: >> > http://www.compel.ru/infosheet/TSI/EB-570/ >> > >> > -- >> > Regards, >> > Alexander Chemeris. >> > CEO, Fairwaves LLC / ??? ??????? >> > http://fairwaves.ru >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Wed Jul 4 12:01:50 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Wed, 4 Jul 2012 13:01:50 +0100 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Jean-Samuel, I sent you the link to Compel just for the reference, to give you an idea of price. As I mentioned, I recommend you to contact manufacturer directly. On Wed, Jul 4, 2012 at 11:24 AM, Jean-Samuel Najnudel - BJT PARTNERS SARL wrote: > Hi Alexander, > > Thank you very much for your advice. > Price looks fine but Compel.ru web site is all in Russian. It is not very > easy for me to order. > Would you know another online store that would have English order web pages > ? > > Thanks a lot for your help. > > Best regards. > > Jean-Samuel. > :-) > > > On Tue, Jul 3, 2012 at 11:10 PM, Alexander Chemeris > wrote: >> >> On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT PARTNERS >> SARL wrote: >> > 1/ Would you know a distributor for the Murata chokes ? The fab them to >> > have >> > some issue to source these. >> >> Andrey is looking into this. >> >> > 2/ Would you suggest a distributor for the GPS chip ? >> >> Try contacting manufacturer directly: >> http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >> >> They have a distributor in UK, but I think it might be easier to buy >> from the manufacturer directly: >> http://www.castlemicrowave.com/castle-contact.asp >> >> This chip is popular in Russia, so it is easy to source them here, >> shipping them to EU might be a pain in big batches, but I think we >> could send few chips for this prototyping batch if manufacturer's lead >> time is too long. Here it costs $14.50/chip for more then 16 chips: >> http://www.compel.ru/infosheet/TSI/EB-570/ >> >> -- >> Regards, >> Alexander Chemeris. >> CEO, Fairwaves LLC / ??? ??????? >> http://fairwaves.ru > > -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From andreysviyaz at gmail.com Wed Jul 4 12:02:14 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Wed, 4 Jul 2012 16:02:14 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Jean-Samuel. For the TI160808U601 and TI201209U121 you can use any high current ferrite chip bead with 600 Ohm and 120 Ohm impedance respectively. For example you could order similar partnumbers from the ELFAcatalogue in the 0603 and 0805 SMD cases respectively, datasheet here pdf . Best regards, Andrey Sviyazov. 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL > Hi Andrey, > > Thank you very much for your reply. > > I try to find where to buy the TI160808U601 and TI201209-121 chokes. I do > not know where I should find these. Would you know where I should order > these components ? > > By the way, do you confirm the ISSI SRAM is pin compatible with the > Cypress chip ? > > http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 > > Is this ISSI chip fine for our application ? Is 18 MBit enough ? > Do you confirm this ISSI chip is the best value for what we need ? Are you > sure we cannot find a lower cost chip with similar performances and/or a > better performances chip with similar cost ? > Are you sure we will not need to reroute the PCB ? > > We really need to be sure before starting the PCB production. If both you > and Alexander confirm everything is fine, I will ask the fab to start the > PCB. > > Please let me know. > > Again, thanks a lot for your help. > > Best regards. > > Jean-Samuel. > :-) > > > > On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov wrote: > >> Jean-Samuel. >> >> Please inform me what actually rf chockes partnumbers are problem to >> order. >> Unfortunately MuRata produce few billion pcs and then stopped for a few >> years. >> So, possible we have to find some Chinese fab partnumbers to order. >> >> Best regards, >> Andrey Sviyazov. >> (Sent from my mobile client) >> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" >> ???????: >> >> Hi Jean-Samuel. >>> Unfortunately I have no internet connection now. >>> Tomorrow I'll check flash and others. >>> >>> Best regards, >>> Andrey Sviyazov. >>> (Sent from my mobile client) >>> >>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" < >>> alexander.chemeris at gmail.com> ???????: >>> > >>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT PARTNERS >>> > SARL wrote: >>> > > 1/ Would you know a distributor for the Murata chokes ? The fab them >>> to have >>> > > some issue to source these. >>> > >>> > Andrey is looking into this. >>> > >>> > > 2/ Would you suggest a distributor for the GPS chip ? >>> > >>> > Try contacting manufacturer directly: >>> > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >>> > >>> > They have a distributor in UK, but I think it might be easier to buy >>> > from the manufacturer directly: >>> > http://www.castlemicrowave.com/castle-contact.asp >>> > >>> > This chip is popular in Russia, so it is easy to source them here, >>> > shipping them to EU might be a pain in big batches, but I think we >>> > could send few chips for this prototyping batch if manufacturer's lead >>> > time is too long. Here it costs $14.50/chip for more then 16 chips: >>> > http://www.compel.ru/infosheet/TSI/EB-570/ >>> > >>> > -- >>> > Regards, >>> > Alexander Chemeris. >>> > CEO, Fairwaves LLC / ??? ??????? >>> > http://fairwaves.ru >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From jsn at bjtpartners.com Wed Jul 4 12:20:29 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Wed, 4 Jul 2012 14:20:29 +0200 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Alexander, Thank you for your reply. I just contacted the manufacturer. I will let you know. Best regards. Jean-Samuel. :-) On Wed, Jul 4, 2012 at 2:01 PM, Alexander Chemeris < alexander.chemeris at gmail.com> wrote: > Jean-Samuel, > > I sent you the link to Compel just for the reference, to give you an > idea of price. As I mentioned, I recommend you to contact manufacturer > directly. > > On Wed, Jul 4, 2012 at 11:24 AM, Jean-Samuel Najnudel - BJT PARTNERS > SARL wrote: > > Hi Alexander, > > > > Thank you very much for your advice. > > Price looks fine but Compel.ru web site is all in Russian. It is not very > > easy for me to order. > > Would you know another online store that would have English order web > pages > > ? > > > > Thanks a lot for your help. > > > > Best regards. > > > > Jean-Samuel. > > :-) > > > > > > On Tue, Jul 3, 2012 at 11:10 PM, Alexander Chemeris > > wrote: > >> > >> On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT PARTNERS > >> SARL wrote: > >> > 1/ Would you know a distributor for the Murata chokes ? The fab them > to > >> > have > >> > some issue to source these. > >> > >> Andrey is looking into this. > >> > >> > 2/ Would you suggest a distributor for the GPS chip ? > >> > >> Try contacting manufacturer directly: > >> http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 > >> > >> They have a distributor in UK, but I think it might be easier to buy > >> from the manufacturer directly: > >> http://www.castlemicrowave.com/castle-contact.asp > >> > >> This chip is popular in Russia, so it is easy to source them here, > >> shipping them to EU might be a pain in big batches, but I think we > >> could send few chips for this prototyping batch if manufacturer's lead > >> time is too long. Here it costs $14.50/chip for more then 16 chips: > >> http://www.compel.ru/infosheet/TSI/EB-570/ > >> > >> -- > >> Regards, > >> Alexander Chemeris. > >> CEO, Fairwaves LLC / ??? ??????? > >> http://fairwaves.ru > > > > > > > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andreysviyaz at gmail.com Wed Jul 4 12:23:06 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Wed, 4 Jul 2012 16:23:06 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Jean-Samuel. About SRAM which I've found from ISSI I'm sure that it full compatible and of cause we are discussed with Andrew Karpenkov and Alexander Chemeris that 18Mbit size should be enough. And also I think you should order exactly this 0603 and 0805 chip beads instead of TI160808U601 and TI201209U121 as I mentioned and do not spend time for search. Best regards, Andrey Sviyazov. 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL > Hi Andrey, > > Thank you very much for your reply. > > I try to find where to buy the TI160808U601 and TI201209-121 chokes. I do > not know where I should find these. Would you know where I should order > these components ? > > By the way, do you confirm the ISSI SRAM is pin compatible with the > Cypress chip ? > > http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 > > Is this ISSI chip fine for our application ? Is 18 MBit enough ? > Do you confirm this ISSI chip is the best value for what we need ? Are you > sure we cannot find a lower cost chip with similar performances and/or a > better performances chip with similar cost ? > Are you sure we will not need to reroute the PCB ? > > We really need to be sure before starting the PCB production. If both you > and Alexander confirm everything is fine, I will ask the fab to start the > PCB. > > Please let me know. > > Again, thanks a lot for your help. > > Best regards. > > Jean-Samuel. > :-) > > > > On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov wrote: > >> Jean-Samuel. >> >> Please inform me what actually rf chockes partnumbers are problem to >> order. >> Unfortunately MuRata produce few billion pcs and then stopped for a few >> years. >> So, possible we have to find some Chinese fab partnumbers to order. >> >> Best regards, >> Andrey Sviyazov. >> (Sent from my mobile client) >> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" >> ???????: >> >> Hi Jean-Samuel. >>> Unfortunately I have no internet connection now. >>> Tomorrow I'll check flash and others. >>> >>> Best regards, >>> Andrey Sviyazov. >>> (Sent from my mobile client) >>> >>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" < >>> alexander.chemeris at gmail.com> ???????: >>> > >>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT PARTNERS >>> > SARL wrote: >>> > > 1/ Would you know a distributor for the Murata chokes ? The fab them >>> to have >>> > > some issue to source these. >>> > >>> > Andrey is looking into this. >>> > >>> > > 2/ Would you suggest a distributor for the GPS chip ? >>> > >>> > Try contacting manufacturer directly: >>> > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >>> > >>> > They have a distributor in UK, but I think it might be easier to buy >>> > from the manufacturer directly: >>> > http://www.castlemicrowave.com/castle-contact.asp >>> > >>> > This chip is popular in Russia, so it is easy to source them here, >>> > shipping them to EU might be a pain in big batches, but I think we >>> > could send few chips for this prototyping batch if manufacturer's lead >>> > time is too long. Here it costs $14.50/chip for more then 16 chips: >>> > http://www.compel.ru/infosheet/TSI/EB-570/ >>> > >>> > -- >>> > Regards, >>> > Alexander Chemeris. >>> > CEO, Fairwaves LLC / ??? ??????? >>> > http://fairwaves.ru >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From jsn at bjtpartners.com Wed Jul 4 12:25:10 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Wed, 4 Jul 2012 14:25:10 +0200 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Andrey, Thank you very much for your reply. Could you please confirm the components bellow are fine ? http://fr.farnell.com/murata/blm18tg601tn1d/ferrite-600ohm/dp/1115050RL http://fr.farnell.com/tdk/mmz2012121b/perle-de-ferrite-0805-120-ohm/dp/1669728RL Please let me know if this is fine. If not, which would you suggest ? http://ru.farnell.com/ferrite-beads Thanks a lot for your help. Best regards. Jean-Samuel. :-) On Wed, Jul 4, 2012 at 2:02 PM, Andrey Sviyazov wrote: > Hi Jean-Samuel. > > For the TI160808U601 and TI201209U121 you can use any high current ferrite > chip bead with 600 Ohm and 120 Ohm impedance respectively. > For example you could order similar partnumbers from the ELFAcatalogue in the > 0603and > 0805 SMD > cases respectively, datasheet here pdf > . > > Best regards, > Andrey Sviyazov. > > > > 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL > >> Hi Andrey, >> >> Thank you very much for your reply. >> >> I try to find where to buy the TI160808U601 and TI201209-121 chokes. I do >> not know where I should find these. Would you know where I should order >> these components ? >> >> By the way, do you confirm the ISSI SRAM is pin compatible with the >> Cypress chip ? >> >> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >> >> Is this ISSI chip fine for our application ? Is 18 MBit enough ? >> Do you confirm this ISSI chip is the best value for what we need ? Are >> you sure we cannot find a lower cost chip with similar performances and/or >> a better performances chip with similar cost ? >> Are you sure we will not need to reroute the PCB ? >> >> We really need to be sure before starting the PCB production. If both you >> and Alexander confirm everything is fine, I will ask the fab to start the >> PCB. >> >> Please let me know. >> >> Again, thanks a lot for your help. >> >> Best regards. >> >> Jean-Samuel. >> :-) >> >> >> >> On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov wrote: >> >>> Jean-Samuel. >>> >>> Please inform me what actually rf chockes partnumbers are problem to >>> order. >>> Unfortunately MuRata produce few billion pcs and then stopped for a few >>> years. >>> So, possible we have to find some Chinese fab partnumbers to order. >>> >>> Best regards, >>> Andrey Sviyazov. >>> (Sent from my mobile client) >>> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" >>> ???????: >>> >>> Hi Jean-Samuel. >>>> Unfortunately I have no internet connection now. >>>> Tomorrow I'll check flash and others. >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> (Sent from my mobile client) >>>> >>>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" < >>>> alexander.chemeris at gmail.com> ???????: >>>> > >>>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT PARTNERS >>>> > SARL wrote: >>>> > > 1/ Would you know a distributor for the Murata chokes ? The fab >>>> them to have >>>> > > some issue to source these. >>>> > >>>> > Andrey is looking into this. >>>> > >>>> > > 2/ Would you suggest a distributor for the GPS chip ? >>>> > >>>> > Try contacting manufacturer directly: >>>> > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >>>> > >>>> > They have a distributor in UK, but I think it might be easier to buy >>>> > from the manufacturer directly: >>>> > http://www.castlemicrowave.com/castle-contact.asp >>>> > >>>> > This chip is popular in Russia, so it is easy to source them here, >>>> > shipping them to EU might be a pain in big batches, but I think we >>>> > could send few chips for this prototyping batch if manufacturer's lead >>>> > time is too long. Here it costs $14.50/chip for more then 16 chips: >>>> > http://www.compel.ru/infosheet/TSI/EB-570/ >>>> > >>>> > -- >>>> > Regards, >>>> > Alexander Chemeris. >>>> > CEO, Fairwaves LLC / ??? ??????? >>>> > http://fairwaves.ru >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From jsn at bjtpartners.com Wed Jul 4 12:39:53 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Wed, 4 Jul 2012 14:39:53 +0200 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Andrey, Thank you for your reply. The problem is the chip beads you suggest are quite expensive. You can see this on Farnell. As there are 60 of these beads on the board, even a few cents make a difference. Could you suggest cheaper references ? Thanks a lot for your help. Best regards. Jean-Samuel. :-) On Wed, Jul 4, 2012 at 2:23 PM, Andrey Sviyazov wrote: > Hi Jean-Samuel. > > About SRAM which I've found from ISSI I'm sure that it full compatible and > of cause we are discussed with Andrew Karpenkov and Alexander Chemeris that > 18Mbit size should be enough. > And also I think you should order exactly this 0603 and 0805 chip beads > instead of TI160808U601 and TI201209U121 as I mentioned and do not spend > time for search. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL > >> Hi Andrey, >> >> Thank you very much for your reply. >> >> I try to find where to buy the TI160808U601 and TI201209-121 chokes. I do >> not know where I should find these. Would you know where I should order >> these components ? >> >> By the way, do you confirm the ISSI SRAM is pin compatible with the >> Cypress chip ? >> >> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >> >> Is this ISSI chip fine for our application ? Is 18 MBit enough ? >> Do you confirm this ISSI chip is the best value for what we need ? Are >> you sure we cannot find a lower cost chip with similar performances and/or >> a better performances chip with similar cost ? >> Are you sure we will not need to reroute the PCB ? >> >> We really need to be sure before starting the PCB production. If both you >> and Alexander confirm everything is fine, I will ask the fab to start the >> PCB. >> >> Please let me know. >> >> Again, thanks a lot for your help. >> >> Best regards. >> >> Jean-Samuel. >> :-) >> >> >> >> On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov wrote: >> >>> Jean-Samuel. >>> >>> Please inform me what actually rf chockes partnumbers are problem to >>> order. >>> Unfortunately MuRata produce few billion pcs and then stopped for a few >>> years. >>> So, possible we have to find some Chinese fab partnumbers to order. >>> >>> Best regards, >>> Andrey Sviyazov. >>> (Sent from my mobile client) >>> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" >>> ???????: >>> >>> Hi Jean-Samuel. >>>> Unfortunately I have no internet connection now. >>>> Tomorrow I'll check flash and others. >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> (Sent from my mobile client) >>>> >>>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" < >>>> alexander.chemeris at gmail.com> ???????: >>>> > >>>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT PARTNERS >>>> > SARL wrote: >>>> > > 1/ Would you know a distributor for the Murata chokes ? The fab >>>> them to have >>>> > > some issue to source these. >>>> > >>>> > Andrey is looking into this. >>>> > >>>> > > 2/ Would you suggest a distributor for the GPS chip ? >>>> > >>>> > Try contacting manufacturer directly: >>>> > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >>>> > >>>> > They have a distributor in UK, but I think it might be easier to buy >>>> > from the manufacturer directly: >>>> > http://www.castlemicrowave.com/castle-contact.asp >>>> > >>>> > This chip is popular in Russia, so it is easy to source them here, >>>> > shipping them to EU might be a pain in big batches, but I think we >>>> > could send few chips for this prototyping batch if manufacturer's lead >>>> > time is too long. Here it costs $14.50/chip for more then 16 chips: >>>> > http://www.compel.ru/infosheet/TSI/EB-570/ >>>> > >>>> > -- >>>> > Regards, >>>> > Alexander Chemeris. >>>> > CEO, Fairwaves LLC / ??? ??????? >>>> > http://fairwaves.ru >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andreysviyaz at gmail.com Wed Jul 4 13:22:09 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Wed, 4 Jul 2012 17:22:09 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Jean-Samuel. If Farnell better for you, then please order exactly MLB-201209-0120PU and MLB-160808-0600PL . They are HI_CURRENT beads and it is really required. Please find attached here new SCH and BOM files with new part numbers and links. Best regards, Andrey Sviyazov. 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL > Hi Andrey, > > Thank you very much for your reply. > > Could you please confirm the components bellow are fine ? > http://fr.farnell.com/murata/blm18tg601tn1d/ferrite-600ohm/dp/1115050RL > > http://fr.farnell.com/tdk/mmz2012121b/perle-de-ferrite-0805-120-ohm/dp/1669728RL > > Please let me know if this is fine. > If not, which would you suggest ? > http://ru.farnell.com/ferrite-beads > > > Thanks a lot for your help. > > Best regards. > > Jean-Samuel. > :-) > > > On Wed, Jul 4, 2012 at 2:02 PM, Andrey Sviyazov wrote: > >> Hi Jean-Samuel. >> >> For the TI160808U601 and TI201209U121 you can use any high current >> ferrite chip bead with 600 Ohm and 120 Ohm impedance respectively. >> For example you could order similar partnumbers from the ELFAcatalogue in the >> 0603and >> 0805 SMD >> cases respectively, datasheet here pdf >> . >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >> >>> Hi Andrey, >>> >>> Thank you very much for your reply. >>> >>> I try to find where to buy the TI160808U601 and TI201209-121 chokes. I >>> do not know where I should find these. Would you know where I should order >>> these components ? >>> >>> By the way, do you confirm the ISSI SRAM is pin compatible with the >>> Cypress chip ? >>> >>> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >>> >>> Is this ISSI chip fine for our application ? Is 18 MBit enough ? >>> Do you confirm this ISSI chip is the best value for what we need ? Are >>> you sure we cannot find a lower cost chip with similar performances and/or >>> a better performances chip with similar cost ? >>> Are you sure we will not need to reroute the PCB ? >>> >>> We really need to be sure before starting the PCB production. If both >>> you and Alexander confirm everything is fine, I will ask the fab to start >>> the PCB. >>> >>> Please let me know. >>> >>> Again, thanks a lot for your help. >>> >>> Best regards. >>> >>> Jean-Samuel. >>> :-) >>> >>> >>> >>> On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov >> > wrote: >>> >>>> Jean-Samuel. >>>> >>>> Please inform me what actually rf chockes partnumbers are problem to >>>> order. >>>> Unfortunately MuRata produce few billion pcs and then stopped for a few >>>> years. >>>> So, possible we have to find some Chinese fab partnumbers to order. >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> (Sent from my mobile client) >>>> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" >>>> ???????: >>>> >>>> Hi Jean-Samuel. >>>>> Unfortunately I have no internet connection now. >>>>> Tomorrow I'll check flash and others. >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> (Sent from my mobile client) >>>>> >>>>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" < >>>>> alexander.chemeris at gmail.com> ???????: >>>>> > >>>>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT PARTNERS >>>>> > SARL wrote: >>>>> > > 1/ Would you know a distributor for the Murata chokes ? The fab >>>>> them to have >>>>> > > some issue to source these. >>>>> > >>>>> > Andrey is looking into this. >>>>> > >>>>> > > 2/ Would you suggest a distributor for the GPS chip ? >>>>> > >>>>> > Try contacting manufacturer directly: >>>>> > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >>>>> > >>>>> > They have a distributor in UK, but I think it might be easier to buy >>>>> > from the manufacturer directly: >>>>> > http://www.castlemicrowave.com/castle-contact.asp >>>>> > >>>>> > This chip is popular in Russia, so it is easy to source them here, >>>>> > shipping them to EU might be a pain in big batches, but I think we >>>>> > could send few chips for this prototyping batch if manufacturer's >>>>> lead >>>>> > time is too long. Here it costs $14.50/chip for more then 16 chips: >>>>> > http://www.compel.ru/infosheet/TSI/EB-570/ >>>>> > >>>>> > -- >>>>> > Regards, >>>>> > Alexander Chemeris. >>>>> > CEO, Fairwaves LLC / ??? ??????? >>>>> > http://fairwaves.ru >>>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: UmTRXv2_BOM_20dBm_TCXO_040712.xls Type: application/vnd.ms-excel Size: 61440 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: UmTRXv2_sch_20dBm_TCXO_040712.pdf Type: application/pdf Size: 1607567 bytes Desc: not available URL: From andreysviyaz at gmail.com Wed Jul 4 13:38:48 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Wed, 4 Jul 2012 17:38:48 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi all. Here package of the project and schdoc. PcbDoc still doesn't changed. Best regards, Andrey Sviyazov. 2012/7/4 Andrey Sviyazov > Hi Jean-Samuel. > > If Farnell better for you, then please order exactly MLB-201209-0120PU > and MLB-160808-0600PL > . > They are HI_CURRENT beads and it is really required. > > Please find attached here new SCH and BOM files with new part numbers and > links. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL > >> Hi Andrey, >> >> Thank you very much for your reply. >> >> Could you please confirm the components bellow are fine ? >> http://fr.farnell.com/murata/blm18tg601tn1d/ferrite-600ohm/dp/1115050RL >> >> http://fr.farnell.com/tdk/mmz2012121b/perle-de-ferrite-0805-120-ohm/dp/1669728RL >> >> Please let me know if this is fine. >> If not, which would you suggest ? >> http://ru.farnell.com/ferrite-beads >> >> >> Thanks a lot for your help. >> >> Best regards. >> >> Jean-Samuel. >> :-) >> >> >> On Wed, Jul 4, 2012 at 2:02 PM, Andrey Sviyazov wrote: >> >>> Hi Jean-Samuel. >>> >>> For the TI160808U601 and TI201209U121 you can use any high current >>> ferrite chip bead with 600 Ohm and 120 Ohm impedance respectively. >>> For example you could order similar partnumbers from the ELFAcatalogue in the >>> 0603and >>> 0805 SMD >>> cases respectively, datasheet here pdf >>> . >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>> >>>> Hi Andrey, >>>> >>>> Thank you very much for your reply. >>>> >>>> I try to find where to buy the TI160808U601 and TI201209-121 chokes. I >>>> do not know where I should find these. Would you know where I should order >>>> these components ? >>>> >>>> By the way, do you confirm the ISSI SRAM is pin compatible with the >>>> Cypress chip ? >>>> >>>> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >>>> >>>> Is this ISSI chip fine for our application ? Is 18 MBit enough ? >>>> Do you confirm this ISSI chip is the best value for what we need ? Are >>>> you sure we cannot find a lower cost chip with similar performances and/or >>>> a better performances chip with similar cost ? >>>> Are you sure we will not need to reroute the PCB ? >>>> >>>> We really need to be sure before starting the PCB production. If both >>>> you and Alexander confirm everything is fine, I will ask the fab to start >>>> the PCB. >>>> >>>> Please let me know. >>>> >>>> Again, thanks a lot for your help. >>>> >>>> Best regards. >>>> >>>> Jean-Samuel. >>>> :-) >>>> >>>> >>>> >>>> On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov < >>>> andreysviyaz at gmail.com> wrote: >>>> >>>>> Jean-Samuel. >>>>> >>>>> Please inform me what actually rf chockes partnumbers are problem to >>>>> order. >>>>> Unfortunately MuRata produce few billion pcs and then stopped for a >>>>> few years. >>>>> So, possible we have to find some Chinese fab partnumbers to order. >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> (Sent from my mobile client) >>>>> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" >>>>> ???????: >>>>> >>>>> Hi Jean-Samuel. >>>>>> Unfortunately I have no internet connection now. >>>>>> Tomorrow I'll check flash and others. >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> (Sent from my mobile client) >>>>>> >>>>>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" < >>>>>> alexander.chemeris at gmail.com> ???????: >>>>>> > >>>>>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT PARTNERS >>>>>> > SARL wrote: >>>>>> > > 1/ Would you know a distributor for the Murata chokes ? The fab >>>>>> them to have >>>>>> > > some issue to source these. >>>>>> > >>>>>> > Andrey is looking into this. >>>>>> > >>>>>> > > 2/ Would you suggest a distributor for the GPS chip ? >>>>>> > >>>>>> > Try contacting manufacturer directly: >>>>>> > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >>>>>> > >>>>>> > They have a distributor in UK, but I think it might be easier to buy >>>>>> > from the manufacturer directly: >>>>>> > http://www.castlemicrowave.com/castle-contact.asp >>>>>> > >>>>>> > This chip is popular in Russia, so it is easy to source them here, >>>>>> > shipping them to EU might be a pain in big batches, but I think we >>>>>> > could send few chips for this prototyping batch if manufacturer's >>>>>> lead >>>>>> > time is too long. Here it costs $14.50/chip for more then 16 chips: >>>>>> > http://www.compel.ru/infosheet/TSI/EB-570/ >>>>>> > >>>>>> > -- >>>>>> > Regards, >>>>>> > Alexander Chemeris. >>>>>> > CEO, Fairwaves LLC / ??? ??????? >>>>>> > http://fairwaves.ru >>>>>> >>>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: UmTRXv2_SCHDOC (04.07.2012 17-31-16).zip Type: application/zip Size: 767371 bytes Desc: not available URL: From jsn at bjtpartners.com Wed Jul 4 13:46:47 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Wed, 4 Jul 2012 15:46:47 +0200 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Andrey, Thank you very much for your reply. Now, I better understand. You are all right. I do not have anything as high current as MLB-201209-0120PU at a lower price. However, I have a 0603 600 ohm 1A bead, as MLB-160808-0600PL, at a much lower price. http://ru.farnell.com/tdk/mpz1608s601a/ferrite-bead-0603-600-ohm/dp/1669747RL What do you think about this component (TDK MPZ1608S601A)? Best regards. Jean-Samuel. :-) On Wed, Jul 4, 2012 at 3:22 PM, Andrey Sviyazov wrote: > Hi Jean-Samuel. > > If Farnell better for you, then please order exactly MLB-201209-0120PU > and MLB-160808-0600PL > . > They are HI_CURRENT beads and it is really required. > > Please find attached here new SCH and BOM files with new part numbers and > links. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL > >> Hi Andrey, >> >> Thank you very much for your reply. >> >> Could you please confirm the components bellow are fine ? >> http://fr.farnell.com/murata/blm18tg601tn1d/ferrite-600ohm/dp/1115050RL >> >> http://fr.farnell.com/tdk/mmz2012121b/perle-de-ferrite-0805-120-ohm/dp/1669728RL >> >> Please let me know if this is fine. >> If not, which would you suggest ? >> http://ru.farnell.com/ferrite-beads >> >> >> Thanks a lot for your help. >> >> Best regards. >> >> Jean-Samuel. >> :-) >> >> >> On Wed, Jul 4, 2012 at 2:02 PM, Andrey Sviyazov wrote: >> >>> Hi Jean-Samuel. >>> >>> For the TI160808U601 and TI201209U121 you can use any high current >>> ferrite chip bead with 600 Ohm and 120 Ohm impedance respectively. >>> For example you could order similar partnumbers from the ELFAcatalogue in the >>> 0603and >>> 0805 SMD >>> cases respectively, datasheet here pdf >>> . >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>> >>>> Hi Andrey, >>>> >>>> Thank you very much for your reply. >>>> >>>> I try to find where to buy the TI160808U601 and TI201209-121 chokes. I >>>> do not know where I should find these. Would you know where I should order >>>> these components ? >>>> >>>> By the way, do you confirm the ISSI SRAM is pin compatible with the >>>> Cypress chip ? >>>> >>>> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >>>> >>>> Is this ISSI chip fine for our application ? Is 18 MBit enough ? >>>> Do you confirm this ISSI chip is the best value for what we need ? Are >>>> you sure we cannot find a lower cost chip with similar performances and/or >>>> a better performances chip with similar cost ? >>>> Are you sure we will not need to reroute the PCB ? >>>> >>>> We really need to be sure before starting the PCB production. If both >>>> you and Alexander confirm everything is fine, I will ask the fab to start >>>> the PCB. >>>> >>>> Please let me know. >>>> >>>> Again, thanks a lot for your help. >>>> >>>> Best regards. >>>> >>>> Jean-Samuel. >>>> :-) >>>> >>>> >>>> >>>> On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov < >>>> andreysviyaz at gmail.com> wrote: >>>> >>>>> Jean-Samuel. >>>>> >>>>> Please inform me what actually rf chockes partnumbers are problem to >>>>> order. >>>>> Unfortunately MuRata produce few billion pcs and then stopped for a >>>>> few years. >>>>> So, possible we have to find some Chinese fab partnumbers to order. >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> (Sent from my mobile client) >>>>> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" >>>>> ???????: >>>>> >>>>> Hi Jean-Samuel. >>>>>> Unfortunately I have no internet connection now. >>>>>> Tomorrow I'll check flash and others. >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> (Sent from my mobile client) >>>>>> >>>>>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" < >>>>>> alexander.chemeris at gmail.com> ???????: >>>>>> > >>>>>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT PARTNERS >>>>>> > SARL wrote: >>>>>> > > 1/ Would you know a distributor for the Murata chokes ? The fab >>>>>> them to have >>>>>> > > some issue to source these. >>>>>> > >>>>>> > Andrey is looking into this. >>>>>> > >>>>>> > > 2/ Would you suggest a distributor for the GPS chip ? >>>>>> > >>>>>> > Try contacting manufacturer directly: >>>>>> > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >>>>>> > >>>>>> > They have a distributor in UK, but I think it might be easier to buy >>>>>> > from the manufacturer directly: >>>>>> > http://www.castlemicrowave.com/castle-contact.asp >>>>>> > >>>>>> > This chip is popular in Russia, so it is easy to source them here, >>>>>> > shipping them to EU might be a pain in big batches, but I think we >>>>>> > could send few chips for this prototyping batch if manufacturer's >>>>>> lead >>>>>> > time is too long. Here it costs $14.50/chip for more then 16 chips: >>>>>> > http://www.compel.ru/infosheet/TSI/EB-570/ >>>>>> > >>>>>> > -- >>>>>> > Regards, >>>>>> > Alexander Chemeris. >>>>>> > CEO, Fairwaves LLC / ??? ??????? >>>>>> > http://fairwaves.ru >>>>>> >>>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andreysviyaz at gmail.com Wed Jul 4 14:30:36 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Wed, 4 Jul 2012 18:30:36 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Jean-Samuel. Yes, you are all right and you can order TDK - MPZ1608S601A instead of MLB-160808-0600PL. And also possible to use 3 times cheaper FBMH2012HM121-T, 0805, 2.5A instead of MLB-201209-0120PU. Best regards, Andrey Sviyazov. 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL > Hi Andrey, > > Thank you very much for your reply. > Now, I better understand. > > You are all right. I do not have anything as high current as > MLB-201209-0120PU at a lower price. > > However, I have a 0603 600 ohm 1A bead, as MLB-160808-0600PL, at a much > lower price. > > http://ru.farnell.com/tdk/mpz1608s601a/ferrite-bead-0603-600-ohm/dp/1669747RL > What do you think about this component (TDK MPZ1608S601A)? > > Best regards. > > Jean-Samuel. > :-) > > > > On Wed, Jul 4, 2012 at 3:22 PM, Andrey Sviyazov wrote: > >> Hi Jean-Samuel. >> >> If Farnell better for you, then please order exactly MLB-201209-0120PU >> and MLB-160808-0600PL >> . >> They are HI_CURRENT beads and it is really required. >> >> Please find attached here new SCH and BOM files with new part numbers and >> links. >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >> >>> Hi Andrey, >>> >>> Thank you very much for your reply. >>> >>> Could you please confirm the components bellow are fine ? >>> http://fr.farnell.com/murata/blm18tg601tn1d/ferrite-600ohm/dp/1115050RL >>> >>> http://fr.farnell.com/tdk/mmz2012121b/perle-de-ferrite-0805-120-ohm/dp/1669728RL >>> >>> Please let me know if this is fine. >>> If not, which would you suggest ? >>> http://ru.farnell.com/ferrite-beads >>> >>> >>> Thanks a lot for your help. >>> >>> Best regards. >>> >>> Jean-Samuel. >>> :-) >>> >>> >>> On Wed, Jul 4, 2012 at 2:02 PM, Andrey Sviyazov wrote: >>> >>>> Hi Jean-Samuel. >>>> >>>> For the TI160808U601 and TI201209U121 you can use any high current >>>> ferrite chip bead with 600 Ohm and 120 Ohm impedance respectively. >>>> For example you could order similar partnumbers from the ELFAcatalogue in the >>>> 0603and >>>> 0805 SMD >>>> cases respectively, datasheet here pdf >>>> . >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> >>>> >>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>>> >>>>> Hi Andrey, >>>>> >>>>> Thank you very much for your reply. >>>>> >>>>> I try to find where to buy the TI160808U601 and TI201209-121 chokes. I >>>>> do not know where I should find these. Would you know where I should order >>>>> these components ? >>>>> >>>>> By the way, do you confirm the ISSI SRAM is pin compatible with the >>>>> Cypress chip ? >>>>> >>>>> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >>>>> >>>>> Is this ISSI chip fine for our application ? Is 18 MBit enough ? >>>>> Do you confirm this ISSI chip is the best value for what we need ? Are >>>>> you sure we cannot find a lower cost chip with similar performances and/or >>>>> a better performances chip with similar cost ? >>>>> Are you sure we will not need to reroute the PCB ? >>>>> >>>>> We really need to be sure before starting the PCB production. If both >>>>> you and Alexander confirm everything is fine, I will ask the fab to start >>>>> the PCB. >>>>> >>>>> Please let me know. >>>>> >>>>> Again, thanks a lot for your help. >>>>> >>>>> Best regards. >>>>> >>>>> Jean-Samuel. >>>>> :-) >>>>> >>>>> >>>>> >>>>> On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov < >>>>> andreysviyaz at gmail.com> wrote: >>>>> >>>>>> Jean-Samuel. >>>>>> >>>>>> Please inform me what actually rf chockes partnumbers are problem to >>>>>> order. >>>>>> Unfortunately MuRata produce few billion pcs and then stopped for a >>>>>> few years. >>>>>> So, possible we have to find some Chinese fab partnumbers to order. >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> (Sent from my mobile client) >>>>>> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" < >>>>>> andreysviyaz at gmail.com> ???????: >>>>>> >>>>>> Hi Jean-Samuel. >>>>>>> Unfortunately I have no internet connection now. >>>>>>> Tomorrow I'll check flash and others. >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> (Sent from my mobile client) >>>>>>> >>>>>>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" < >>>>>>> alexander.chemeris at gmail.com> ???????: >>>>>>> > >>>>>>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT >>>>>>> PARTNERS >>>>>>> > SARL wrote: >>>>>>> > > 1/ Would you know a distributor for the Murata chokes ? The fab >>>>>>> them to have >>>>>>> > > some issue to source these. >>>>>>> > >>>>>>> > Andrey is looking into this. >>>>>>> > >>>>>>> > > 2/ Would you suggest a distributor for the GPS chip ? >>>>>>> > >>>>>>> > Try contacting manufacturer directly: >>>>>>> > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >>>>>>> > >>>>>>> > They have a distributor in UK, but I think it might be easier to >>>>>>> buy >>>>>>> > from the manufacturer directly: >>>>>>> > http://www.castlemicrowave.com/castle-contact.asp >>>>>>> > >>>>>>> > This chip is popular in Russia, so it is easy to source them here, >>>>>>> > shipping them to EU might be a pain in big batches, but I think we >>>>>>> > could send few chips for this prototyping batch if manufacturer's >>>>>>> lead >>>>>>> > time is too long. Here it costs $14.50/chip for more then 16 chips: >>>>>>> > http://www.compel.ru/infosheet/TSI/EB-570/ >>>>>>> > >>>>>>> > -- >>>>>>> > Regards, >>>>>>> > Alexander Chemeris. >>>>>>> > CEO, Fairwaves LLC / ??? ??????? >>>>>>> > http://fairwaves.ru >>>>>>> >>>>>> >>>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From jsn at bjtpartners.com Wed Jul 4 16:00:56 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Wed, 4 Jul 2012 18:00:56 +0200 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Andrey, Thank you very much for your help. I will forward this to the fab. Yes, you are all right, the FBMH2012HM121-T price is much better than the MLB-201209-0120PU. However, availability on Farnell France is not as good as the MLB-201209-0120PU. Price difference is quite big but we only use 5 beads per boards. Difference makes only about 1 euro per board. I will let the fab decide between these 2 references. Best regards. Jean-Samuel. :-) On Wed, Jul 4, 2012 at 4:30 PM, Andrey Sviyazov wrote: > Hi Jean-Samuel. > > Yes, you are all right and you can order TDK - MPZ1608S601A instead of > MLB-160808-0600PL. > And also possible to use 3 times cheaper FBMH2012HM121-T, 0805, 2.5A instead > of MLB-201209-0120PU. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL > >> Hi Andrey, >> >> Thank you very much for your reply. >> Now, I better understand. >> >> You are all right. I do not have anything as high current as >> MLB-201209-0120PU at a lower price. >> >> However, I have a 0603 600 ohm 1A bead, as MLB-160808-0600PL, at a much >> lower price. >> >> http://ru.farnell.com/tdk/mpz1608s601a/ferrite-bead-0603-600-ohm/dp/1669747RL >> What do you think about this component (TDK MPZ1608S601A)? >> >> Best regards. >> >> Jean-Samuel. >> :-) >> >> >> >> On Wed, Jul 4, 2012 at 3:22 PM, Andrey Sviyazov wrote: >> >>> Hi Jean-Samuel. >>> >>> If Farnell better for you, then please order exactly MLB-201209-0120PU >>> and MLB-160808-0600PL >>> . >>> They are HI_CURRENT beads and it is really required. >>> >>> Please find attached here new SCH and BOM files with new part numbers >>> and links. >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>> >>>> Hi Andrey, >>>> >>>> Thank you very much for your reply. >>>> >>>> Could you please confirm the components bellow are fine ? >>>> http://fr.farnell.com/murata/blm18tg601tn1d/ferrite-600ohm/dp/1115050RL >>>> >>>> http://fr.farnell.com/tdk/mmz2012121b/perle-de-ferrite-0805-120-ohm/dp/1669728RL >>>> >>>> Please let me know if this is fine. >>>> If not, which would you suggest ? >>>> http://ru.farnell.com/ferrite-beads >>>> >>>> >>>> Thanks a lot for your help. >>>> >>>> Best regards. >>>> >>>> Jean-Samuel. >>>> :-) >>>> >>>> >>>> On Wed, Jul 4, 2012 at 2:02 PM, Andrey Sviyazov >>> > wrote: >>>> >>>>> Hi Jean-Samuel. >>>>> >>>>> For the TI160808U601 and TI201209U121 you can use any high current >>>>> ferrite chip bead with 600 Ohm and 120 Ohm impedance respectively. >>>>> For example you could order similar partnumbers from the ELFAcatalogue in the >>>>> 0603and >>>>> 0805 SMD >>>>> cases respectively, datasheet here pdf >>>>> . >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> >>>>> >>>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>>> > >>>>> >>>>>> Hi Andrey, >>>>>> >>>>>> Thank you very much for your reply. >>>>>> >>>>>> I try to find where to buy the TI160808U601 and TI201209-121 chokes. >>>>>> I do not know where I should find these. Would you know where I should >>>>>> order these components ? >>>>>> >>>>>> By the way, do you confirm the ISSI SRAM is pin compatible with the >>>>>> Cypress chip ? >>>>>> >>>>>> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >>>>>> >>>>>> Is this ISSI chip fine for our application ? Is 18 MBit enough ? >>>>>> Do you confirm this ISSI chip is the best value for what we need ? >>>>>> Are you sure we cannot find a lower cost chip with similar performances >>>>>> and/or a better performances chip with similar cost ? >>>>>> Are you sure we will not need to reroute the PCB ? >>>>>> >>>>>> We really need to be sure before starting the PCB production. If both >>>>>> you and Alexander confirm everything is fine, I will ask the fab to start >>>>>> the PCB. >>>>>> >>>>>> Please let me know. >>>>>> >>>>>> Again, thanks a lot for your help. >>>>>> >>>>>> Best regards. >>>>>> >>>>>> Jean-Samuel. >>>>>> :-) >>>>>> >>>>>> >>>>>> >>>>>> On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov < >>>>>> andreysviyaz at gmail.com> wrote: >>>>>> >>>>>>> Jean-Samuel. >>>>>>> >>>>>>> Please inform me what actually rf chockes partnumbers are problem to >>>>>>> order. >>>>>>> Unfortunately MuRata produce few billion pcs and then stopped for a >>>>>>> few years. >>>>>>> So, possible we have to find some Chinese fab partnumbers to order. >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> (Sent from my mobile client) >>>>>>> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" < >>>>>>> andreysviyaz at gmail.com> ???????: >>>>>>> >>>>>>> Hi Jean-Samuel. >>>>>>>> Unfortunately I have no internet connection now. >>>>>>>> Tomorrow I'll check flash and others. >>>>>>>> >>>>>>>> Best regards, >>>>>>>> Andrey Sviyazov. >>>>>>>> (Sent from my mobile client) >>>>>>>> >>>>>>>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" < >>>>>>>> alexander.chemeris at gmail.com> ???????: >>>>>>>> > >>>>>>>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT >>>>>>>> PARTNERS >>>>>>>> > SARL wrote: >>>>>>>> > > 1/ Would you know a distributor for the Murata chokes ? The fab >>>>>>>> them to have >>>>>>>> > > some issue to source these. >>>>>>>> > >>>>>>>> > Andrey is looking into this. >>>>>>>> > >>>>>>>> > > 2/ Would you suggest a distributor for the GPS chip ? >>>>>>>> > >>>>>>>> > Try contacting manufacturer directly: >>>>>>>> > >>>>>>>> http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >>>>>>>> > >>>>>>>> > They have a distributor in UK, but I think it might be easier to >>>>>>>> buy >>>>>>>> > from the manufacturer directly: >>>>>>>> > http://www.castlemicrowave.com/castle-contact.asp >>>>>>>> > >>>>>>>> > This chip is popular in Russia, so it is easy to source them here, >>>>>>>> > shipping them to EU might be a pain in big batches, but I think we >>>>>>>> > could send few chips for this prototyping batch if manufacturer's >>>>>>>> lead >>>>>>>> > time is too long. Here it costs $14.50/chip for more then 16 >>>>>>>> chips: >>>>>>>> > http://www.compel.ru/infosheet/TSI/EB-570/ >>>>>>>> > >>>>>>>> > -- >>>>>>>> > Regards, >>>>>>>> > Alexander Chemeris. >>>>>>>> > CEO, Fairwaves LLC / ??? ??????? >>>>>>>> > http://fairwaves.ru >>>>>>>> >>>>>>> >>>>>> >>>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Sun Jul 15 07:08:41 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sun, 15 Jul 2012 11:08:41 +0400 Subject: UmTRX prototypes cost Message-ID: Hi Jean-Samuel, Could you share the prices you get for UmTRX from your fab for this batch of prototypes and for the next batches? We have to understand the cost price to see what could we offer to customers. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sun Jul 15 10:43:47 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sun, 15 Jul 2012 14:43:47 +0400 Subject: UmTRX goes public Message-ID: Hi all, As UmTRX release gets closer, i want to gradually move all related documentation, discussions, news, etc to public. The plan is to move everything under the Osmocom umbrella, because it's a good neighborhood for UmTRX. Omsmocom.org server is somewhat overloaded now, so for the time being all git repos will stay at github and wiki and files will stay at Google Code. They will be moved to osmocom.org when they upgrade their server. Mailing list is not a big load, so the UmTRX public mailing list has been created as umtrx at lists.osmocom.org. Some of you already received subscription e-mails, everyone else is encouraged to subscribe as well. You could do that with the web interface here: http://lists.osmocom.org/cgi-bin/mailman/listinfo/umtrx Please use the public mailing list for all technical discussions from now on. "Project-mayotte" and "gsm-internal" are to be used for business and manufacturing related, private or other highly 533kr337 discussions. I'm going to publish schematics today together with some brief description of features. Public Lime documentation will be published as well. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From jsn at bjtpartners.com Sun Jul 15 15:08:54 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Sun, 15 Jul 2012 17:08:54 +0200 Subject: UmTRX prototypes cost In-Reply-To: References: Message-ID: Hi Alexander, Total cost for production is approximately 10000 Euros for 20 units, including about 1000 Euros Non Recuring Costs. Approximate unit cost for sample batches (6 and 14 units each) is a bit bellow 500 Euros. If we do not need to change the PCB, unit cost will be around 440 Euros for 20 units batches. If we make 50 or 100 units batches, cost could be a bit lower but not that much. We could expect to save on the TCD-4029-26.0M. Today, we pay it about 15 Euros because of our low volume. For 50 or 100 units, we could buy this part directly from Pletronics and save about 5 or 6 Euros per unit. We could also save on the PCB. For 20 units, cost is 32 Euros but we could expect to save 5 to 10 Euros on it. On all other components, we could expect something like about 10 to 15 Euros extra savings. For 50 units batches instead of 20 units, we could also save about 4 Euros per board on the cost the fab charges for loading the assembly machines. For 50 units batches, we could achieve a unit production cost at 500 USD. Anyway, please find enclosed a few details about our production costs. You can see fab costs are quite reasonable expecially for our low and medium volumes. This cost structure is really convenient to make our samples and gradually ramp up our production volumes. In case we reach much higher volumes in the future, I am quite confident we could bargain a bit more the fab costs and certainly also save a bit more on the components sourcing costs. Except for the low cost femtocells market, I really believe this cost structure will allow you to compete on the market in good conditions. You would need to add the cost of the enclosure, the PSU, the diversity and selectivity RF daughter board we need to pass the spec and the CPU mother board we need to run the Transceiver and OpenBTS. You should expect a total cost around 800 USD excluding the frontend (PA+LNA+duplexers). For your information, the dual TRX outdoor enclosure frontend with 10 Watts PA I can get from my Chinese supplier costs 810 USD + shipping. Please do not hesitate to contact me if you need any extra figures or information. Best regards. Jean-Samuel. :-) On Sun, Jul 15, 2012 at 9:08 AM, Alexander Chemeris < alexander.chemeris at gmail.com> wrote: > Hi Jean-Samuel, > > Could you share the prices you get for UmTRX from your fab for this > batch of prototypes and for the next batches? We have to understand > the cost price to see what could we offer to customers. > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx-production-costs.ods Type: application/vnd.oasis.opendocument.spreadsheet Size: 13738 bytes Desc: not available URL: From alexander.chemeris at gmail.com Sun Jul 15 15:50:02 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sun, 15 Jul 2012 19:50:02 +0400 Subject: UmTRX prototypes cost In-Reply-To: References: Message-ID: Hi Jean-Samuel, This is very good news! It means we've met the target cost price and we haven't compromised functionality. Could you ask the fab how much would it cost to put the board into an enclosure like this, including the front panel and the rear panel drilling and engraving? http://www.fischerelektronik.de/web_fischer/en_GB/cases/M1.07/Miniature%20aluminium%20cases/PR/AKG105_030_/$productCard/dimensionParameters/index.xhtml The idea is to sell it to general public in small quantities for in-lab use. On Sun, Jul 15, 2012 at 7:08 PM, Jean-Samuel Najnudel - BJT PARTNERS SARL wrote: > Hi Alexander, > > Total cost for production is approximately 10000 Euros for 20 units, > including about 1000 Euros Non Recuring Costs. Approximate unit cost for > sample batches (6 and 14 units each) is a bit bellow 500 Euros. > > If we do not need to change the PCB, unit cost will be around 440 Euros for > 20 units batches. > > If we make 50 or 100 units batches, cost could be a bit lower but not that > much. > > We could expect to save on the TCD-4029-26.0M. Today, we pay it about 15 > Euros because of our low volume. For 50 or 100 units, we could buy this part > directly from Pletronics and save about 5 or 6 Euros per unit. > > We could also save on the PCB. For 20 units, cost is 32 Euros but we could > expect to save 5 to 10 Euros on it. > > On all other components, we could expect something like about 10 to 15 Euros > extra savings. > > For 50 units batches instead of 20 units, we could also save about 4 Euros > per board on the cost the fab charges for loading the assembly machines. > > For 50 units batches, we could achieve a unit production cost at 500 USD. > > Anyway, please find enclosed a few details about our production costs. You > can see fab costs are quite reasonable expecially for our low and medium > volumes. This cost structure is really convenient to make our samples and > gradually ramp up our production volumes. In case we reach much higher > volumes in the future, I am quite confident we could bargain a bit more the > fab costs and certainly also save a bit more on the components sourcing > costs. Except for the low cost femtocells market, I really believe this cost > structure will allow you to compete on the market in good conditions. > > You would need to add the cost of the enclosure, the PSU, the diversity and > selectivity RF daughter board we need to pass the spec and the CPU mother > board we need to run the Transceiver and OpenBTS. You should expect a total > cost around 800 USD excluding the frontend (PA+LNA+duplexers). > > For your information, the dual TRX outdoor enclosure frontend with 10 Watts > PA I can get from my Chinese supplier costs 810 USD + shipping. > > Please do not hesitate to contact me if you need any extra figures or > information. > > Best regards. > > Jean-Samuel. > :-) > > > > On Sun, Jul 15, 2012 at 9:08 AM, Alexander Chemeris > wrote: >> >> Hi Jean-Samuel, >> >> Could you share the prices you get for UmTRX from your fab for this >> batch of prototypes and for the next batches? We have to understand >> the cost price to see what could we offer to customers. >> >> -- >> Regards, >> Alexander Chemeris. >> CEO, Fairwaves LLC / ??? ??????? >> http://fairwaves.ru > > -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From jsn at bjtpartners.com Sun Jul 15 16:46:50 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Sun, 15 Jul 2012 18:46:50 +0200 Subject: UmTRX prototypes cost In-Reply-To: References: Message-ID: Hi Alexander, Yes, this is a very good news. Except for selectivity, the UmTRX performances and features are great and you still have a reasonable cost structure. Regarding the enclosure, I think the fab can do this. However, they would need to know the exact drawing of all the connectors. They really need precise details before they accept to send me a quote. Moreover, most of the volume order will need outdoor enclosure including the UmTRX, the diversity and selectivity daughter board and the CPU board. UmTRX only in an enclosure will be only interesting for some lab applications (excluding people who are ok with the board without any enclosure). This would make the volume quite low and I am afraid low volume would mean quite high price. For the board itself, the fab makes some efforts on the price because they expect reasonably larger volumes but for this enclosure for lab applications only, they will probably be quite expensive. If you are still interested in this enclosure assembly, please send me the exact drawing and I will ask them for a quote. By the way, I will be on holidays on next week. I may take some time to reply to your e-mails. Sorry about this. Best regards. Jean-Samuel. :-) On Sun, Jul 15, 2012 at 5:50 PM, Alexander Chemeris < alexander.chemeris at gmail.com> wrote: > Hi Jean-Samuel, > > This is very good news! It means we've met the target cost price and > we haven't compromised functionality. > > Could you ask the fab how much would it cost to put the board into an > enclosure like this, including the front panel and the rear panel > drilling and engraving? > > http://www.fischerelektronik.de/web_fischer/en_GB/cases/M1.07/Miniature%20aluminium%20cases/PR/AKG105_030_/$productCard/dimensionParameters/index.xhtml > > The idea is to sell it to general public in small quantities for in-lab > use. > > On Sun, Jul 15, 2012 at 7:08 PM, Jean-Samuel Najnudel - BJT PARTNERS > SARL wrote: > > Hi Alexander, > > > > Total cost for production is approximately 10000 Euros for 20 units, > > including about 1000 Euros Non Recuring Costs. Approximate unit cost for > > sample batches (6 and 14 units each) is a bit bellow 500 Euros. > > > > If we do not need to change the PCB, unit cost will be around 440 Euros > for > > 20 units batches. > > > > If we make 50 or 100 units batches, cost could be a bit lower but not > that > > much. > > > > We could expect to save on the TCD-4029-26.0M. Today, we pay it about 15 > > Euros because of our low volume. For 50 or 100 units, we could buy this > part > > directly from Pletronics and save about 5 or 6 Euros per unit. > > > > We could also save on the PCB. For 20 units, cost is 32 Euros but we > could > > expect to save 5 to 10 Euros on it. > > > > On all other components, we could expect something like about 10 to 15 > Euros > > extra savings. > > > > For 50 units batches instead of 20 units, we could also save about 4 > Euros > > per board on the cost the fab charges for loading the assembly machines. > > > > For 50 units batches, we could achieve a unit production cost at 500 USD. > > > > Anyway, please find enclosed a few details about our production costs. > You > > can see fab costs are quite reasonable expecially for our low and medium > > volumes. This cost structure is really convenient to make our samples and > > gradually ramp up our production volumes. In case we reach much higher > > volumes in the future, I am quite confident we could bargain a bit more > the > > fab costs and certainly also save a bit more on the components sourcing > > costs. Except for the low cost femtocells market, I really believe this > cost > > structure will allow you to compete on the market in good conditions. > > > > You would need to add the cost of the enclosure, the PSU, the diversity > and > > selectivity RF daughter board we need to pass the spec and the CPU mother > > board we need to run the Transceiver and OpenBTS. You should expect a > total > > cost around 800 USD excluding the frontend (PA+LNA+duplexers). > > > > For your information, the dual TRX outdoor enclosure frontend with 10 > Watts > > PA I can get from my Chinese supplier costs 810 USD + shipping. > > > > Please do not hesitate to contact me if you need any extra figures or > > information. > > > > Best regards. > > > > Jean-Samuel. > > :-) > > > > > > > > On Sun, Jul 15, 2012 at 9:08 AM, Alexander Chemeris > > wrote: > >> > >> Hi Jean-Samuel, > >> > >> Could you share the prices you get for UmTRX from your fab for this > >> batch of prototypes and for the next batches? We have to understand > >> the cost price to see what could we offer to customers. > >> > >> -- > >> Regards, > >> Alexander Chemeris. > >> CEO, Fairwaves LLC / ??? ??????? > >> http://fairwaves.ru > > > > > > > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Sun Jul 15 16:57:24 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sun, 15 Jul 2012 20:57:24 +0400 Subject: UmTRX prototypes cost In-Reply-To: References: Message-ID: Jean-Samuel, Ok, we'll prepare drawings for the enclosure. But my assumption was that the biggest part of the cost would be handling, as it's a manual operation and prices in Europe for this are insane. I hope you have a good vacation! We'll try to mail you as little as possible :) Before you leave - could you update us whether the original estimation for this batch of UmTRX production is correct, i.e. we'll get prototypes at the first week of Aug? On Sun, Jul 15, 2012 at 8:46 PM, Jean-Samuel Najnudel - BJT PARTNERS SARL wrote: > Hi Alexander, > > Yes, this is a very good news. Except for selectivity, the UmTRX > performances and features are great and you still have a reasonable cost > structure. > > Regarding the enclosure, I think the fab can do this. However, they would > need to know the exact drawing of all the connectors. They really need > precise details before they accept to send me a quote. > > Moreover, most of the volume order will need outdoor enclosure including the > UmTRX, the diversity and selectivity daughter board and the CPU board. > UmTRX only in an enclosure will be only interesting for some lab > applications (excluding people who are ok with the board without any > enclosure). This would make the volume quite low and I am afraid low volume > would mean quite high price. For the board itself, the fab makes some > efforts on the price because they expect reasonably larger volumes but for > this enclosure for lab applications only, they will probably be quite > expensive. > > If you are still interested in this enclosure assembly, please send me the > exact drawing and I will ask them for a quote. > > By the way, I will be on holidays on next week. I may take some time to > reply to your e-mails. Sorry about this. > > Best regards. > > Jean-Samuel. > :-) > > > > On Sun, Jul 15, 2012 at 5:50 PM, Alexander Chemeris > wrote: >> >> Hi Jean-Samuel, >> >> This is very good news! It means we've met the target cost price and >> we haven't compromised functionality. >> >> Could you ask the fab how much would it cost to put the board into an >> enclosure like this, including the front panel and the rear panel >> drilling and engraving? >> >> http://www.fischerelektronik.de/web_fischer/en_GB/cases/M1.07/Miniature%20aluminium%20cases/PR/AKG105_030_/$productCard/dimensionParameters/index.xhtml >> >> The idea is to sell it to general public in small quantities for in-lab >> use. >> >> On Sun, Jul 15, 2012 at 7:08 PM, Jean-Samuel Najnudel - BJT PARTNERS >> SARL wrote: >> > Hi Alexander, >> > >> > Total cost for production is approximately 10000 Euros for 20 units, >> > including about 1000 Euros Non Recuring Costs. Approximate unit cost for >> > sample batches (6 and 14 units each) is a bit bellow 500 Euros. >> > >> > If we do not need to change the PCB, unit cost will be around 440 Euros >> > for >> > 20 units batches. >> > >> > If we make 50 or 100 units batches, cost could be a bit lower but not >> > that >> > much. >> > >> > We could expect to save on the TCD-4029-26.0M. Today, we pay it about 15 >> > Euros because of our low volume. For 50 or 100 units, we could buy this >> > part >> > directly from Pletronics and save about 5 or 6 Euros per unit. >> > >> > We could also save on the PCB. For 20 units, cost is 32 Euros but we >> > could >> > expect to save 5 to 10 Euros on it. >> > >> > On all other components, we could expect something like about 10 to 15 >> > Euros >> > extra savings. >> > >> > For 50 units batches instead of 20 units, we could also save about 4 >> > Euros >> > per board on the cost the fab charges for loading the assembly machines. >> > >> > For 50 units batches, we could achieve a unit production cost at 500 >> > USD. >> > >> > Anyway, please find enclosed a few details about our production costs. >> > You >> > can see fab costs are quite reasonable expecially for our low and medium >> > volumes. This cost structure is really convenient to make our samples >> > and >> > gradually ramp up our production volumes. In case we reach much higher >> > volumes in the future, I am quite confident we could bargain a bit more >> > the >> > fab costs and certainly also save a bit more on the components sourcing >> > costs. Except for the low cost femtocells market, I really believe this >> > cost >> > structure will allow you to compete on the market in good conditions. >> > >> > You would need to add the cost of the enclosure, the PSU, the diversity >> > and >> > selectivity RF daughter board we need to pass the spec and the CPU >> > mother >> > board we need to run the Transceiver and OpenBTS. You should expect a >> > total >> > cost around 800 USD excluding the frontend (PA+LNA+duplexers). >> > >> > For your information, the dual TRX outdoor enclosure frontend with 10 >> > Watts >> > PA I can get from my Chinese supplier costs 810 USD + shipping. >> > >> > Please do not hesitate to contact me if you need any extra figures or >> > information. >> > >> > Best regards. >> > >> > Jean-Samuel. >> > :-) >> > >> > >> > >> > On Sun, Jul 15, 2012 at 9:08 AM, Alexander Chemeris >> > wrote: >> >> >> >> Hi Jean-Samuel, >> >> >> >> Could you share the prices you get for UmTRX from your fab for this >> >> batch of prototypes and for the next batches? We have to understand >> >> the cost price to see what could we offer to customers. >> >> >> >> -- >> >> Regards, >> >> Alexander Chemeris. >> >> CEO, Fairwaves LLC / ??? ??????? >> >> http://fairwaves.ru >> > >> > >> >> >> >> -- >> Regards, >> Alexander Chemeris. >> CEO, Fairwaves LLC / ??? ??????? >> http://fairwaves.ru > > -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From jsn at bjtpartners.com Sun Jul 15 17:58:09 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Sun, 15 Jul 2012 19:58:09 +0200 Subject: UmTRX prototypes cost In-Reply-To: References: Message-ID: Hi Alexander, Yes, all the manual handling operations we would need is also what makes me feel a bit afraid of the cost too. In France, including all the costs they need to pay for, a fab would charge manual operations around 30 Euros per hour. Regarding the UmTRX samples production schedule, I do not think this will be ready at the beginning of August. We should expect to get the boards in mid-August. Sorry for the delay. Actually, everything is slower in France from around July 14th to August 15th. I am really sorry about that. Next batches will be faster. Best regards. Jean-Samuel. :-) On Sun, Jul 15, 2012 at 6:57 PM, Alexander Chemeris < alexander.chemeris at gmail.com> wrote: > Jean-Samuel, > > Ok, we'll prepare drawings for the enclosure. But my assumption was > that the biggest part of the cost would be handling, as it's a manual > operation and prices in Europe for this are insane. > > I hope you have a good vacation! We'll try to mail you as little as > possible :) > > Before you leave - could you update us whether the original estimation > for this batch of UmTRX production is correct, i.e. we'll get > prototypes at the first week of Aug? > > On Sun, Jul 15, 2012 at 8:46 PM, Jean-Samuel Najnudel - BJT PARTNERS > SARL wrote: > > Hi Alexander, > > > > Yes, this is a very good news. Except for selectivity, the UmTRX > > performances and features are great and you still have a reasonable cost > > structure. > > > > Regarding the enclosure, I think the fab can do this. However, they would > > need to know the exact drawing of all the connectors. They really need > > precise details before they accept to send me a quote. > > > > Moreover, most of the volume order will need outdoor enclosure including > the > > UmTRX, the diversity and selectivity daughter board and the CPU board. > > UmTRX only in an enclosure will be only interesting for some lab > > applications (excluding people who are ok with the board without any > > enclosure). This would make the volume quite low and I am afraid low > volume > > would mean quite high price. For the board itself, the fab makes some > > efforts on the price because they expect reasonably larger volumes but > for > > this enclosure for lab applications only, they will probably be quite > > expensive. > > > > If you are still interested in this enclosure assembly, please send me > the > > exact drawing and I will ask them for a quote. > > > > By the way, I will be on holidays on next week. I may take some time to > > reply to your e-mails. Sorry about this. > > > > Best regards. > > > > Jean-Samuel. > > :-) > > > > > > > > On Sun, Jul 15, 2012 at 5:50 PM, Alexander Chemeris > > wrote: > >> > >> Hi Jean-Samuel, > >> > >> This is very good news! It means we've met the target cost price and > >> we haven't compromised functionality. > >> > >> Could you ask the fab how much would it cost to put the board into an > >> enclosure like this, including the front panel and the rear panel > >> drilling and engraving? > >> > >> > http://www.fischerelektronik.de/web_fischer/en_GB/cases/M1.07/Miniature%20aluminium%20cases/PR/AKG105_030_/$productCard/dimensionParameters/index.xhtml > >> > >> The idea is to sell it to general public in small quantities for in-lab > >> use. > >> > >> On Sun, Jul 15, 2012 at 7:08 PM, Jean-Samuel Najnudel - BJT PARTNERS > >> SARL wrote: > >> > Hi Alexander, > >> > > >> > Total cost for production is approximately 10000 Euros for 20 units, > >> > including about 1000 Euros Non Recuring Costs. Approximate unit cost > for > >> > sample batches (6 and 14 units each) is a bit bellow 500 Euros. > >> > > >> > If we do not need to change the PCB, unit cost will be around 440 > Euros > >> > for > >> > 20 units batches. > >> > > >> > If we make 50 or 100 units batches, cost could be a bit lower but not > >> > that > >> > much. > >> > > >> > We could expect to save on the TCD-4029-26.0M. Today, we pay it about > 15 > >> > Euros because of our low volume. For 50 or 100 units, we could buy > this > >> > part > >> > directly from Pletronics and save about 5 or 6 Euros per unit. > >> > > >> > We could also save on the PCB. For 20 units, cost is 32 Euros but we > >> > could > >> > expect to save 5 to 10 Euros on it. > >> > > >> > On all other components, we could expect something like about 10 to 15 > >> > Euros > >> > extra savings. > >> > > >> > For 50 units batches instead of 20 units, we could also save about 4 > >> > Euros > >> > per board on the cost the fab charges for loading the assembly > machines. > >> > > >> > For 50 units batches, we could achieve a unit production cost at 500 > >> > USD. > >> > > >> > Anyway, please find enclosed a few details about our production costs. > >> > You > >> > can see fab costs are quite reasonable expecially for our low and > medium > >> > volumes. This cost structure is really convenient to make our samples > >> > and > >> > gradually ramp up our production volumes. In case we reach much higher > >> > volumes in the future, I am quite confident we could bargain a bit > more > >> > the > >> > fab costs and certainly also save a bit more on the components > sourcing > >> > costs. Except for the low cost femtocells market, I really believe > this > >> > cost > >> > structure will allow you to compete on the market in good conditions. > >> > > >> > You would need to add the cost of the enclosure, the PSU, the > diversity > >> > and > >> > selectivity RF daughter board we need to pass the spec and the CPU > >> > mother > >> > board we need to run the Transceiver and OpenBTS. You should expect a > >> > total > >> > cost around 800 USD excluding the frontend (PA+LNA+duplexers). > >> > > >> > For your information, the dual TRX outdoor enclosure frontend with 10 > >> > Watts > >> > PA I can get from my Chinese supplier costs 810 USD + shipping. > >> > > >> > Please do not hesitate to contact me if you need any extra figures or > >> > information. > >> > > >> > Best regards. > >> > > >> > Jean-Samuel. > >> > :-) > >> > > >> > > >> > > >> > On Sun, Jul 15, 2012 at 9:08 AM, Alexander Chemeris > >> > wrote: > >> >> > >> >> Hi Jean-Samuel, > >> >> > >> >> Could you share the prices you get for UmTRX from your fab for this > >> >> batch of prototypes and for the next batches? We have to understand > >> >> the cost price to see what could we offer to customers. > >> >> > >> >> -- > >> >> Regards, > >> >> Alexander Chemeris. > >> >> CEO, Fairwaves LLC / ??? ??????? > >> >> http://fairwaves.ru > >> > > >> > > >> > >> > >> > >> -- > >> Regards, > >> Alexander Chemeris. > >> CEO, Fairwaves LLC / ??? ??????? > >> http://fairwaves.ru > > > > > > > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Sun Jul 15 18:53:00 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sun, 15 Jul 2012 22:53:00 +0400 Subject: UmTRX prototypes cost In-Reply-To: References: Message-ID: Ok, thank you for the update. On Sun, Jul 15, 2012 at 9:58 PM, Jean-Samuel Najnudel - BJT PARTNERS SARL wrote: > Hi Alexander, > > Yes, all the manual handling operations we would need is also what makes me > feel a bit afraid of the cost too. In France, including all the costs they > need to pay for, a fab would charge manual operations around 30 Euros per > hour. > > Regarding the UmTRX samples production schedule, I do not think this will be > ready at the beginning of August. We should expect to get the boards in > mid-August. Sorry for the delay. Actually, everything is slower in France > from around July 14th to August 15th. I am really sorry about that. Next > batches will be faster. > > Best regards. > > Jean-Samuel. > :-) > > > > On Sun, Jul 15, 2012 at 6:57 PM, Alexander Chemeris > wrote: >> >> Jean-Samuel, >> >> Ok, we'll prepare drawings for the enclosure. But my assumption was >> that the biggest part of the cost would be handling, as it's a manual >> operation and prices in Europe for this are insane. >> >> I hope you have a good vacation! We'll try to mail you as little as >> possible :) >> >> Before you leave - could you update us whether the original estimation >> for this batch of UmTRX production is correct, i.e. we'll get >> prototypes at the first week of Aug? >> >> On Sun, Jul 15, 2012 at 8:46 PM, Jean-Samuel Najnudel - BJT PARTNERS >> SARL wrote: >> > Hi Alexander, >> > >> > Yes, this is a very good news. Except for selectivity, the UmTRX >> > performances and features are great and you still have a reasonable cost >> > structure. >> > >> > Regarding the enclosure, I think the fab can do this. However, they >> > would >> > need to know the exact drawing of all the connectors. They really need >> > precise details before they accept to send me a quote. >> > >> > Moreover, most of the volume order will need outdoor enclosure including >> > the >> > UmTRX, the diversity and selectivity daughter board and the CPU board. >> > UmTRX only in an enclosure will be only interesting for some lab >> > applications (excluding people who are ok with the board without any >> > enclosure). This would make the volume quite low and I am afraid low >> > volume >> > would mean quite high price. For the board itself, the fab makes some >> > efforts on the price because they expect reasonably larger volumes but >> > for >> > this enclosure for lab applications only, they will probably be quite >> > expensive. >> > >> > If you are still interested in this enclosure assembly, please send me >> > the >> > exact drawing and I will ask them for a quote. >> > >> > By the way, I will be on holidays on next week. I may take some time to >> > reply to your e-mails. Sorry about this. >> > >> > Best regards. >> > >> > Jean-Samuel. >> > :-) >> > >> > >> > >> > On Sun, Jul 15, 2012 at 5:50 PM, Alexander Chemeris >> > wrote: >> >> >> >> Hi Jean-Samuel, >> >> >> >> This is very good news! It means we've met the target cost price and >> >> we haven't compromised functionality. >> >> >> >> Could you ask the fab how much would it cost to put the board into an >> >> enclosure like this, including the front panel and the rear panel >> >> drilling and engraving? >> >> >> >> >> >> http://www.fischerelektronik.de/web_fischer/en_GB/cases/M1.07/Miniature%20aluminium%20cases/PR/AKG105_030_/$productCard/dimensionParameters/index.xhtml >> >> >> >> The idea is to sell it to general public in small quantities for in-lab >> >> use. >> >> >> >> On Sun, Jul 15, 2012 at 7:08 PM, Jean-Samuel Najnudel - BJT PARTNERS >> >> SARL wrote: >> >> > Hi Alexander, >> >> > >> >> > Total cost for production is approximately 10000 Euros for 20 units, >> >> > including about 1000 Euros Non Recuring Costs. Approximate unit cost >> >> > for >> >> > sample batches (6 and 14 units each) is a bit bellow 500 Euros. >> >> > >> >> > If we do not need to change the PCB, unit cost will be around 440 >> >> > Euros >> >> > for >> >> > 20 units batches. >> >> > >> >> > If we make 50 or 100 units batches, cost could be a bit lower but not >> >> > that >> >> > much. >> >> > >> >> > We could expect to save on the TCD-4029-26.0M. Today, we pay it about >> >> > 15 >> >> > Euros because of our low volume. For 50 or 100 units, we could buy >> >> > this >> >> > part >> >> > directly from Pletronics and save about 5 or 6 Euros per unit. >> >> > >> >> > We could also save on the PCB. For 20 units, cost is 32 Euros but we >> >> > could >> >> > expect to save 5 to 10 Euros on it. >> >> > >> >> > On all other components, we could expect something like about 10 to >> >> > 15 >> >> > Euros >> >> > extra savings. >> >> > >> >> > For 50 units batches instead of 20 units, we could also save about 4 >> >> > Euros >> >> > per board on the cost the fab charges for loading the assembly >> >> > machines. >> >> > >> >> > For 50 units batches, we could achieve a unit production cost at 500 >> >> > USD. >> >> > >> >> > Anyway, please find enclosed a few details about our production >> >> > costs. >> >> > You >> >> > can see fab costs are quite reasonable expecially for our low and >> >> > medium >> >> > volumes. This cost structure is really convenient to make our samples >> >> > and >> >> > gradually ramp up our production volumes. In case we reach much >> >> > higher >> >> > volumes in the future, I am quite confident we could bargain a bit >> >> > more >> >> > the >> >> > fab costs and certainly also save a bit more on the components >> >> > sourcing >> >> > costs. Except for the low cost femtocells market, I really believe >> >> > this >> >> > cost >> >> > structure will allow you to compete on the market in good conditions. >> >> > >> >> > You would need to add the cost of the enclosure, the PSU, the >> >> > diversity >> >> > and >> >> > selectivity RF daughter board we need to pass the spec and the CPU >> >> > mother >> >> > board we need to run the Transceiver and OpenBTS. You should expect a >> >> > total >> >> > cost around 800 USD excluding the frontend (PA+LNA+duplexers). >> >> > >> >> > For your information, the dual TRX outdoor enclosure frontend with 10 >> >> > Watts >> >> > PA I can get from my Chinese supplier costs 810 USD + shipping. >> >> > >> >> > Please do not hesitate to contact me if you need any extra figures or >> >> > information. >> >> > >> >> > Best regards. >> >> > >> >> > Jean-Samuel. >> >> > :-) >> >> > >> >> > >> >> > >> >> > On Sun, Jul 15, 2012 at 9:08 AM, Alexander Chemeris >> >> > wrote: >> >> >> >> >> >> Hi Jean-Samuel, >> >> >> >> >> >> Could you share the prices you get for UmTRX from your fab for this >> >> >> batch of prototypes and for the next batches? We have to understand >> >> >> the cost price to see what could we offer to customers. >> >> >> >> >> >> -- >> >> >> Regards, >> >> >> Alexander Chemeris. >> >> >> CEO, Fairwaves LLC / ??? ??????? >> >> >> http://fairwaves.ru >> >> > >> >> > >> >> >> >> >> >> >> >> -- >> >> Regards, >> >> Alexander Chemeris. >> >> CEO, Fairwaves LLC / ??? ??????? >> >> http://fairwaves.ru >> > >> > >> >> >> >> -- >> Regards, >> Alexander Chemeris. >> CEO, Fairwaves LLC / ??? ??????? >> http://fairwaves.ru > > -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Mon Jul 16 14:52:53 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Mon, 16 Jul 2012 18:52:53 +0400 Subject: [rfc] git workflow model In-Reply-To: <5002F45F.6040204@fairwaves.ru> References: <5002F45F.6040204@fairwaves.ru> Message-ID: Hi, On Sun, Jul 15, 2012 at 8:48 PM, ? wrote: > Hello. > > I'd like to test new ML anyway so here is my question :) > > I've stumbled upon pretty interesting $subj at > http://nvie.com/posts/a-successful-git-branching-model/ (Russian translation is > available at http://habrahabr.ru/post/147260/ ). > > What do you think of it guys? Should we try to adopt it? Or at least document > whatever model we use now? I need some time to read the post, but in general it's a good idea to describe branching policy. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Mon Jul 16 14:59:00 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Mon, 16 Jul 2012 18:59:00 +0400 Subject: LMS6002D documentation Message-ID: Hi all, I've pushed more public documentation for LMS6002D to the repository: https://github.com/chemeris/lms6002-documentation FAQ should be very interesting for everyone - recommended reading. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Mon Jul 16 14:59:00 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Mon, 16 Jul 2012 18:59:00 +0400 Subject: LMS6002D documentation Message-ID: Hi all, I've pushed more public documentation for LMS6002D to the repository: https://github.com/chemeris/lms6002-documentation FAQ should be very interesting for everyone - recommended reading. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From plddesigner at gmail.com Mon Jul 16 20:14:59 2012 From: plddesigner at gmail.com (Andrew Karpenkov) Date: Tue, 17 Jul 2012 00:14:59 +0400 Subject: Dual-channel Tx In-Reply-To: References: Message-ID: Hi All, I added one more RX and TX units and connected them to the second LMS chip. You can find fpga sources with full supply (both, receive and transmit) of dual channel at akarpenkov/dual-channel branch of github repository. Also, we need to make some changes in HOST code: - SR_RX_FRONT0 (base adress of RX0 frontend) was changed from 24 to 20 (dec) - SR_RX_FRONT1 (base adress of RX1 frontend) was added with value = 25 (dec) - SR_TX_FRONT (base adress of TX0 frontend) was changed from 128 to 110 (dec) - SR_TX_CTRL (base adress of control logic of TX0 channel) was changed from 144 to 126 (dec) - SR_TX_DSP (base adress of DSP TX0 unit) was changed from 160 to 135 (dec) - SR_TX1_FRONT (base adress of TX1 frontend) was added with value = 145 (dec) - SR_TX1_CTRL (base adress of control logic of TX1 channel) was added with value = 161 (dec) - SR_TX1_DSP (base adress of TX1 channel) was added with value = 170 (dec) - Setting register to program the UDP TX DSP port (16 + 1 in dec) are now 32 bit wide (udp dst0 port - lower 16 bits, udp dst1 port - higher 16 bits). I sent flash for FPGA to Alexander and he must publish files on the site soon. I should say, I have not tested work of the project. Please report any issues. Regards , Andrew Karpenkov -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Mon Jul 16 21:05:16 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Tue, 17 Jul 2012 01:05:16 +0400 Subject: Dual-channel Tx In-Reply-To: References: Message-ID: On Tue, Jul 17, 2012 at 12:14 AM, Andrew Karpenkov wrote: > Hi All, > > I added one more RX and TX units and connected them to the second LMS chip. > You can find fpga sources with full supply (both, receive and transmit) of > dual channel at akarpenkov/dual-channel branch of github repository. > > Also, we need to make some changes in HOST code: > > SR_RX_FRONT0 (base adress of RX0 frontend) was changed from 24 to 20 (dec) > SR_RX_FRONT1 (base adress of RX1 frontend) was added with value = 25 (dec) > SR_TX_FRONT (base adress of TX0 frontend) was changed from 128 to 110 (dec) > SR_TX_CTRL (base adress of control logic of TX0 channel) was changed from > 144 to 126 (dec) > SR_TX_DSP (base adress of DSP TX0 unit) was changed from 160 to 135 (dec) > SR_TX1_FRONT (base adress of TX1 frontend) was added with value = 145 (dec) > SR_TX1_CTRL (base adress of control logic of TX1 channel) was added with > value = 161 (dec) > SR_TX1_DSP (base adress of TX1 channel) was added with value = 170 (dec) > Setting register to program the UDP TX DSP port (16 + 1 in dec) are now 32 > bit wide (udp dst0 port - lower 16 bits, udp dst1 port - higher 16 bits). > > I sent flash for FPGA to Alexander and he must publish files on the site > soon. Get them here: http://people.osmocom.org/ipse/umtrx/fpga_bitsream/2012-07-16/ -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From andrey.sviyazov at fairwaves.ru Thu Jul 19 07:30:03 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 11:30:03 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Sorry, that was meant to be sent to the mailing list :) Best regards, Andrey Sviyazov. ---------- Forwarded message ---------- From: Andrey Sviyazov Date: 2012/7/18 Subject: LMS TxLO noise Hi Thomas. Here forwarded my last e-mail with noise plots when I stopped work around it at first time, please see below. Please try to play around Tx PLL charge pump current (register 0x16) for better RMS phase stability. I think we should reach 1 degree or below. Alexander gave me the second UmTRX board and after checking and fixing all known hardware issuesI've got roughly the same LO noise plot. Possible Robin had no time to fixing all of our issues, so check them all please. And also check please what type of TCXO installed on your board. Best regards, Andrey Sviyazov. ---------- Forwarded message ---------- From: Andrey Sviyazov Date: 2012/4/13 Subject: Re: LMS TxLO noise Hi all. There is progress with LMS PLL :) Pictures are attached here. t was discovered that 80 kHz spurs come from Ethernet, or rather from the ET1011. I unknowingly put the choke between transistor of 1V regulator and analog power 1V. As a result, the regulator has become unstable and oscillated 80 kHz with amplitude of 200 mV, which climbed into the LMS PLL. To correct this problem L46 should be replaced by jumper on all alfa version PCB's. Also I just played with current in the PLL loop, shown on the picture for clarity. Proved to be the optimal current 1,9 mA (you should write 0x93 in the register of 0x16). But, I think, for the RxPLL will be better use of the current 2.4 mA, because the nearest noises more important for Rx (you should write 0x98 in the register 0x26). Best regards, Andrey Sviyazov. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: TCD4029_925MHz_TxLO_noise#3_130412.png Type: image/png Size: 37905 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: TCD4029_925MHz_TxLO_spures#2_130412.png Type: image/png Size: 35467 bytes Desc: not available URL: From andrey.sviyazov at fairwaves.ru Thu Jul 19 07:30:03 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 11:30:03 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Sorry, that was meant to be sent to the mailing list :) Best regards, Andrey Sviyazov. ---------- Forwarded message ---------- From: Andrey Sviyazov Date: 2012/7/18 Subject: LMS TxLO noise Hi Thomas. Here forwarded my last e-mail with noise plots when I stopped work around it at first time, please see below. Please try to play around Tx PLL charge pump current (register 0x16) for better RMS phase stability. I think we should reach 1 degree or below. Alexander gave me the second UmTRX board and after checking and fixing all known hardware issuesI've got roughly the same LO noise plot. Possible Robin had no time to fixing all of our issues, so check them all please. And also check please what type of TCXO installed on your board. Best regards, Andrey Sviyazov. ---------- Forwarded message ---------- From: Andrey Sviyazov Date: 2012/4/13 Subject: Re: LMS TxLO noise Hi all. There is progress with LMS PLL :) Pictures are attached here. t was discovered that 80 kHz spurs come from Ethernet, or rather from the ET1011. I unknowingly put the choke between transistor of 1V regulator and analog power 1V. As a result, the regulator has become unstable and oscillated 80 kHz with amplitude of 200 mV, which climbed into the LMS PLL. To correct this problem L46 should be replaced by jumper on all alfa version PCB's. Also I just played with current in the PLL loop, shown on the picture for clarity. Proved to be the optimal current 1,9 mA (you should write 0x93 in the register of 0x16). But, I think, for the RxPLL will be better use of the current 2.4 mA, because the nearest noises more important for Rx (you should write 0x98 in the register 0x26). Best regards, Andrey Sviyazov. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: TCD4029_925MHz_TxLO_noise#3_130412.png Type: image/png Size: 37905 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: TCD4029_925MHz_TxLO_spures#2_130412.png Type: image/png Size: 35467 bytes Desc: not available URL: From andrey.sviyazov at fairwaves.ru Thu Jul 19 09:33:21 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 13:33:21 +0400 Subject: UmTRX dual-channel Rx Message-ID: Hi all. I found that both Rx divercity switches have zero state for A and B control inputs. Thus both LNA and LNA-D connectors are not switched to Rx inputs of the LMS's. To proceed Rx testing I suggest to set the next fixed states in the FPGA: DIVSW1_P = 1, DIVSW1_N = 0, DIVSW2_P = 1, DIVSW2_N = 0. In this case LMS1 will be switched to LNA connector, but LMS2 to LNA-D. Andrew Karpenkov, would you please to make this kind changes, until DIVSW will controled by host? Best regards, Andrey Sviyazov. -------------- next part -------------- An HTML attachment was scrubbed... URL: From andrey.sviyazov at fairwaves.ru Thu Jul 19 09:33:21 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 13:33:21 +0400 Subject: UmTRX dual-channel Rx Message-ID: Hi all. I found that both Rx divercity switches have zero state for A and B control inputs. Thus both LNA and LNA-D connectors are not switched to Rx inputs of the LMS's. To proceed Rx testing I suggest to set the next fixed states in the FPGA: DIVSW1_P = 1, DIVSW1_N = 0, DIVSW2_P = 1, DIVSW2_N = 0. In this case LMS1 will be switched to LNA connector, but LMS2 to LNA-D. Andrew Karpenkov, would you please to make this kind changes, until DIVSW will controled by host? Best regards, Andrey Sviyazov. -------------- next part -------------- An HTML attachment was scrubbed... URL: From plddesigner at gmail.com Thu Jul 19 09:49:49 2012 From: plddesigner at gmail.com (Andrew Karpenkov) Date: Thu, 19 Jul 2012 13:49:49 +0400 Subject: UmTRX dual-channel Rx In-Reply-To: References: Message-ID: Hi Andrey, I'll do it ASAP and then send you flash image for FPGA. Regards, Andrew Karpenkov 2012/7/19 Andrey Sviyazov > I found that both Rx divercity switches have zero state for A and B > control inputs. > Thus both LNA and LNA-D connectors are not switched to Rx inputs of the > LMS's. > To proceed Rx testing I suggest to set the next fixed states in the FPGA: > DIVSW1_P = 1, DIVSW1_N = 0, DIVSW2_P = 1, DIVSW2_N = 0. > In this case LMS1 will be switched to LNA connector, but LMS2 to LNA-D. > > Andrew Karpenkov, would you please to make this kind changes, until DIVSW > will controled by host? > -------------- next part -------------- An HTML attachment was scrubbed... URL: From plddesigner at gmail.com Thu Jul 19 09:49:49 2012 From: plddesigner at gmail.com (Andrew Karpenkov) Date: Thu, 19 Jul 2012 13:49:49 +0400 Subject: UmTRX dual-channel Rx In-Reply-To: References: Message-ID: Hi Andrey, I'll do it ASAP and then send you flash image for FPGA. Regards, Andrew Karpenkov 2012/7/19 Andrey Sviyazov > I found that both Rx divercity switches have zero state for A and B > control inputs. > Thus both LNA and LNA-D connectors are not switched to Rx inputs of the > LMS's. > To proceed Rx testing I suggest to set the next fixed states in the FPGA: > DIVSW1_P = 1, DIVSW1_N = 0, DIVSW2_P = 1, DIVSW2_N = 0. > In this case LMS1 will be switched to LNA connector, but LMS2 to LNA-D. > > Andrew Karpenkov, would you please to make this kind changes, until DIVSW > will controled by host? > -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Thu Jul 19 10:28:43 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Thu, 19 Jul 2012 14:28:43 +0400 Subject: UmTRX dual-channel Rx In-Reply-To: References: Message-ID: On Thu, Jul 19, 2012 at 1:33 PM, Andrey Sviyazov wrote: > Andrew Karpenkov, would you please to make this kind changes, until DIVSW > will controled by host? That's an interesting question. Andrey Karpenkov - is there a way to control them from ZPU? Some config register? -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Thu Jul 19 10:28:43 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Thu, 19 Jul 2012 14:28:43 +0400 Subject: UmTRX dual-channel Rx In-Reply-To: References: Message-ID: On Thu, Jul 19, 2012 at 1:33 PM, Andrey Sviyazov wrote: > Andrew Karpenkov, would you please to make this kind changes, until DIVSW > will controled by host? That's an interesting question. Andrey Karpenkov - is there a way to control them from ZPU? Some config register? -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From plddesigner at gmail.com Thu Jul 19 10:42:30 2012 From: plddesigner at gmail.com (Andrew Karpenkov) Date: Thu, 19 Jul 2012 14:42:30 +0400 Subject: UmTRX dual-channel Rx In-Reply-To: References: Message-ID: Yes, I can add this option. I'll try to do it, and tomorrow make changes at github. Regards, Andrew Karpenkov Sent from my Android device. 19.07.2012 14:29 ???????????? "Alexander Chemeris" < alexander.chemeris at gmail.com> ???????: > On Thu, Jul 19, 2012 at 1:33 PM, Andrey Sviyazov > wrote: > > Andrew Karpenkov, would you please to make this kind changes, until DIVSW > > will controled by host? > > That's an interesting question. Andrey Karpenkov - is there a way to > control them from ZPU? Some config register? > > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: From plddesigner at gmail.com Thu Jul 19 10:42:30 2012 From: plddesigner at gmail.com (Andrew Karpenkov) Date: Thu, 19 Jul 2012 14:42:30 +0400 Subject: UmTRX dual-channel Rx In-Reply-To: References: Message-ID: Yes, I can add this option. I'll try to do it, and tomorrow make changes at github. Regards, Andrew Karpenkov Sent from my Android device. 19.07.2012 14:29 ???????????? "Alexander Chemeris" < alexander.chemeris at gmail.com> ???????: > On Thu, Jul 19, 2012 at 1:33 PM, Andrey Sviyazov > wrote: > > Andrew Karpenkov, would you please to make this kind changes, until DIVSW > > will controled by host? > > That's an interesting question. Andrey Karpenkov - is there a way to > control them from ZPU? Some config register? > > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Thu Jul 19 11:25:04 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Thu, 19 Jul 2012 15:25:04 +0400 Subject: UmTRX dual-channel Rx In-Reply-To: References: Message-ID: Thanks. Looking forward for it. On Thu, Jul 19, 2012 at 2:42 PM, Andrew Karpenkov wrote: > Yes, I can add this option. I'll try to do it, and tomorrow make changes at > github. > > Regards, > Andrew Karpenkov > > Sent from my Android device. > > 19.07.2012 14:29 ???????????? "Alexander Chemeris" > ???????: > >> On Thu, Jul 19, 2012 at 1:33 PM, Andrey Sviyazov >> wrote: >> > Andrew Karpenkov, would you please to make this kind changes, until >> > DIVSW >> > will controled by host? >> >> That's an interesting question. Andrey Karpenkov - is there a way to >> control them from ZPU? Some config register? >> >> >> -- >> Regards, >> Alexander Chemeris. >> CEO, Fairwaves LLC / ??? ??????? >> http://fairwaves.ru -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Thu Jul 19 11:25:04 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Thu, 19 Jul 2012 15:25:04 +0400 Subject: UmTRX dual-channel Rx In-Reply-To: References: Message-ID: Thanks. Looking forward for it. On Thu, Jul 19, 2012 at 2:42 PM, Andrew Karpenkov wrote: > Yes, I can add this option. I'll try to do it, and tomorrow make changes at > github. > > Regards, > Andrew Karpenkov > > Sent from my Android device. > > 19.07.2012 14:29 ???????????? "Alexander Chemeris" > ???????: > >> On Thu, Jul 19, 2012 at 1:33 PM, Andrey Sviyazov >> wrote: >> > Andrew Karpenkov, would you please to make this kind changes, until >> > DIVSW >> > will controled by host? >> >> That's an interesting question. Andrey Karpenkov - is there a way to >> control them from ZPU? Some config register? >> >> >> -- >> Regards, >> Alexander Chemeris. >> CEO, Fairwaves LLC / ??? ??????? >> http://fairwaves.ru -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From andrey.sviyazov at fairwaves.ru Thu Jul 19 14:10:56 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 18:10:56 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi all. I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset when GPS antenna used and position locked. This spurs begin grow up when GPS just near to lock position and after locking spurs stopped to grow as you can see at picture. If thereafter GPS disconnected then noise coming back to normal plot. I think that it is result of 32768Hz clock in the GPS module EB-230, but can't understant how it can impact to 26MHz clock or VCO. Please tell me something who know. Thomas. Was GPS antenna connected when noise measured like on the picture which you sent us (also attached here)? I would to know because of anomal peak near to 30kHz offset too. Best regards, Andrey Sviyazov. 2012/7/19 Andrey Sviyazov > Sorry, that was meant to be sent to the mailing list :) > > Best regards, > Andrey Sviyazov. > > ---------- Forwarded message ---------- > From: Andrey Sviyazov > Date: 2012/7/18 > Subject: LMS TxLO noise > > Hi Thomas. > > Here forwarded my last e-mail with noise plots when I stopped work around > it at first time, please see below. > > Please try to play around Tx PLL charge pump current (register 0x16) for > better RMS phase stability. > I think we should reach 1 degree or below. > > Alexander gave me the second UmTRX board and after checking and fixing all > known hardware issuesI've got roughly the same LO noise plot. > Possible Robin had no time to fixing all of our issues, so check them all > please. > And also check please what type of TCXO installed on your board. > > Best regards, > Andrey Sviyazov. > > ---------- Forwarded message ---------- > From: Andrey Sviyazov > Date: 2012/4/13 > Subject: Re: LMS TxLO noise > > Hi all. > > There is progress with LMS PLL :) > Pictures are attached here. > t was discovered that 80 kHz spurs come from Ethernet, or rather from the > ET1011. > I unknowingly put the choke between transistor of 1V regulator and analog > power 1V. > As a result, the regulator has become unstable and oscillated 80 kHz with > amplitude of 200 mV, which climbed into the LMS PLL. > To correct this problem L46 should be replaced by jumper on all alfa > version PCB's. > > Also I just played with current in the PLL loop, shown on the picture for > clarity. > Proved to be the optimal current 1,9 mA (you should write 0x93 in the > register of 0x16). > But, I think, for the RxPLL will be better use of the current 2.4 mA, > because the nearest noises more important for Rx (you should write 0x98 in > the register 0x26). > > Best regards, > Andrey Sviyazov. > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: LO noise GPS dependance.png Type: image/png Size: 54641 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_phs_noise.JPG Type: image/jpeg Size: 123925 bytes Desc: not available URL: From andrey.sviyazov at fairwaves.ru Thu Jul 19 14:10:56 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 18:10:56 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi all. I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset when GPS antenna used and position locked. This spurs begin grow up when GPS just near to lock position and after locking spurs stopped to grow as you can see at picture. If thereafter GPS disconnected then noise coming back to normal plot. I think that it is result of 32768Hz clock in the GPS module EB-230, but can't understant how it can impact to 26MHz clock or VCO. Please tell me something who know. Thomas. Was GPS antenna connected when noise measured like on the picture which you sent us (also attached here)? I would to know because of anomal peak near to 30kHz offset too. Best regards, Andrey Sviyazov. 2012/7/19 Andrey Sviyazov > Sorry, that was meant to be sent to the mailing list :) > > Best regards, > Andrey Sviyazov. > > ---------- Forwarded message ---------- > From: Andrey Sviyazov > Date: 2012/7/18 > Subject: LMS TxLO noise > > Hi Thomas. > > Here forwarded my last e-mail with noise plots when I stopped work around > it at first time, please see below. > > Please try to play around Tx PLL charge pump current (register 0x16) for > better RMS phase stability. > I think we should reach 1 degree or below. > > Alexander gave me the second UmTRX board and after checking and fixing all > known hardware issuesI've got roughly the same LO noise plot. > Possible Robin had no time to fixing all of our issues, so check them all > please. > And also check please what type of TCXO installed on your board. > > Best regards, > Andrey Sviyazov. > > ---------- Forwarded message ---------- > From: Andrey Sviyazov > Date: 2012/4/13 > Subject: Re: LMS TxLO noise > > Hi all. > > There is progress with LMS PLL :) > Pictures are attached here. > t was discovered that 80 kHz spurs come from Ethernet, or rather from the > ET1011. > I unknowingly put the choke between transistor of 1V regulator and analog > power 1V. > As a result, the regulator has become unstable and oscillated 80 kHz with > amplitude of 200 mV, which climbed into the LMS PLL. > To correct this problem L46 should be replaced by jumper on all alfa > version PCB's. > > Also I just played with current in the PLL loop, shown on the picture for > clarity. > Proved to be the optimal current 1,9 mA (you should write 0x93 in the > register of 0x16). > But, I think, for the RxPLL will be better use of the current 2.4 mA, > because the nearest noises more important for Rx (you should write 0x98 in > the register 0x26). > > Best regards, > Andrey Sviyazov. > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: LO noise GPS dependance.png Type: image/png Size: 54641 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_phs_noise.JPG Type: image/jpeg Size: 123925 bytes Desc: not available URL: From andrey.sviyazov at fairwaves.ru Thu Jul 19 14:29:57 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 18:29:57 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Sergey. Is it really so frequently (32k/s updates at 1pps reference)? Best regards, Andrey Sviyazov. 2012/7/19 sergey kostanbaev > > > On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov < > andrey.sviyazov at fairwaves.ru> wrote: > >> Hi all. >> >> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset when >> GPS antenna used and position locked. >> This spurs begin grow up when GPS just near to lock position and after >> locking spurs stopped to grow as you can see at picture. >> If thereafter GPS disconnected then noise coming back to normal plot. >> I think that it is result of 32768Hz clock in the GPS module EB-230, but >> can't understant how it can impact to 26MHz clock or VCO. >> > > As another idea it can be caused by continues GPS correction lead to DAC > changes to the VCTXCO. > > >> Please tell me something who know. >> >> Thomas. >> Was GPS antenna connected when noise measured like on the picture which >> you sent us (also attached here)? >> I would to know because of anomal peak near to 30kHz offset too. >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/19 Andrey Sviyazov >> >>> Sorry, that was meant to be sent to the mailing list :) >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> ---------- Forwarded message ---------- >>> From: Andrey Sviyazov >>> Date: 2012/7/18 >>> Subject: LMS TxLO noise >>> >>> Hi Thomas. >>> >>> Here forwarded my last e-mail with noise plots when I stopped work >>> around it at first time, please see below. >>> >>> Please try to play around Tx PLL charge pump current (register 0x16) for >>> better RMS phase stability. >>> I think we should reach 1 degree or below. >>> >>> Alexander gave me the second UmTRX board and after checking and fixing >>> all known hardware issuesI've got roughly the same LO noise plot. >>> Possible Robin had no time to fixing all of our issues, so check them >>> all please. >>> And also check please what type of TCXO installed on your board. >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> ---------- Forwarded message ---------- >>> From: Andrey Sviyazov >>> Date: 2012/4/13 >>> Subject: Re: LMS TxLO noise >>> >>> Hi all. >>> >>> There is progress with LMS PLL :) >>> Pictures are attached here. >>> t was discovered that 80 kHz spurs come from Ethernet, or rather from >>> the ET1011. >>> I unknowingly put the choke between transistor of 1V regulator and >>> analog power 1V. >>> As a result, the regulator has become unstable and oscillated 80 kHz >>> with amplitude of 200 mV, which climbed into the LMS PLL. >>> To correct this problem L46 should be replaced by jumper on all alfa >>> version PCB's. >>> >>> Also I just played with current in the PLL loop, shown on the picture >>> for clarity. >>> Proved to be the optimal current 1,9 mA (you should write 0x93 in the >>> register of 0x16). >>> But, I think, for the RxPLL will be better use of the current 2.4 mA, >>> because the nearest noises more important for Rx (you should write 0x98 in >>> the register 0x26). >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andrey.sviyazov at fairwaves.ru Thu Jul 19 14:29:57 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 18:29:57 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Sergey. Is it really so frequently (32k/s updates at 1pps reference)? Best regards, Andrey Sviyazov. 2012/7/19 sergey kostanbaev > > > On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov < > andrey.sviyazov at fairwaves.ru> wrote: > >> Hi all. >> >> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset when >> GPS antenna used and position locked. >> This spurs begin grow up when GPS just near to lock position and after >> locking spurs stopped to grow as you can see at picture. >> If thereafter GPS disconnected then noise coming back to normal plot. >> I think that it is result of 32768Hz clock in the GPS module EB-230, but >> can't understant how it can impact to 26MHz clock or VCO. >> > > As another idea it can be caused by continues GPS correction lead to DAC > changes to the VCTXCO. > > >> Please tell me something who know. >> >> Thomas. >> Was GPS antenna connected when noise measured like on the picture which >> you sent us (also attached here)? >> I would to know because of anomal peak near to 30kHz offset too. >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/19 Andrey Sviyazov >> >>> Sorry, that was meant to be sent to the mailing list :) >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> ---------- Forwarded message ---------- >>> From: Andrey Sviyazov >>> Date: 2012/7/18 >>> Subject: LMS TxLO noise >>> >>> Hi Thomas. >>> >>> Here forwarded my last e-mail with noise plots when I stopped work >>> around it at first time, please see below. >>> >>> Please try to play around Tx PLL charge pump current (register 0x16) for >>> better RMS phase stability. >>> I think we should reach 1 degree or below. >>> >>> Alexander gave me the second UmTRX board and after checking and fixing >>> all known hardware issuesI've got roughly the same LO noise plot. >>> Possible Robin had no time to fixing all of our issues, so check them >>> all please. >>> And also check please what type of TCXO installed on your board. >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> ---------- Forwarded message ---------- >>> From: Andrey Sviyazov >>> Date: 2012/4/13 >>> Subject: Re: LMS TxLO noise >>> >>> Hi all. >>> >>> There is progress with LMS PLL :) >>> Pictures are attached here. >>> t was discovered that 80 kHz spurs come from Ethernet, or rather from >>> the ET1011. >>> I unknowingly put the choke between transistor of 1V regulator and >>> analog power 1V. >>> As a result, the regulator has become unstable and oscillated 80 kHz >>> with amplitude of 200 mV, which climbed into the LMS PLL. >>> To correct this problem L46 should be replaced by jumper on all alfa >>> version PCB's. >>> >>> Also I just played with current in the PLL loop, shown on the picture >>> for clarity. >>> Proved to be the optimal current 1,9 mA (you should write 0x93 in the >>> register of 0x16). >>> But, I think, for the RxPLL will be better use of the current 2.4 mA, >>> because the nearest noises more important for Rx (you should write 0x98 in >>> the register 0x26). >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andrey.sviyazov at fairwaves.ru Thu Jul 19 14:41:18 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 18:41:18 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC input. Of course I'll increase capacitance or resistance to be sure about VC pin. Best regards, Andrey Sviyazov. 2012/7/19 sergey kostanbaev > No :) But it may cause. > > I'd check all the line from FPGA to DAC to VCTXCO because VC pin is really > sensible to any noise. > - caused by power supply of DAC. > - output noise of DAC. > - algorithm of changing values > > At first I'd inspect VC pin at VCTXCO and try to filter it with cut-off > frequency 1-0.1 Hz > > > On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov < > andrey.sviyazov at fairwaves.ru> wrote: > >> Sergey. >> Is it really so frequently (32k/s updates at 1pps reference)? >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/19 sergey kostanbaev >> >>> >>> >>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov < >>> andrey.sviyazov at fairwaves.ru> wrote: >>> >>>> Hi all. >>>> >>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset when >>>> GPS antenna used and position locked. >>>> This spurs begin grow up when GPS just near to lock position and after >>>> locking spurs stopped to grow as you can see at picture. >>>> If thereafter GPS disconnected then noise coming back to normal plot. >>>> I think that it is result of 32768Hz clock in the GPS module EB-230, >>>> but can't understant how it can impact to 26MHz clock or VCO. >>>> >>> >>> As another idea it can be caused by continues GPS correction lead to DAC >>> changes to the VCTXCO. >>> >>> >>>> Please tell me something who know. >>>> >>>> Thomas. >>>> Was GPS antenna connected when noise measured like on the picture which >>>> you sent us (also attached here)? >>>> I would to know because of anomal peak near to 30kHz offset too. >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> >>>> >>>> 2012/7/19 Andrey Sviyazov >>>> >>>>> Sorry, that was meant to be sent to the mailing list :) >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> ---------- Forwarded message ---------- >>>>> From: Andrey Sviyazov >>>>> Date: 2012/7/18 >>>>> Subject: LMS TxLO noise >>>>> >>>>> Hi Thomas. >>>>> >>>>> Here forwarded my last e-mail with noise plots when I stopped work >>>>> around it at first time, please see below. >>>>> >>>>> Please try to play around Tx PLL charge pump current (register 0x16) >>>>> for better RMS phase stability. >>>>> I think we should reach 1 degree or below. >>>>> >>>>> Alexander gave me the second UmTRX board and after checking and fixing >>>>> all known hardware issuesI've got roughly the same LO noise plot. >>>>> Possible Robin had no time to fixing all of our issues, so check them >>>>> all please. >>>>> And also check please what type of TCXO installed on your board. >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> ---------- Forwarded message ---------- >>>>> From: Andrey Sviyazov >>>>> Date: 2012/4/13 >>>>> Subject: Re: LMS TxLO noise >>>>> >>>>> Hi all. >>>>> >>>>> There is progress with LMS PLL :) >>>>> Pictures are attached here. >>>>> t was discovered that 80 kHz spurs come from Ethernet, or rather from >>>>> the ET1011. >>>>> I unknowingly put the choke between transistor of 1V regulator and >>>>> analog power 1V. >>>>> As a result, the regulator has become unstable and oscillated 80 kHz >>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>>>> To correct this problem L46 should be replaced by jumper on all alfa >>>>> version PCB's. >>>>> >>>>> Also I just played with current in the PLL loop, shown on the picture >>>>> for clarity. >>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in the >>>>> register of 0x16). >>>>> But, I think, for the RxPLL will be better use of the current 2.4 mA, >>>>> because the nearest noises more important for Rx (you should write 0x98 in >>>>> the register 0x26). >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> >>>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andrey.sviyazov at fairwaves.ru Thu Jul 19 14:41:18 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 18:41:18 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC input. Of course I'll increase capacitance or resistance to be sure about VC pin. Best regards, Andrey Sviyazov. 2012/7/19 sergey kostanbaev > No :) But it may cause. > > I'd check all the line from FPGA to DAC to VCTXCO because VC pin is really > sensible to any noise. > - caused by power supply of DAC. > - output noise of DAC. > - algorithm of changing values > > At first I'd inspect VC pin at VCTXCO and try to filter it with cut-off > frequency 1-0.1 Hz > > > On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov < > andrey.sviyazov at fairwaves.ru> wrote: > >> Sergey. >> Is it really so frequently (32k/s updates at 1pps reference)? >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/19 sergey kostanbaev >> >>> >>> >>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov < >>> andrey.sviyazov at fairwaves.ru> wrote: >>> >>>> Hi all. >>>> >>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset when >>>> GPS antenna used and position locked. >>>> This spurs begin grow up when GPS just near to lock position and after >>>> locking spurs stopped to grow as you can see at picture. >>>> If thereafter GPS disconnected then noise coming back to normal plot. >>>> I think that it is result of 32768Hz clock in the GPS module EB-230, >>>> but can't understant how it can impact to 26MHz clock or VCO. >>>> >>> >>> As another idea it can be caused by continues GPS correction lead to DAC >>> changes to the VCTXCO. >>> >>> >>>> Please tell me something who know. >>>> >>>> Thomas. >>>> Was GPS antenna connected when noise measured like on the picture which >>>> you sent us (also attached here)? >>>> I would to know because of anomal peak near to 30kHz offset too. >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> >>>> >>>> 2012/7/19 Andrey Sviyazov >>>> >>>>> Sorry, that was meant to be sent to the mailing list :) >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> ---------- Forwarded message ---------- >>>>> From: Andrey Sviyazov >>>>> Date: 2012/7/18 >>>>> Subject: LMS TxLO noise >>>>> >>>>> Hi Thomas. >>>>> >>>>> Here forwarded my last e-mail with noise plots when I stopped work >>>>> around it at first time, please see below. >>>>> >>>>> Please try to play around Tx PLL charge pump current (register 0x16) >>>>> for better RMS phase stability. >>>>> I think we should reach 1 degree or below. >>>>> >>>>> Alexander gave me the second UmTRX board and after checking and fixing >>>>> all known hardware issuesI've got roughly the same LO noise plot. >>>>> Possible Robin had no time to fixing all of our issues, so check them >>>>> all please. >>>>> And also check please what type of TCXO installed on your board. >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> ---------- Forwarded message ---------- >>>>> From: Andrey Sviyazov >>>>> Date: 2012/4/13 >>>>> Subject: Re: LMS TxLO noise >>>>> >>>>> Hi all. >>>>> >>>>> There is progress with LMS PLL :) >>>>> Pictures are attached here. >>>>> t was discovered that 80 kHz spurs come from Ethernet, or rather from >>>>> the ET1011. >>>>> I unknowingly put the choke between transistor of 1V regulator and >>>>> analog power 1V. >>>>> As a result, the regulator has become unstable and oscillated 80 kHz >>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>>>> To correct this problem L46 should be replaced by jumper on all alfa >>>>> version PCB's. >>>>> >>>>> Also I just played with current in the PLL loop, shown on the picture >>>>> for clarity. >>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in the >>>>> register of 0x16). >>>>> But, I think, for the RxPLL will be better use of the current 2.4 mA, >>>>> because the nearest noises more important for Rx (you should write 0x98 in >>>>> the register 0x26). >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> >>>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andrey.sviyazov at fairwaves.ru Thu Jul 19 14:56:40 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 18:56:40 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Sergey. I'll play around GPS power and RTC supply, thank you for your help. Thomas. About r0x16 please be sure that sometimes it isn't set to default value after power up (I saw it few times). Also I think that possible those bad "power on reset" gave us unstable result of LMS autocalibration. Best regards, Andrey Sviyazov. 2012/7/19 sergey kostanbaev > Which gives ~1.5khz cut-off, that's strange > > Also I'd check GPS VDD and AVDD nosies > > > On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov < > andrey.sviyazov at fairwaves.ru> wrote: > >> 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC input. >> Of course I'll increase capacitance or resistance to be sure about VC pin. >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/19 sergey kostanbaev >> >>> No :) But it may cause. >>> >>> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is >>> really sensible to any noise. >>> - caused by power supply of DAC. >>> - output noise of DAC. >>> - algorithm of changing values >>> >>> At first I'd inspect VC pin at VCTXCO and try to filter it with cut-off >>> frequency 1-0.1 Hz >>> >>> >>> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov < >>> andrey.sviyazov at fairwaves.ru> wrote: >>> >>>> Sergey. >>>> Is it really so frequently (32k/s updates at 1pps reference)? >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> >>>> >>>> 2012/7/19 sergey kostanbaev >>>> >>>>> >>>>> >>>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov < >>>>> andrey.sviyazov at fairwaves.ru> wrote: >>>>> >>>>>> Hi all. >>>>>> >>>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset >>>>>> when GPS antenna used and position locked. >>>>>> This spurs begin grow up when GPS just near to lock position and >>>>>> after locking spurs stopped to grow as you can see at picture. >>>>>> If thereafter GPS disconnected then noise coming back to normal plot. >>>>>> I think that it is result of 32768Hz clock in the GPS module EB-230, >>>>>> but can't understant how it can impact to 26MHz clock or VCO. >>>>>> >>>>> >>>>> As another idea it can be caused by continues GPS correction lead to >>>>> DAC changes to the VCTXCO. >>>>> >>>>> >>>>>> Please tell me something who know. >>>>>> >>>>>> Thomas. >>>>>> Was GPS antenna connected when noise measured like on the picture >>>>>> which you sent us (also attached here)? >>>>>> I would to know because of anomal peak near to 30kHz offset too. >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> >>>>>> >>>>>> >>>>>> 2012/7/19 Andrey Sviyazov >>>>>> >>>>>>> Sorry, that was meant to be sent to the mailing list :) >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> >>>>>>> ---------- Forwarded message ---------- >>>>>>> From: Andrey Sviyazov >>>>>>> Date: 2012/7/18 >>>>>>> Subject: LMS TxLO noise >>>>>>> >>>>>>> Hi Thomas. >>>>>>> >>>>>>> Here forwarded my last e-mail with noise plots when I stopped work >>>>>>> around it at first time, please see below. >>>>>>> >>>>>>> Please try to play around Tx PLL charge pump current (register 0x16) >>>>>>> for better RMS phase stability. >>>>>>> I think we should reach 1 degree or below. >>>>>>> >>>>>>> Alexander gave me the second UmTRX board and after checking and >>>>>>> fixing all known hardware issuesI've got roughly the same LO noise plot. >>>>>>> Possible Robin had no time to fixing all of our issues, so check >>>>>>> them all please. >>>>>>> And also check please what type of TCXO installed on your board. >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> >>>>>>> ---------- Forwarded message ---------- >>>>>>> From: Andrey Sviyazov >>>>>>> Date: 2012/4/13 >>>>>>> Subject: Re: LMS TxLO noise >>>>>>> >>>>>>> Hi all. >>>>>>> >>>>>>> There is progress with LMS PLL :) >>>>>>> Pictures are attached here. >>>>>>> t was discovered that 80 kHz spurs come from Ethernet, or rather >>>>>>> from the ET1011. >>>>>>> I unknowingly put the choke between transistor of 1V regulator and >>>>>>> analog power 1V. >>>>>>> As a result, the regulator has become unstable and oscillated 80 kHz >>>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>>>>>> To correct this problem L46 should be replaced by jumper on all alfa >>>>>>> version PCB's. >>>>>>> >>>>>>> Also I just played with current in the PLL loop, shown on the >>>>>>> picture for clarity. >>>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in >>>>>>> the register of 0x16). >>>>>>> But, I think, for the RxPLL will be better use of the current 2.4 >>>>>>> mA, because the nearest noises more important for Rx (you should write 0x98 >>>>>>> in the register 0x26). >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> >>>>>>> >>>>>>> >>>>>> >>>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andrey.sviyazov at fairwaves.ru Thu Jul 19 14:56:40 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 18:56:40 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Sergey. I'll play around GPS power and RTC supply, thank you for your help. Thomas. About r0x16 please be sure that sometimes it isn't set to default value after power up (I saw it few times). Also I think that possible those bad "power on reset" gave us unstable result of LMS autocalibration. Best regards, Andrey Sviyazov. 2012/7/19 sergey kostanbaev > Which gives ~1.5khz cut-off, that's strange > > Also I'd check GPS VDD and AVDD nosies > > > On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov < > andrey.sviyazov at fairwaves.ru> wrote: > >> 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC input. >> Of course I'll increase capacitance or resistance to be sure about VC pin. >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/19 sergey kostanbaev >> >>> No :) But it may cause. >>> >>> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is >>> really sensible to any noise. >>> - caused by power supply of DAC. >>> - output noise of DAC. >>> - algorithm of changing values >>> >>> At first I'd inspect VC pin at VCTXCO and try to filter it with cut-off >>> frequency 1-0.1 Hz >>> >>> >>> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov < >>> andrey.sviyazov at fairwaves.ru> wrote: >>> >>>> Sergey. >>>> Is it really so frequently (32k/s updates at 1pps reference)? >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> >>>> >>>> 2012/7/19 sergey kostanbaev >>>> >>>>> >>>>> >>>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov < >>>>> andrey.sviyazov at fairwaves.ru> wrote: >>>>> >>>>>> Hi all. >>>>>> >>>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset >>>>>> when GPS antenna used and position locked. >>>>>> This spurs begin grow up when GPS just near to lock position and >>>>>> after locking spurs stopped to grow as you can see at picture. >>>>>> If thereafter GPS disconnected then noise coming back to normal plot. >>>>>> I think that it is result of 32768Hz clock in the GPS module EB-230, >>>>>> but can't understant how it can impact to 26MHz clock or VCO. >>>>>> >>>>> >>>>> As another idea it can be caused by continues GPS correction lead to >>>>> DAC changes to the VCTXCO. >>>>> >>>>> >>>>>> Please tell me something who know. >>>>>> >>>>>> Thomas. >>>>>> Was GPS antenna connected when noise measured like on the picture >>>>>> which you sent us (also attached here)? >>>>>> I would to know because of anomal peak near to 30kHz offset too. >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> >>>>>> >>>>>> >>>>>> 2012/7/19 Andrey Sviyazov >>>>>> >>>>>>> Sorry, that was meant to be sent to the mailing list :) >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> >>>>>>> ---------- Forwarded message ---------- >>>>>>> From: Andrey Sviyazov >>>>>>> Date: 2012/7/18 >>>>>>> Subject: LMS TxLO noise >>>>>>> >>>>>>> Hi Thomas. >>>>>>> >>>>>>> Here forwarded my last e-mail with noise plots when I stopped work >>>>>>> around it at first time, please see below. >>>>>>> >>>>>>> Please try to play around Tx PLL charge pump current (register 0x16) >>>>>>> for better RMS phase stability. >>>>>>> I think we should reach 1 degree or below. >>>>>>> >>>>>>> Alexander gave me the second UmTRX board and after checking and >>>>>>> fixing all known hardware issuesI've got roughly the same LO noise plot. >>>>>>> Possible Robin had no time to fixing all of our issues, so check >>>>>>> them all please. >>>>>>> And also check please what type of TCXO installed on your board. >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> >>>>>>> ---------- Forwarded message ---------- >>>>>>> From: Andrey Sviyazov >>>>>>> Date: 2012/4/13 >>>>>>> Subject: Re: LMS TxLO noise >>>>>>> >>>>>>> Hi all. >>>>>>> >>>>>>> There is progress with LMS PLL :) >>>>>>> Pictures are attached here. >>>>>>> t was discovered that 80 kHz spurs come from Ethernet, or rather >>>>>>> from the ET1011. >>>>>>> I unknowingly put the choke between transistor of 1V regulator and >>>>>>> analog power 1V. >>>>>>> As a result, the regulator has become unstable and oscillated 80 kHz >>>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>>>>>> To correct this problem L46 should be replaced by jumper on all alfa >>>>>>> version PCB's. >>>>>>> >>>>>>> Also I just played with current in the PLL loop, shown on the >>>>>>> picture for clarity. >>>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in >>>>>>> the register of 0x16). >>>>>>> But, I think, for the RxPLL will be better use of the current 2.4 >>>>>>> mA, because the nearest noises more important for Rx (you should write 0x98 >>>>>>> in the register 0x26). >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> >>>>>>> >>>>>>> >>>>>> >>>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From sergey.kostanbaev at gmail.com Thu Jul 19 14:23:48 2012 From: sergey.kostanbaev at gmail.com (sergey kostanbaev) Date: Thu, 19 Jul 2012 18:23:48 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov < andrey.sviyazov at fairwaves.ru> wrote: > Hi all. > > I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset when > GPS antenna used and position locked. > This spurs begin grow up when GPS just near to lock position and after > locking spurs stopped to grow as you can see at picture. > If thereafter GPS disconnected then noise coming back to normal plot. > I think that it is result of 32768Hz clock in the GPS module EB-230, but > can't understant how it can impact to 26MHz clock or VCO. > As another idea it can be caused by continues GPS correction lead to DAC changes to the VCTXCO. > Please tell me something who know. > > Thomas. > Was GPS antenna connected when noise measured like on the picture which > you sent us (also attached here)? > I would to know because of anomal peak near to 30kHz offset too. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 Andrey Sviyazov > >> Sorry, that was meant to be sent to the mailing list :) >> >> Best regards, >> Andrey Sviyazov. >> >> ---------- Forwarded message ---------- >> From: Andrey Sviyazov >> Date: 2012/7/18 >> Subject: LMS TxLO noise >> >> Hi Thomas. >> >> Here forwarded my last e-mail with noise plots when I stopped work around >> it at first time, please see below. >> >> Please try to play around Tx PLL charge pump current (register 0x16) for >> better RMS phase stability. >> I think we should reach 1 degree or below. >> >> Alexander gave me the second UmTRX board and after checking and fixing >> all known hardware issuesI've got roughly the same LO noise plot. >> Possible Robin had no time to fixing all of our issues, so check them all >> please. >> And also check please what type of TCXO installed on your board. >> >> Best regards, >> Andrey Sviyazov. >> >> ---------- Forwarded message ---------- >> From: Andrey Sviyazov >> Date: 2012/4/13 >> Subject: Re: LMS TxLO noise >> >> Hi all. >> >> There is progress with LMS PLL :) >> Pictures are attached here. >> t was discovered that 80 kHz spurs come from Ethernet, or rather from the >> ET1011. >> I unknowingly put the choke between transistor of 1V regulator and >> analog power 1V. >> As a result, the regulator has become unstable and oscillated 80 kHz with >> amplitude of 200 mV, which climbed into the LMS PLL. >> To correct this problem L46 should be replaced by jumper on all alfa >> version PCB's. >> >> Also I just played with current in the PLL loop, shown on the picture for >> clarity. >> Proved to be the optimal current 1,9 mA (you should write 0x93 in the >> register of 0x16). >> But, I think, for the RxPLL will be better use of the current 2.4 mA, >> because the nearest noises more important for Rx (you should write 0x98 in >> the register 0x26). >> >> Best regards, >> Andrey Sviyazov. >> >> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From sergey.kostanbaev at gmail.com Thu Jul 19 14:23:48 2012 From: sergey.kostanbaev at gmail.com (sergey kostanbaev) Date: Thu, 19 Jul 2012 18:23:48 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov < andrey.sviyazov at fairwaves.ru> wrote: > Hi all. > > I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset when > GPS antenna used and position locked. > This spurs begin grow up when GPS just near to lock position and after > locking spurs stopped to grow as you can see at picture. > If thereafter GPS disconnected then noise coming back to normal plot. > I think that it is result of 32768Hz clock in the GPS module EB-230, but > can't understant how it can impact to 26MHz clock or VCO. > As another idea it can be caused by continues GPS correction lead to DAC changes to the VCTXCO. > Please tell me something who know. > > Thomas. > Was GPS antenna connected when noise measured like on the picture which > you sent us (also attached here)? > I would to know because of anomal peak near to 30kHz offset too. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 Andrey Sviyazov > >> Sorry, that was meant to be sent to the mailing list :) >> >> Best regards, >> Andrey Sviyazov. >> >> ---------- Forwarded message ---------- >> From: Andrey Sviyazov >> Date: 2012/7/18 >> Subject: LMS TxLO noise >> >> Hi Thomas. >> >> Here forwarded my last e-mail with noise plots when I stopped work around >> it at first time, please see below. >> >> Please try to play around Tx PLL charge pump current (register 0x16) for >> better RMS phase stability. >> I think we should reach 1 degree or below. >> >> Alexander gave me the second UmTRX board and after checking and fixing >> all known hardware issuesI've got roughly the same LO noise plot. >> Possible Robin had no time to fixing all of our issues, so check them all >> please. >> And also check please what type of TCXO installed on your board. >> >> Best regards, >> Andrey Sviyazov. >> >> ---------- Forwarded message ---------- >> From: Andrey Sviyazov >> Date: 2012/4/13 >> Subject: Re: LMS TxLO noise >> >> Hi all. >> >> There is progress with LMS PLL :) >> Pictures are attached here. >> t was discovered that 80 kHz spurs come from Ethernet, or rather from the >> ET1011. >> I unknowingly put the choke between transistor of 1V regulator and >> analog power 1V. >> As a result, the regulator has become unstable and oscillated 80 kHz with >> amplitude of 200 mV, which climbed into the LMS PLL. >> To correct this problem L46 should be replaced by jumper on all alfa >> version PCB's. >> >> Also I just played with current in the PLL loop, shown on the picture for >> clarity. >> Proved to be the optimal current 1,9 mA (you should write 0x93 in the >> register of 0x16). >> But, I think, for the RxPLL will be better use of the current 2.4 mA, >> because the nearest noises more important for Rx (you should write 0x98 in >> the register 0x26). >> >> Best regards, >> Andrey Sviyazov. >> >> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From sergey.kostanbaev at gmail.com Thu Jul 19 14:35:15 2012 From: sergey.kostanbaev at gmail.com (sergey kostanbaev) Date: Thu, 19 Jul 2012 18:35:15 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: No :) But it may cause. I'd check all the line from FPGA to DAC to VCTXCO because VC pin is really sensible to any noise. - caused by power supply of DAC. - output noise of DAC. - algorithm of changing values At first I'd inspect VC pin at VCTXCO and try to filter it with cut-off frequency 1-0.1 Hz On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov < andrey.sviyazov at fairwaves.ru> wrote: > Sergey. > Is it really so frequently (32k/s updates at 1pps reference)? > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 sergey kostanbaev > >> >> >> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov < >> andrey.sviyazov at fairwaves.ru> wrote: >> >>> Hi all. >>> >>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset when >>> GPS antenna used and position locked. >>> This spurs begin grow up when GPS just near to lock position and after >>> locking spurs stopped to grow as you can see at picture. >>> If thereafter GPS disconnected then noise coming back to normal plot. >>> I think that it is result of 32768Hz clock in the GPS module EB-230, but >>> can't understant how it can impact to 26MHz clock or VCO. >>> >> >> As another idea it can be caused by continues GPS correction lead to DAC >> changes to the VCTXCO. >> >> >>> Please tell me something who know. >>> >>> Thomas. >>> Was GPS antenna connected when noise measured like on the picture which >>> you sent us (also attached here)? >>> I would to know because of anomal peak near to 30kHz offset too. >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/19 Andrey Sviyazov >>> >>>> Sorry, that was meant to be sent to the mailing list :) >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> ---------- Forwarded message ---------- >>>> From: Andrey Sviyazov >>>> Date: 2012/7/18 >>>> Subject: LMS TxLO noise >>>> >>>> Hi Thomas. >>>> >>>> Here forwarded my last e-mail with noise plots when I stopped work >>>> around it at first time, please see below. >>>> >>>> Please try to play around Tx PLL charge pump current (register 0x16) >>>> for better RMS phase stability. >>>> I think we should reach 1 degree or below. >>>> >>>> Alexander gave me the second UmTRX board and after checking and fixing >>>> all known hardware issuesI've got roughly the same LO noise plot. >>>> Possible Robin had no time to fixing all of our issues, so check them >>>> all please. >>>> And also check please what type of TCXO installed on your board. >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> ---------- Forwarded message ---------- >>>> From: Andrey Sviyazov >>>> Date: 2012/4/13 >>>> Subject: Re: LMS TxLO noise >>>> >>>> Hi all. >>>> >>>> There is progress with LMS PLL :) >>>> Pictures are attached here. >>>> t was discovered that 80 kHz spurs come from Ethernet, or rather from >>>> the ET1011. >>>> I unknowingly put the choke between transistor of 1V regulator and >>>> analog power 1V. >>>> As a result, the regulator has become unstable and oscillated 80 kHz >>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>>> To correct this problem L46 should be replaced by jumper on all alfa >>>> version PCB's. >>>> >>>> Also I just played with current in the PLL loop, shown on the picture >>>> for clarity. >>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in the >>>> register of 0x16). >>>> But, I think, for the RxPLL will be better use of the current 2.4 mA, >>>> because the nearest noises more important for Rx (you should write 0x98 in >>>> the register 0x26). >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From sergey.kostanbaev at gmail.com Thu Jul 19 14:35:15 2012 From: sergey.kostanbaev at gmail.com (sergey kostanbaev) Date: Thu, 19 Jul 2012 18:35:15 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: No :) But it may cause. I'd check all the line from FPGA to DAC to VCTXCO because VC pin is really sensible to any noise. - caused by power supply of DAC. - output noise of DAC. - algorithm of changing values At first I'd inspect VC pin at VCTXCO and try to filter it with cut-off frequency 1-0.1 Hz On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov < andrey.sviyazov at fairwaves.ru> wrote: > Sergey. > Is it really so frequently (32k/s updates at 1pps reference)? > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 sergey kostanbaev > >> >> >> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov < >> andrey.sviyazov at fairwaves.ru> wrote: >> >>> Hi all. >>> >>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset when >>> GPS antenna used and position locked. >>> This spurs begin grow up when GPS just near to lock position and after >>> locking spurs stopped to grow as you can see at picture. >>> If thereafter GPS disconnected then noise coming back to normal plot. >>> I think that it is result of 32768Hz clock in the GPS module EB-230, but >>> can't understant how it can impact to 26MHz clock or VCO. >>> >> >> As another idea it can be caused by continues GPS correction lead to DAC >> changes to the VCTXCO. >> >> >>> Please tell me something who know. >>> >>> Thomas. >>> Was GPS antenna connected when noise measured like on the picture which >>> you sent us (also attached here)? >>> I would to know because of anomal peak near to 30kHz offset too. >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/19 Andrey Sviyazov >>> >>>> Sorry, that was meant to be sent to the mailing list :) >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> ---------- Forwarded message ---------- >>>> From: Andrey Sviyazov >>>> Date: 2012/7/18 >>>> Subject: LMS TxLO noise >>>> >>>> Hi Thomas. >>>> >>>> Here forwarded my last e-mail with noise plots when I stopped work >>>> around it at first time, please see below. >>>> >>>> Please try to play around Tx PLL charge pump current (register 0x16) >>>> for better RMS phase stability. >>>> I think we should reach 1 degree or below. >>>> >>>> Alexander gave me the second UmTRX board and after checking and fixing >>>> all known hardware issuesI've got roughly the same LO noise plot. >>>> Possible Robin had no time to fixing all of our issues, so check them >>>> all please. >>>> And also check please what type of TCXO installed on your board. >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> ---------- Forwarded message ---------- >>>> From: Andrey Sviyazov >>>> Date: 2012/4/13 >>>> Subject: Re: LMS TxLO noise >>>> >>>> Hi all. >>>> >>>> There is progress with LMS PLL :) >>>> Pictures are attached here. >>>> t was discovered that 80 kHz spurs come from Ethernet, or rather from >>>> the ET1011. >>>> I unknowingly put the choke between transistor of 1V regulator and >>>> analog power 1V. >>>> As a result, the regulator has become unstable and oscillated 80 kHz >>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>>> To correct this problem L46 should be replaced by jumper on all alfa >>>> version PCB's. >>>> >>>> Also I just played with current in the PLL loop, shown on the picture >>>> for clarity. >>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in the >>>> register of 0x16). >>>> But, I think, for the RxPLL will be better use of the current 2.4 mA, >>>> because the nearest noises more important for Rx (you should write 0x98 in >>>> the register 0x26). >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From thomastsou at gmail.com Thu Jul 19 14:45:04 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Thu, 19 Jul 2012 10:45:04 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Andrey, On Thu, Jul 19, 2012 at 10:10 AM, Andrey Sviyazov wrote: > Hi all. > > I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset when GPS > antenna used and position locked. > This spurs begin grow up when GPS just near to lock position and after > locking spurs stopped to grow as you can see at picture. > If thereafter GPS disconnected then noise coming back to normal plot. > I think that it is result of 32768Hz clock in the GPS module EB-230, but > can't understant how it can impact to 26MHz clock or VCO. > Please tell me something who know. > > Thomas. > Was GPS antenna connected when noise measured like on the picture which you > sent us (also attached here)? > I would to know because of anomal peak near to 30kHz offset too. I have not connected a GPS antenna for any of the tests. I will run some measurements with register 0x16 later today. Thomas From thomastsou at gmail.com Thu Jul 19 14:45:04 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Thu, 19 Jul 2012 10:45:04 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Andrey, On Thu, Jul 19, 2012 at 10:10 AM, Andrey Sviyazov wrote: > Hi all. > > I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset when GPS > antenna used and position locked. > This spurs begin grow up when GPS just near to lock position and after > locking spurs stopped to grow as you can see at picture. > If thereafter GPS disconnected then noise coming back to normal plot. > I think that it is result of 32768Hz clock in the GPS module EB-230, but > can't understant how it can impact to 26MHz clock or VCO. > Please tell me something who know. > > Thomas. > Was GPS antenna connected when noise measured like on the picture which you > sent us (also attached here)? > I would to know because of anomal peak near to 30kHz offset too. I have not connected a GPS antenna for any of the tests. I will run some measurements with register 0x16 later today. Thomas From sergey.kostanbaev at gmail.com Thu Jul 19 14:49:33 2012 From: sergey.kostanbaev at gmail.com (sergey kostanbaev) Date: Thu, 19 Jul 2012 18:49:33 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Which gives ~1.5khz cut-off, that's strange Also I'd check GPS VDD and AVDD nosies On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov < andrey.sviyazov at fairwaves.ru> wrote: > 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC input. > Of course I'll increase capacitance or resistance to be sure about VC pin. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 sergey kostanbaev > >> No :) But it may cause. >> >> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is >> really sensible to any noise. >> - caused by power supply of DAC. >> - output noise of DAC. >> - algorithm of changing values >> >> At first I'd inspect VC pin at VCTXCO and try to filter it with cut-off >> frequency 1-0.1 Hz >> >> >> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov < >> andrey.sviyazov at fairwaves.ru> wrote: >> >>> Sergey. >>> Is it really so frequently (32k/s updates at 1pps reference)? >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/19 sergey kostanbaev >>> >>>> >>>> >>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov < >>>> andrey.sviyazov at fairwaves.ru> wrote: >>>> >>>>> Hi all. >>>>> >>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset >>>>> when GPS antenna used and position locked. >>>>> This spurs begin grow up when GPS just near to lock position and after >>>>> locking spurs stopped to grow as you can see at picture. >>>>> If thereafter GPS disconnected then noise coming back to normal plot. >>>>> I think that it is result of 32768Hz clock in the GPS module EB-230, >>>>> but can't understant how it can impact to 26MHz clock or VCO. >>>>> >>>> >>>> As another idea it can be caused by continues GPS correction lead to >>>> DAC changes to the VCTXCO. >>>> >>>> >>>>> Please tell me something who know. >>>>> >>>>> Thomas. >>>>> Was GPS antenna connected when noise measured like on the picture >>>>> which you sent us (also attached here)? >>>>> I would to know because of anomal peak near to 30kHz offset too. >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> >>>>> >>>>> 2012/7/19 Andrey Sviyazov >>>>> >>>>>> Sorry, that was meant to be sent to the mailing list :) >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> >>>>>> ---------- Forwarded message ---------- >>>>>> From: Andrey Sviyazov >>>>>> Date: 2012/7/18 >>>>>> Subject: LMS TxLO noise >>>>>> >>>>>> Hi Thomas. >>>>>> >>>>>> Here forwarded my last e-mail with noise plots when I stopped work >>>>>> around it at first time, please see below. >>>>>> >>>>>> Please try to play around Tx PLL charge pump current (register 0x16) >>>>>> for better RMS phase stability. >>>>>> I think we should reach 1 degree or below. >>>>>> >>>>>> Alexander gave me the second UmTRX board and after checking and >>>>>> fixing all known hardware issuesI've got roughly the same LO noise plot. >>>>>> Possible Robin had no time to fixing all of our issues, so check them >>>>>> all please. >>>>>> And also check please what type of TCXO installed on your board. >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> >>>>>> ---------- Forwarded message ---------- >>>>>> From: Andrey Sviyazov >>>>>> Date: 2012/4/13 >>>>>> Subject: Re: LMS TxLO noise >>>>>> >>>>>> Hi all. >>>>>> >>>>>> There is progress with LMS PLL :) >>>>>> Pictures are attached here. >>>>>> t was discovered that 80 kHz spurs come from Ethernet, or rather from >>>>>> the ET1011. >>>>>> I unknowingly put the choke between transistor of 1V regulator and >>>>>> analog power 1V. >>>>>> As a result, the regulator has become unstable and oscillated 80 kHz >>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>>>>> To correct this problem L46 should be replaced by jumper on all alfa >>>>>> version PCB's. >>>>>> >>>>>> Also I just played with current in the PLL loop, shown on the picture >>>>>> for clarity. >>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in the >>>>>> register of 0x16). >>>>>> But, I think, for the RxPLL will be better use of the current 2.4 mA, >>>>>> because the nearest noises more important for Rx (you should write 0x98 in >>>>>> the register 0x26). >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> >>>>>> >>>>>> >>>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From sergey.kostanbaev at gmail.com Thu Jul 19 14:49:33 2012 From: sergey.kostanbaev at gmail.com (sergey kostanbaev) Date: Thu, 19 Jul 2012 18:49:33 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Which gives ~1.5khz cut-off, that's strange Also I'd check GPS VDD and AVDD nosies On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov < andrey.sviyazov at fairwaves.ru> wrote: > 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC input. > Of course I'll increase capacitance or resistance to be sure about VC pin. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 sergey kostanbaev > >> No :) But it may cause. >> >> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is >> really sensible to any noise. >> - caused by power supply of DAC. >> - output noise of DAC. >> - algorithm of changing values >> >> At first I'd inspect VC pin at VCTXCO and try to filter it with cut-off >> frequency 1-0.1 Hz >> >> >> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov < >> andrey.sviyazov at fairwaves.ru> wrote: >> >>> Sergey. >>> Is it really so frequently (32k/s updates at 1pps reference)? >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/19 sergey kostanbaev >>> >>>> >>>> >>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov < >>>> andrey.sviyazov at fairwaves.ru> wrote: >>>> >>>>> Hi all. >>>>> >>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset >>>>> when GPS antenna used and position locked. >>>>> This spurs begin grow up when GPS just near to lock position and after >>>>> locking spurs stopped to grow as you can see at picture. >>>>> If thereafter GPS disconnected then noise coming back to normal plot. >>>>> I think that it is result of 32768Hz clock in the GPS module EB-230, >>>>> but can't understant how it can impact to 26MHz clock or VCO. >>>>> >>>> >>>> As another idea it can be caused by continues GPS correction lead to >>>> DAC changes to the VCTXCO. >>>> >>>> >>>>> Please tell me something who know. >>>>> >>>>> Thomas. >>>>> Was GPS antenna connected when noise measured like on the picture >>>>> which you sent us (also attached here)? >>>>> I would to know because of anomal peak near to 30kHz offset too. >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> >>>>> >>>>> 2012/7/19 Andrey Sviyazov >>>>> >>>>>> Sorry, that was meant to be sent to the mailing list :) >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> >>>>>> ---------- Forwarded message ---------- >>>>>> From: Andrey Sviyazov >>>>>> Date: 2012/7/18 >>>>>> Subject: LMS TxLO noise >>>>>> >>>>>> Hi Thomas. >>>>>> >>>>>> Here forwarded my last e-mail with noise plots when I stopped work >>>>>> around it at first time, please see below. >>>>>> >>>>>> Please try to play around Tx PLL charge pump current (register 0x16) >>>>>> for better RMS phase stability. >>>>>> I think we should reach 1 degree or below. >>>>>> >>>>>> Alexander gave me the second UmTRX board and after checking and >>>>>> fixing all known hardware issuesI've got roughly the same LO noise plot. >>>>>> Possible Robin had no time to fixing all of our issues, so check them >>>>>> all please. >>>>>> And also check please what type of TCXO installed on your board. >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> >>>>>> ---------- Forwarded message ---------- >>>>>> From: Andrey Sviyazov >>>>>> Date: 2012/4/13 >>>>>> Subject: Re: LMS TxLO noise >>>>>> >>>>>> Hi all. >>>>>> >>>>>> There is progress with LMS PLL :) >>>>>> Pictures are attached here. >>>>>> t was discovered that 80 kHz spurs come from Ethernet, or rather from >>>>>> the ET1011. >>>>>> I unknowingly put the choke between transistor of 1V regulator and >>>>>> analog power 1V. >>>>>> As a result, the regulator has become unstable and oscillated 80 kHz >>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>>>>> To correct this problem L46 should be replaced by jumper on all alfa >>>>>> version PCB's. >>>>>> >>>>>> Also I just played with current in the PLL loop, shown on the picture >>>>>> for clarity. >>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in the >>>>>> register of 0x16). >>>>>> But, I think, for the RxPLL will be better use of the current 2.4 mA, >>>>>> because the nearest noises more important for Rx (you should write 0x98 in >>>>>> the register 0x26). >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> >>>>>> >>>>>> >>>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Thu Jul 19 15:05:44 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Thu, 19 Jul 2012 19:05:44 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Guys, please keep track of all LMS configuration values which are not set to default during power on and we'll add them to our manual initialization script. On Thu, Jul 19, 2012 at 6:56 PM, Andrey Sviyazov wrote: > Sergey. > I'll play around GPS power and RTC supply, thank you for your help. > > Thomas. > About r0x16 please be sure that sometimes it isn't set to default value > after power up (I saw it few times). > Also I think that possible those bad "power on reset" gave us unstable > result of LMS autocalibration. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 sergey kostanbaev >> >> Which gives ~1.5khz cut-off, that's strange >> >> Also I'd check GPS VDD and AVDD nosies >> >> >> On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov >> wrote: >>> >>> 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC >>> input. >>> Of course I'll increase capacitance or resistance to be sure about VC >>> pin. >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/19 sergey kostanbaev >>>> >>>> No :) But it may cause. >>>> >>>> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is >>>> really sensible to any noise. >>>> - caused by power supply of DAC. >>>> - output noise of DAC. >>>> - algorithm of changing values >>>> >>>> At first I'd inspect VC pin at VCTXCO and try to filter it with cut-off >>>> frequency 1-0.1 Hz >>>> >>>> >>>> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov >>>> wrote: >>>>> >>>>> Sergey. >>>>> Is it really so frequently (32k/s updates at 1pps reference)? >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> >>>>> >>>>> 2012/7/19 sergey kostanbaev >>>>>> >>>>>> >>>>>> >>>>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov >>>>>> wrote: >>>>>>> >>>>>>> Hi all. >>>>>>> >>>>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset >>>>>>> when GPS antenna used and position locked. >>>>>>> This spurs begin grow up when GPS just near to lock position and >>>>>>> after locking spurs stopped to grow as you can see at picture. >>>>>>> If thereafter GPS disconnected then noise coming back to normal plot. >>>>>>> I think that it is result of 32768Hz clock in the GPS module EB-230, >>>>>>> but can't understant how it can impact to 26MHz clock or VCO. >>>>>> >>>>>> >>>>>> As another idea it can be caused by continues GPS correction lead to >>>>>> DAC changes to the VCTXCO. >>>>>> >>>>>>> >>>>>>> Please tell me something who know. >>>>>>> >>>>>>> Thomas. >>>>>>> Was GPS antenna connected when noise measured like on the picture >>>>>>> which you sent us (also attached here)? >>>>>>> I would to know because of anomal peak near to 30kHz offset too. >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> >>>>>>> >>>>>>> >>>>>>> 2012/7/19 Andrey Sviyazov >>>>>>>> >>>>>>>> Sorry, that was meant to be sent to the mailing list :) >>>>>>>> >>>>>>>> Best regards, >>>>>>>> Andrey Sviyazov. >>>>>>>> >>>>>>>> ---------- Forwarded message ---------- >>>>>>>> From: Andrey Sviyazov >>>>>>>> Date: 2012/7/18 >>>>>>>> Subject: LMS TxLO noise >>>>>>>> >>>>>>>> Hi Thomas. >>>>>>>> >>>>>>>> Here forwarded my last e-mail with noise plots when I stopped work >>>>>>>> around it at first time, please see below. >>>>>>>> >>>>>>>> Please try to play around Tx PLL charge pump current (register 0x16) >>>>>>>> for better RMS phase stability. >>>>>>>> I think we should reach 1 degree or below. >>>>>>>> >>>>>>>> Alexander gave me the second UmTRX board and after checking and >>>>>>>> fixing all known hardware issues I've got roughly the same LO noise plot. >>>>>>>> Possible Robin had no time to fixing all of our issues, so check >>>>>>>> them all please. >>>>>>>> And also check please what type of TCXO installed on your board. >>>>>>>> >>>>>>>> Best regards, >>>>>>>> Andrey Sviyazov. >>>>>>>> >>>>>>>> ---------- Forwarded message ---------- >>>>>>>> From: Andrey Sviyazov >>>>>>>> Date: 2012/4/13 >>>>>>>> Subject: Re: LMS TxLO noise >>>>>>>> >>>>>>>> Hi all. >>>>>>>> >>>>>>>> There is progress with LMS PLL :) >>>>>>>> Pictures are attached here. >>>>>>>> t was discovered that 80 kHz spurs come from Ethernet, or rather >>>>>>>> from the ET1011. >>>>>>>> I unknowingly put the choke between transistor of 1V regulator and >>>>>>>> analog power 1V. >>>>>>>> As a result, the regulator has become unstable and oscillated 80 kHz >>>>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>>>>>>> To correct this problem L46 should be replaced by jumper on all alfa >>>>>>>> version PCB's. >>>>>>>> >>>>>>>> Also I just played with current in the PLL loop, shown on the >>>>>>>> picture for clarity. >>>>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in >>>>>>>> the register of 0x16). >>>>>>>> But, I think, for the RxPLL will be better use of the current 2.4 >>>>>>>> mA, because the nearest noises more important for Rx (you should write 0x98 >>>>>>>> in the register 0x26). >>>>>>>> >>>>>>>> Best regards, >>>>>>>> Andrey Sviyazov. >>>>>>>> >>>>>>>> >>>>>>> >>>>>> >>>>> >>>> >>> >> > -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Thu Jul 19 15:05:44 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Thu, 19 Jul 2012 19:05:44 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Guys, please keep track of all LMS configuration values which are not set to default during power on and we'll add them to our manual initialization script. On Thu, Jul 19, 2012 at 6:56 PM, Andrey Sviyazov wrote: > Sergey. > I'll play around GPS power and RTC supply, thank you for your help. > > Thomas. > About r0x16 please be sure that sometimes it isn't set to default value > after power up (I saw it few times). > Also I think that possible those bad "power on reset" gave us unstable > result of LMS autocalibration. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 sergey kostanbaev >> >> Which gives ~1.5khz cut-off, that's strange >> >> Also I'd check GPS VDD and AVDD nosies >> >> >> On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov >> wrote: >>> >>> 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC >>> input. >>> Of course I'll increase capacitance or resistance to be sure about VC >>> pin. >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/19 sergey kostanbaev >>>> >>>> No :) But it may cause. >>>> >>>> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is >>>> really sensible to any noise. >>>> - caused by power supply of DAC. >>>> - output noise of DAC. >>>> - algorithm of changing values >>>> >>>> At first I'd inspect VC pin at VCTXCO and try to filter it with cut-off >>>> frequency 1-0.1 Hz >>>> >>>> >>>> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov >>>> wrote: >>>>> >>>>> Sergey. >>>>> Is it really so frequently (32k/s updates at 1pps reference)? >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> >>>>> >>>>> 2012/7/19 sergey kostanbaev >>>>>> >>>>>> >>>>>> >>>>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov >>>>>> wrote: >>>>>>> >>>>>>> Hi all. >>>>>>> >>>>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset >>>>>>> when GPS antenna used and position locked. >>>>>>> This spurs begin grow up when GPS just near to lock position and >>>>>>> after locking spurs stopped to grow as you can see at picture. >>>>>>> If thereafter GPS disconnected then noise coming back to normal plot. >>>>>>> I think that it is result of 32768Hz clock in the GPS module EB-230, >>>>>>> but can't understant how it can impact to 26MHz clock or VCO. >>>>>> >>>>>> >>>>>> As another idea it can be caused by continues GPS correction lead to >>>>>> DAC changes to the VCTXCO. >>>>>> >>>>>>> >>>>>>> Please tell me something who know. >>>>>>> >>>>>>> Thomas. >>>>>>> Was GPS antenna connected when noise measured like on the picture >>>>>>> which you sent us (also attached here)? >>>>>>> I would to know because of anomal peak near to 30kHz offset too. >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> >>>>>>> >>>>>>> >>>>>>> 2012/7/19 Andrey Sviyazov >>>>>>>> >>>>>>>> Sorry, that was meant to be sent to the mailing list :) >>>>>>>> >>>>>>>> Best regards, >>>>>>>> Andrey Sviyazov. >>>>>>>> >>>>>>>> ---------- Forwarded message ---------- >>>>>>>> From: Andrey Sviyazov >>>>>>>> Date: 2012/7/18 >>>>>>>> Subject: LMS TxLO noise >>>>>>>> >>>>>>>> Hi Thomas. >>>>>>>> >>>>>>>> Here forwarded my last e-mail with noise plots when I stopped work >>>>>>>> around it at first time, please see below. >>>>>>>> >>>>>>>> Please try to play around Tx PLL charge pump current (register 0x16) >>>>>>>> for better RMS phase stability. >>>>>>>> I think we should reach 1 degree or below. >>>>>>>> >>>>>>>> Alexander gave me the second UmTRX board and after checking and >>>>>>>> fixing all known hardware issues I've got roughly the same LO noise plot. >>>>>>>> Possible Robin had no time to fixing all of our issues, so check >>>>>>>> them all please. >>>>>>>> And also check please what type of TCXO installed on your board. >>>>>>>> >>>>>>>> Best regards, >>>>>>>> Andrey Sviyazov. >>>>>>>> >>>>>>>> ---------- Forwarded message ---------- >>>>>>>> From: Andrey Sviyazov >>>>>>>> Date: 2012/4/13 >>>>>>>> Subject: Re: LMS TxLO noise >>>>>>>> >>>>>>>> Hi all. >>>>>>>> >>>>>>>> There is progress with LMS PLL :) >>>>>>>> Pictures are attached here. >>>>>>>> t was discovered that 80 kHz spurs come from Ethernet, or rather >>>>>>>> from the ET1011. >>>>>>>> I unknowingly put the choke between transistor of 1V regulator and >>>>>>>> analog power 1V. >>>>>>>> As a result, the regulator has become unstable and oscillated 80 kHz >>>>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>>>>>>> To correct this problem L46 should be replaced by jumper on all alfa >>>>>>>> version PCB's. >>>>>>>> >>>>>>>> Also I just played with current in the PLL loop, shown on the >>>>>>>> picture for clarity. >>>>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in >>>>>>>> the register of 0x16). >>>>>>>> But, I think, for the RxPLL will be better use of the current 2.4 >>>>>>>> mA, because the nearest noises more important for Rx (you should write 0x98 >>>>>>>> in the register 0x26). >>>>>>>> >>>>>>>> Best regards, >>>>>>>> Andrey Sviyazov. >>>>>>>> >>>>>>>> >>>>>>> >>>>>> >>>>> >>>> >>> >> > -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From andrey.sviyazov at fairwaves.ru Thu Jul 19 15:33:00 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 19:33:00 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Alexander. I think that few pulses of LMS hardware reset (LMS_NRST-1 and LMS_NRST-2 pins) will be much easily than all registers checking. BTW, are there reset pulses after power up or not? Best regards, Andrey Sviyazov. 2012/7/19 Alexander Chemeris > Guys, please keep track of all LMS configuration values which are not > set to default during power on and we'll add them to our manual > initialization script. > > On Thu, Jul 19, 2012 at 6:56 PM, Andrey Sviyazov > wrote: > > Sergey. > > I'll play around GPS power and RTC supply, thank you for your help. > > > > Thomas. > > About r0x16 please be sure that sometimes it isn't set to default value > > after power up (I saw it few times). > > Also I think that possible those bad "power on reset" gave us unstable > > result of LMS autocalibration. > > > > Best regards, > > Andrey Sviyazov. > > > > > > > > 2012/7/19 sergey kostanbaev > >> > >> Which gives ~1.5khz cut-off, that's strange > >> > >> Also I'd check GPS VDD and AVDD nosies > >> > >> > >> On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov > >> wrote: > >>> > >>> 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC > >>> input. > >>> Of course I'll increase capacitance or resistance to be sure about VC > >>> pin. > >>> > >>> Best regards, > >>> Andrey Sviyazov. > >>> > >>> > >>> > >>> 2012/7/19 sergey kostanbaev > >>>> > >>>> No :) But it may cause. > >>>> > >>>> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is > >>>> really sensible to any noise. > >>>> - caused by power supply of DAC. > >>>> - output noise of DAC. > >>>> - algorithm of changing values > >>>> > >>>> At first I'd inspect VC pin at VCTXCO and try to filter it with > cut-off > >>>> frequency 1-0.1 Hz > >>>> > >>>> > >>>> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov > >>>> wrote: > >>>>> > >>>>> Sergey. > >>>>> Is it really so frequently (32k/s updates at 1pps reference)? > >>>>> > >>>>> Best regards, > >>>>> Andrey Sviyazov. > >>>>> > >>>>> > >>>>> > >>>>> 2012/7/19 sergey kostanbaev > >>>>>> > >>>>>> > >>>>>> > >>>>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov > >>>>>> wrote: > >>>>>>> > >>>>>>> Hi all. > >>>>>>> > >>>>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset > >>>>>>> when GPS antenna used and position locked. > >>>>>>> This spurs begin grow up when GPS just near to lock position and > >>>>>>> after locking spurs stopped to grow as you can see at picture. > >>>>>>> If thereafter GPS disconnected then noise coming back to normal > plot. > >>>>>>> I think that it is result of 32768Hz clock in the GPS module > EB-230, > >>>>>>> but can't understant how it can impact to 26MHz clock or VCO. > >>>>>> > >>>>>> > >>>>>> As another idea it can be caused by continues GPS correction lead to > >>>>>> DAC changes to the VCTXCO. > >>>>>> > >>>>>>> > >>>>>>> Please tell me something who know. > >>>>>>> > >>>>>>> Thomas. > >>>>>>> Was GPS antenna connected when noise measured like on the picture > >>>>>>> which you sent us (also attached here)? > >>>>>>> I would to know because of anomal peak near to 30kHz offset too. > >>>>>>> > >>>>>>> Best regards, > >>>>>>> Andrey Sviyazov. > >>>>>>> > >>>>>>> > >>>>>>> > >>>>>>> 2012/7/19 Andrey Sviyazov > >>>>>>>> > >>>>>>>> Sorry, that was meant to be sent to the mailing list :) > >>>>>>>> > >>>>>>>> Best regards, > >>>>>>>> Andrey Sviyazov. > >>>>>>>> > >>>>>>>> ---------- Forwarded message ---------- > >>>>>>>> From: Andrey Sviyazov > >>>>>>>> Date: 2012/7/18 > >>>>>>>> Subject: LMS TxLO noise > >>>>>>>> > >>>>>>>> Hi Thomas. > >>>>>>>> > >>>>>>>> Here forwarded my last e-mail with noise plots when I stopped work > >>>>>>>> around it at first time, please see below. > >>>>>>>> > >>>>>>>> Please try to play around Tx PLL charge pump current (register > 0x16) > >>>>>>>> for better RMS phase stability. > >>>>>>>> I think we should reach 1 degree or below. > >>>>>>>> > >>>>>>>> Alexander gave me the second UmTRX board and after checking and > >>>>>>>> fixing all known hardware issues I've got roughly the same LO > noise plot. > >>>>>>>> Possible Robin had no time to fixing all of our issues, so check > >>>>>>>> them all please. > >>>>>>>> And also check please what type of TCXO installed on your board. > >>>>>>>> > >>>>>>>> Best regards, > >>>>>>>> Andrey Sviyazov. > >>>>>>>> > >>>>>>>> ---------- Forwarded message ---------- > >>>>>>>> From: Andrey Sviyazov > >>>>>>>> Date: 2012/4/13 > >>>>>>>> Subject: Re: LMS TxLO noise > >>>>>>>> > >>>>>>>> Hi all. > >>>>>>>> > >>>>>>>> There is progress with LMS PLL :) > >>>>>>>> Pictures are attached here. > >>>>>>>> t was discovered that 80 kHz spurs come from Ethernet, or rather > >>>>>>>> from the ET1011. > >>>>>>>> I unknowingly put the choke between transistor of 1V regulator and > >>>>>>>> analog power 1V. > >>>>>>>> As a result, the regulator has become unstable and oscillated 80 > kHz > >>>>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. > >>>>>>>> To correct this problem L46 should be replaced by jumper on all > alfa > >>>>>>>> version PCB's. > >>>>>>>> > >>>>>>>> Also I just played with current in the PLL loop, shown on the > >>>>>>>> picture for clarity. > >>>>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in > >>>>>>>> the register of 0x16). > >>>>>>>> But, I think, for the RxPLL will be better use of the current 2.4 > >>>>>>>> mA, because the nearest noises more important for Rx (you should > write 0x98 > >>>>>>>> in the register 0x26). > >>>>>>>> > >>>>>>>> Best regards, > >>>>>>>> Andrey Sviyazov. > >>>>>>>> > >>>>>>>> > >>>>>>> > >>>>>> > >>>>> > >>>> > >>> > >> > > > > > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andrey.sviyazov at fairwaves.ru Thu Jul 19 15:33:00 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 19:33:00 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Alexander. I think that few pulses of LMS hardware reset (LMS_NRST-1 and LMS_NRST-2 pins) will be much easily than all registers checking. BTW, are there reset pulses after power up or not? Best regards, Andrey Sviyazov. 2012/7/19 Alexander Chemeris > Guys, please keep track of all LMS configuration values which are not > set to default during power on and we'll add them to our manual > initialization script. > > On Thu, Jul 19, 2012 at 6:56 PM, Andrey Sviyazov > wrote: > > Sergey. > > I'll play around GPS power and RTC supply, thank you for your help. > > > > Thomas. > > About r0x16 please be sure that sometimes it isn't set to default value > > after power up (I saw it few times). > > Also I think that possible those bad "power on reset" gave us unstable > > result of LMS autocalibration. > > > > Best regards, > > Andrey Sviyazov. > > > > > > > > 2012/7/19 sergey kostanbaev > >> > >> Which gives ~1.5khz cut-off, that's strange > >> > >> Also I'd check GPS VDD and AVDD nosies > >> > >> > >> On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov > >> wrote: > >>> > >>> 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC > >>> input. > >>> Of course I'll increase capacitance or resistance to be sure about VC > >>> pin. > >>> > >>> Best regards, > >>> Andrey Sviyazov. > >>> > >>> > >>> > >>> 2012/7/19 sergey kostanbaev > >>>> > >>>> No :) But it may cause. > >>>> > >>>> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is > >>>> really sensible to any noise. > >>>> - caused by power supply of DAC. > >>>> - output noise of DAC. > >>>> - algorithm of changing values > >>>> > >>>> At first I'd inspect VC pin at VCTXCO and try to filter it with > cut-off > >>>> frequency 1-0.1 Hz > >>>> > >>>> > >>>> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov > >>>> wrote: > >>>>> > >>>>> Sergey. > >>>>> Is it really so frequently (32k/s updates at 1pps reference)? > >>>>> > >>>>> Best regards, > >>>>> Andrey Sviyazov. > >>>>> > >>>>> > >>>>> > >>>>> 2012/7/19 sergey kostanbaev > >>>>>> > >>>>>> > >>>>>> > >>>>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov > >>>>>> wrote: > >>>>>>> > >>>>>>> Hi all. > >>>>>>> > >>>>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset > >>>>>>> when GPS antenna used and position locked. > >>>>>>> This spurs begin grow up when GPS just near to lock position and > >>>>>>> after locking spurs stopped to grow as you can see at picture. > >>>>>>> If thereafter GPS disconnected then noise coming back to normal > plot. > >>>>>>> I think that it is result of 32768Hz clock in the GPS module > EB-230, > >>>>>>> but can't understant how it can impact to 26MHz clock or VCO. > >>>>>> > >>>>>> > >>>>>> As another idea it can be caused by continues GPS correction lead to > >>>>>> DAC changes to the VCTXCO. > >>>>>> > >>>>>>> > >>>>>>> Please tell me something who know. > >>>>>>> > >>>>>>> Thomas. > >>>>>>> Was GPS antenna connected when noise measured like on the picture > >>>>>>> which you sent us (also attached here)? > >>>>>>> I would to know because of anomal peak near to 30kHz offset too. > >>>>>>> > >>>>>>> Best regards, > >>>>>>> Andrey Sviyazov. > >>>>>>> > >>>>>>> > >>>>>>> > >>>>>>> 2012/7/19 Andrey Sviyazov > >>>>>>>> > >>>>>>>> Sorry, that was meant to be sent to the mailing list :) > >>>>>>>> > >>>>>>>> Best regards, > >>>>>>>> Andrey Sviyazov. > >>>>>>>> > >>>>>>>> ---------- Forwarded message ---------- > >>>>>>>> From: Andrey Sviyazov > >>>>>>>> Date: 2012/7/18 > >>>>>>>> Subject: LMS TxLO noise > >>>>>>>> > >>>>>>>> Hi Thomas. > >>>>>>>> > >>>>>>>> Here forwarded my last e-mail with noise plots when I stopped work > >>>>>>>> around it at first time, please see below. > >>>>>>>> > >>>>>>>> Please try to play around Tx PLL charge pump current (register > 0x16) > >>>>>>>> for better RMS phase stability. > >>>>>>>> I think we should reach 1 degree or below. > >>>>>>>> > >>>>>>>> Alexander gave me the second UmTRX board and after checking and > >>>>>>>> fixing all known hardware issues I've got roughly the same LO > noise plot. > >>>>>>>> Possible Robin had no time to fixing all of our issues, so check > >>>>>>>> them all please. > >>>>>>>> And also check please what type of TCXO installed on your board. > >>>>>>>> > >>>>>>>> Best regards, > >>>>>>>> Andrey Sviyazov. > >>>>>>>> > >>>>>>>> ---------- Forwarded message ---------- > >>>>>>>> From: Andrey Sviyazov > >>>>>>>> Date: 2012/4/13 > >>>>>>>> Subject: Re: LMS TxLO noise > >>>>>>>> > >>>>>>>> Hi all. > >>>>>>>> > >>>>>>>> There is progress with LMS PLL :) > >>>>>>>> Pictures are attached here. > >>>>>>>> t was discovered that 80 kHz spurs come from Ethernet, or rather > >>>>>>>> from the ET1011. > >>>>>>>> I unknowingly put the choke between transistor of 1V regulator and > >>>>>>>> analog power 1V. > >>>>>>>> As a result, the regulator has become unstable and oscillated 80 > kHz > >>>>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. > >>>>>>>> To correct this problem L46 should be replaced by jumper on all > alfa > >>>>>>>> version PCB's. > >>>>>>>> > >>>>>>>> Also I just played with current in the PLL loop, shown on the > >>>>>>>> picture for clarity. > >>>>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in > >>>>>>>> the register of 0x16). > >>>>>>>> But, I think, for the RxPLL will be better use of the current 2.4 > >>>>>>>> mA, because the nearest noises more important for Rx (you should > write 0x98 > >>>>>>>> in the register 0x26). > >>>>>>>> > >>>>>>>> Best regards, > >>>>>>>> Andrey Sviyazov. > >>>>>>>> > >>>>>>>> > >>>>>>> > >>>>>> > >>>>> > >>>> > >>> > >> > > > > > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? 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URL: From andrey.sviyazov at fairwaves.ru Thu Jul 19 16:06:08 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 20:06:08 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Thomas. I've calculate few PIF filters for PLL by the ADIsimPLL and found that RMS phase jitter in case of 5kHz and 50kHz only 0.33 and 0.46 degrees. It is very small difference, so are you sure that I should implement 10kHz bandwidth filter as in USRP? Actually it is absolutly not an problem for me to implement it, but I have to be sure. I've calculated it for 10kHz bandwidth, noise plot will be around 75-80dBc/Hz @ 10kHz and 105-110 dBc/Hz @ 100kHz offset. Best regards, Andrey Sviyazov. 2012/7/19 Andrey Sviyazov > Alexander. > I think that few pulses of LMS hardware reset (LMS_NRST-1 and LMS_NRST-2 > pins) will be much easily than all registers checking. > BTW, are there reset pulses after power up or not? > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 Alexander Chemeris > >> Guys, please keep track of all LMS configuration values which are not >> set to default during power on and we'll add them to our manual >> initialization script. >> >> On Thu, Jul 19, 2012 at 6:56 PM, Andrey Sviyazov >> wrote: >> > Sergey. >> > I'll play around GPS power and RTC supply, thank you for your help. >> > >> > Thomas. >> > About r0x16 please be sure that sometimes it isn't set to default value >> > after power up (I saw it few times). >> > Also I think that possible those bad "power on reset" gave us unstable >> > result of LMS autocalibration. >> > >> > Best regards, >> > Andrey Sviyazov. >> > >> > >> > >> > 2012/7/19 sergey kostanbaev >> >> >> >> Which gives ~1.5khz cut-off, that's strange >> >> >> >> Also I'd check GPS VDD and AVDD nosies >> >> >> >> >> >> On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov >> >> wrote: >> >>> >> >>> 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC >> >>> input. >> >>> Of course I'll increase capacitance or resistance to be sure about VC >> >>> pin. >> >>> >> >>> Best regards, >> >>> Andrey Sviyazov. >> >>> >> >>> >> >>> >> >>> 2012/7/19 sergey kostanbaev >> >>>> >> >>>> No :) But it may cause. >> >>>> >> >>>> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is >> >>>> really sensible to any noise. >> >>>> - caused by power supply of DAC. >> >>>> - output noise of DAC. >> >>>> - algorithm of changing values >> >>>> >> >>>> At first I'd inspect VC pin at VCTXCO and try to filter it with >> cut-off >> >>>> frequency 1-0.1 Hz >> >>>> >> >>>> >> >>>> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov >> >>>> wrote: >> >>>>> >> >>>>> Sergey. >> >>>>> Is it really so frequently (32k/s updates at 1pps reference)? >> >>>>> >> >>>>> Best regards, >> >>>>> Andrey Sviyazov. >> >>>>> >> >>>>> >> >>>>> >> >>>>> 2012/7/19 sergey kostanbaev >> >>>>>> >> >>>>>> >> >>>>>> >> >>>>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov >> >>>>>> wrote: >> >>>>>>> >> >>>>>>> Hi all. >> >>>>>>> >> >>>>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset >> >>>>>>> when GPS antenna used and position locked. >> >>>>>>> This spurs begin grow up when GPS just near to lock position and >> >>>>>>> after locking spurs stopped to grow as you can see at picture. >> >>>>>>> If thereafter GPS disconnected then noise coming back to normal >> plot. >> >>>>>>> I think that it is result of 32768Hz clock in the GPS module >> EB-230, >> >>>>>>> but can't understant how it can impact to 26MHz clock or VCO. >> >>>>>> >> >>>>>> >> >>>>>> As another idea it can be caused by continues GPS correction lead >> to >> >>>>>> DAC changes to the VCTXCO. >> >>>>>> >> >>>>>>> >> >>>>>>> Please tell me something who know. >> >>>>>>> >> >>>>>>> Thomas. >> >>>>>>> Was GPS antenna connected when noise measured like on the picture >> >>>>>>> which you sent us (also attached here)? >> >>>>>>> I would to know because of anomal peak near to 30kHz offset too. >> >>>>>>> >> >>>>>>> Best regards, >> >>>>>>> Andrey Sviyazov. >> >>>>>>> >> >>>>>>> >> >>>>>>> >> >>>>>>> 2012/7/19 Andrey Sviyazov >> >>>>>>>> >> >>>>>>>> Sorry, that was meant to be sent to the mailing list :) >> >>>>>>>> >> >>>>>>>> Best regards, >> >>>>>>>> Andrey Sviyazov. >> >>>>>>>> >> >>>>>>>> ---------- Forwarded message ---------- >> >>>>>>>> From: Andrey Sviyazov >> >>>>>>>> Date: 2012/7/18 >> >>>>>>>> Subject: LMS TxLO noise >> >>>>>>>> >> >>>>>>>> Hi Thomas. >> >>>>>>>> >> >>>>>>>> Here forwarded my last e-mail with noise plots when I stopped >> work >> >>>>>>>> around it at first time, please see below. >> >>>>>>>> >> >>>>>>>> Please try to play around Tx PLL charge pump current (register >> 0x16) >> >>>>>>>> for better RMS phase stability. >> >>>>>>>> I think we should reach 1 degree or below. >> >>>>>>>> >> >>>>>>>> Alexander gave me the second UmTRX board and after checking and >> >>>>>>>> fixing all known hardware issues I've got roughly the same LO >> noise plot. >> >>>>>>>> Possible Robin had no time to fixing all of our issues, so check >> >>>>>>>> them all please. >> >>>>>>>> And also check please what type of TCXO installed on your board. >> >>>>>>>> >> >>>>>>>> Best regards, >> >>>>>>>> Andrey Sviyazov. >> >>>>>>>> >> >>>>>>>> ---------- Forwarded message ---------- >> >>>>>>>> From: Andrey Sviyazov >> >>>>>>>> Date: 2012/4/13 >> >>>>>>>> Subject: Re: LMS TxLO noise >> >>>>>>>> >> >>>>>>>> Hi all. >> >>>>>>>> >> >>>>>>>> There is progress with LMS PLL :) >> >>>>>>>> Pictures are attached here. >> >>>>>>>> t was discovered that 80 kHz spurs come from Ethernet, or rather >> >>>>>>>> from the ET1011. >> >>>>>>>> I unknowingly put the choke between transistor of 1V regulator >> and >> >>>>>>>> analog power 1V. >> >>>>>>>> As a result, the regulator has become unstable and oscillated 80 >> kHz >> >>>>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >> >>>>>>>> To correct this problem L46 should be replaced by jumper on all >> alfa >> >>>>>>>> version PCB's. >> >>>>>>>> >> >>>>>>>> Also I just played with current in the PLL loop, shown on the >> >>>>>>>> picture for clarity. >> >>>>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in >> >>>>>>>> the register of 0x16). >> >>>>>>>> But, I think, for the RxPLL will be better use of the current 2.4 >> >>>>>>>> mA, because the nearest noises more important for Rx (you should >> write 0x98 >> >>>>>>>> in the register 0x26). >> >>>>>>>> >> >>>>>>>> Best regards, >> >>>>>>>> Andrey Sviyazov. >> >>>>>>>> >> >>>>>>>> >> >>>>>>> >> >>>>>> >> >>>>> >> >>>> >> >>> >> >> >> > >> >> >> >> -- >> Regards, >> Alexander Chemeris. >> CEO, Fairwaves LLC / ??? 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URL: From andrey.sviyazov at fairwaves.ru Thu Jul 19 16:06:08 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Thu, 19 Jul 2012 20:06:08 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Thomas. I've calculate few PIF filters for PLL by the ADIsimPLL and found that RMS phase jitter in case of 5kHz and 50kHz only 0.33 and 0.46 degrees. It is very small difference, so are you sure that I should implement 10kHz bandwidth filter as in USRP? Actually it is absolutly not an problem for me to implement it, but I have to be sure. I've calculated it for 10kHz bandwidth, noise plot will be around 75-80dBc/Hz @ 10kHz and 105-110 dBc/Hz @ 100kHz offset. Best regards, Andrey Sviyazov. 2012/7/19 Andrey Sviyazov > Alexander. > I think that few pulses of LMS hardware reset (LMS_NRST-1 and LMS_NRST-2 > pins) will be much easily than all registers checking. > BTW, are there reset pulses after power up or not? > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 Alexander Chemeris > >> Guys, please keep track of all LMS configuration values which are not >> set to default during power on and we'll add them to our manual >> initialization script. >> >> On Thu, Jul 19, 2012 at 6:56 PM, Andrey Sviyazov >> wrote: >> > Sergey. >> > I'll play around GPS power and RTC supply, thank you for your help. >> > >> > Thomas. >> > About r0x16 please be sure that sometimes it isn't set to default value >> > after power up (I saw it few times). >> > Also I think that possible those bad "power on reset" gave us unstable >> > result of LMS autocalibration. >> > >> > Best regards, >> > Andrey Sviyazov. >> > >> > >> > >> > 2012/7/19 sergey kostanbaev >> >> >> >> Which gives ~1.5khz cut-off, that's strange >> >> >> >> Also I'd check GPS VDD and AVDD nosies >> >> >> >> >> >> On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov >> >> wrote: >> >>> >> >>> 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC >> >>> input. >> >>> Of course I'll increase capacitance or resistance to be sure about VC >> >>> pin. >> >>> >> >>> Best regards, >> >>> Andrey Sviyazov. >> >>> >> >>> >> >>> >> >>> 2012/7/19 sergey kostanbaev >> >>>> >> >>>> No :) But it may cause. >> >>>> >> >>>> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is >> >>>> really sensible to any noise. >> >>>> - caused by power supply of DAC. >> >>>> - output noise of DAC. >> >>>> - algorithm of changing values >> >>>> >> >>>> At first I'd inspect VC pin at VCTXCO and try to filter it with >> cut-off >> >>>> frequency 1-0.1 Hz >> >>>> >> >>>> >> >>>> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov >> >>>> wrote: >> >>>>> >> >>>>> Sergey. >> >>>>> Is it really so frequently (32k/s updates at 1pps reference)? >> >>>>> >> >>>>> Best regards, >> >>>>> Andrey Sviyazov. >> >>>>> >> >>>>> >> >>>>> >> >>>>> 2012/7/19 sergey kostanbaev >> >>>>>> >> >>>>>> >> >>>>>> >> >>>>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov >> >>>>>> wrote: >> >>>>>>> >> >>>>>>> Hi all. >> >>>>>>> >> >>>>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz offset >> >>>>>>> when GPS antenna used and position locked. >> >>>>>>> This spurs begin grow up when GPS just near to lock position and >> >>>>>>> after locking spurs stopped to grow as you can see at picture. >> >>>>>>> If thereafter GPS disconnected then noise coming back to normal >> plot. >> >>>>>>> I think that it is result of 32768Hz clock in the GPS module >> EB-230, >> >>>>>>> but can't understant how it can impact to 26MHz clock or VCO. >> >>>>>> >> >>>>>> >> >>>>>> As another idea it can be caused by continues GPS correction lead >> to >> >>>>>> DAC changes to the VCTXCO. >> >>>>>> >> >>>>>>> >> >>>>>>> Please tell me something who know. >> >>>>>>> >> >>>>>>> Thomas. >> >>>>>>> Was GPS antenna connected when noise measured like on the picture >> >>>>>>> which you sent us (also attached here)? >> >>>>>>> I would to know because of anomal peak near to 30kHz offset too. >> >>>>>>> >> >>>>>>> Best regards, >> >>>>>>> Andrey Sviyazov. >> >>>>>>> >> >>>>>>> >> >>>>>>> >> >>>>>>> 2012/7/19 Andrey Sviyazov >> >>>>>>>> >> >>>>>>>> Sorry, that was meant to be sent to the mailing list :) >> >>>>>>>> >> >>>>>>>> Best regards, >> >>>>>>>> Andrey Sviyazov. >> >>>>>>>> >> >>>>>>>> ---------- Forwarded message ---------- >> >>>>>>>> From: Andrey Sviyazov >> >>>>>>>> Date: 2012/7/18 >> >>>>>>>> Subject: LMS TxLO noise >> >>>>>>>> >> >>>>>>>> Hi Thomas. >> >>>>>>>> >> >>>>>>>> Here forwarded my last e-mail with noise plots when I stopped >> work >> >>>>>>>> around it at first time, please see below. >> >>>>>>>> >> >>>>>>>> Please try to play around Tx PLL charge pump current (register >> 0x16) >> >>>>>>>> for better RMS phase stability. >> >>>>>>>> I think we should reach 1 degree or below. >> >>>>>>>> >> >>>>>>>> Alexander gave me the second UmTRX board and after checking and >> >>>>>>>> fixing all known hardware issues I've got roughly the same LO >> noise plot. >> >>>>>>>> Possible Robin had no time to fixing all of our issues, so check >> >>>>>>>> them all please. >> >>>>>>>> And also check please what type of TCXO installed on your board. >> >>>>>>>> >> >>>>>>>> Best regards, >> >>>>>>>> Andrey Sviyazov. >> >>>>>>>> >> >>>>>>>> ---------- Forwarded message ---------- >> >>>>>>>> From: Andrey Sviyazov >> >>>>>>>> Date: 2012/4/13 >> >>>>>>>> Subject: Re: LMS TxLO noise >> >>>>>>>> >> >>>>>>>> Hi all. >> >>>>>>>> >> >>>>>>>> There is progress with LMS PLL :) >> >>>>>>>> Pictures are attached here. >> >>>>>>>> t was discovered that 80 kHz spurs come from Ethernet, or rather >> >>>>>>>> from the ET1011. >> >>>>>>>> I unknowingly put the choke between transistor of 1V regulator >> and >> >>>>>>>> analog power 1V. >> >>>>>>>> As a result, the regulator has become unstable and oscillated 80 >> kHz >> >>>>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >> >>>>>>>> To correct this problem L46 should be replaced by jumper on all >> alfa >> >>>>>>>> version PCB's. >> >>>>>>>> >> >>>>>>>> Also I just played with current in the PLL loop, shown on the >> >>>>>>>> picture for clarity. >> >>>>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 in >> >>>>>>>> the register of 0x16). >> >>>>>>>> But, I think, for the RxPLL will be better use of the current 2.4 >> >>>>>>>> mA, because the nearest noises more important for Rx (you should >> write 0x98 >> >>>>>>>> in the register 0x26). >> >>>>>>>> >> >>>>>>>> Best regards, >> >>>>>>>> Andrey Sviyazov. >> >>>>>>>> >> >>>>>>>> >> >>>>>>> >> >>>>>> >> >>>>> >> >>>> >> >>> >> >> >> > >> >> >> >> -- >> Regards, >> Alexander Chemeris. >> CEO, Fairwaves LLC / ??? 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URL: From thomastsou at gmail.com Fri Jul 20 17:22:48 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Fri, 20 Jul 2012 13:22:48 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Andrey, Sorry I did answer sooner. The E4406A arrived so I have been setting that up. I have UmTRX hooked up right now, which I will be testing very shortly. Thomas On Fri, Jul 20, 2012 at 1:14 PM, Andrey Sviyazov wrote: > Hi Thomas. > > I couldn't wait your reply and start to implement 10kHz BW of PLL. > You can find here two pictures with results. > First of all I found that PLL tuning algorithm doesn't work properly at low > PLL BW. > VCOCAP register (r0x19) should contain higher value at least for +3 units > (to make CAP lower), otherwise freq's above 950MHz never locked. > Note, that you should read and change register 0x19 after autotuning. > Second, you can see some noise difference for the 925MHz because of used > DIV=8 of the VCO, instead of DIV=4 for 942 and 960MHz. > Third, you can see PLL noice dependance with the charge pump current > (r0x16). > > On the other two pictures you can find which components have to be changed. > Thomas, please make one more measure of LO noise and jitter at PLL BW=10kHz > by your instrument. > We need to know, is it real to reach modulation accuracy of 1.5 degrees RMS > or impossible, just because of LMS PLL have bigger jitter. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 Andrey Sviyazov >> >> Thomas. >> I've calculate few PIF filters for PLL by the ADIsimPLL and found that RMS >> phase jitter in case of 5kHz and 50kHz only 0.33 and 0.46 degrees. >> It is very small difference, so are you sure that I should implement 10kHz >> bandwidth filter as in USRP? >> Actually it is absolutly not an problem for me to implement it, but I have >> to be sure. >> I've calculated it for 10kHz bandwidth, noise plot will be around >> 75-80dBc/Hz @ 10kHz and 105-110 dBc/Hz @ 100kHz offset. >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/19 Andrey Sviyazov >>> >>> Alexander. >>> I think that few pulses of LMS hardware reset (LMS_NRST-1 and LMS_NRST-2 >>> pins) will be much easily than all registers checking. >>> BTW, are there reset pulses after power up or not? >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/19 Alexander Chemeris >>>> >>>> Guys, please keep track of all LMS configuration values which are not >>>> set to default during power on and we'll add them to our manual >>>> initialization script. >>>> >>>> On Thu, Jul 19, 2012 at 6:56 PM, Andrey Sviyazov >>>> wrote: >>>> > Sergey. >>>> > I'll play around GPS power and RTC supply, thank you for your help. >>>> > >>>> > Thomas. >>>> > About r0x16 please be sure that sometimes it isn't set to default >>>> > value >>>> > after power up (I saw it few times). >>>> > Also I think that possible those bad "power on reset" gave us unstable >>>> > result of LMS autocalibration. >>>> > >>>> > Best regards, >>>> > Andrey Sviyazov. >>>> > >>>> > >>>> > >>>> > 2012/7/19 sergey kostanbaev >>>> >> >>>> >> Which gives ~1.5khz cut-off, that's strange >>>> >> >>>> >> Also I'd check GPS VDD and AVDD nosies >>>> >> >>>> >> >>>> >> On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov >>>> >> wrote: >>>> >>> >>>> >>> 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC >>>> >>> input. >>>> >>> Of course I'll increase capacitance or resistance to be sure about >>>> >>> VC >>>> >>> pin. >>>> >>> >>>> >>> Best regards, >>>> >>> Andrey Sviyazov. >>>> >>> >>>> >>> >>>> >>> >>>> >>> 2012/7/19 sergey kostanbaev >>>> >>>> >>>> >>>> No :) But it may cause. >>>> >>>> >>>> >>>> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is >>>> >>>> really sensible to any noise. >>>> >>>> - caused by power supply of DAC. >>>> >>>> - output noise of DAC. >>>> >>>> - algorithm of changing values >>>> >>>> >>>> >>>> At first I'd inspect VC pin at VCTXCO and try to filter it with >>>> >>>> cut-off >>>> >>>> frequency 1-0.1 Hz >>>> >>>> >>>> >>>> >>>> >>>> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov >>>> >>>> wrote: >>>> >>>>> >>>> >>>>> Sergey. >>>> >>>>> Is it really so frequently (32k/s updates at 1pps reference)? >>>> >>>>> >>>> >>>>> Best regards, >>>> >>>>> Andrey Sviyazov. >>>> >>>>> >>>> >>>>> >>>> >>>>> >>>> >>>>> 2012/7/19 sergey kostanbaev >>>> >>>>>> >>>> >>>>>> >>>> >>>>>> >>>> >>>>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov >>>> >>>>>> wrote: >>>> >>>>>>> >>>> >>>>>>> Hi all. >>>> >>>>>>> >>>> >>>>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz >>>> >>>>>>> offset >>>> >>>>>>> when GPS antenna used and position locked. >>>> >>>>>>> This spurs begin grow up when GPS just near to lock position and >>>> >>>>>>> after locking spurs stopped to grow as you can see at picture. >>>> >>>>>>> If thereafter GPS disconnected then noise coming back to normal >>>> >>>>>>> plot. >>>> >>>>>>> I think that it is result of 32768Hz clock in the GPS module >>>> >>>>>>> EB-230, >>>> >>>>>>> but can't understant how it can impact to 26MHz clock or VCO. >>>> >>>>>> >>>> >>>>>> >>>> >>>>>> As another idea it can be caused by continues GPS correction lead >>>> >>>>>> to >>>> >>>>>> DAC changes to the VCTXCO. >>>> >>>>>> >>>> >>>>>>> >>>> >>>>>>> Please tell me something who know. >>>> >>>>>>> >>>> >>>>>>> Thomas. >>>> >>>>>>> Was GPS antenna connected when noise measured like on the >>>> >>>>>>> picture >>>> >>>>>>> which you sent us (also attached here)? >>>> >>>>>>> I would to know because of anomal peak near to 30kHz offset too. >>>> >>>>>>> >>>> >>>>>>> Best regards, >>>> >>>>>>> Andrey Sviyazov. >>>> >>>>>>> >>>> >>>>>>> >>>> >>>>>>> >>>> >>>>>>> 2012/7/19 Andrey Sviyazov >>>> >>>>>>>> >>>> >>>>>>>> Sorry, that was meant to be sent to the mailing list :) >>>> >>>>>>>> >>>> >>>>>>>> Best regards, >>>> >>>>>>>> Andrey Sviyazov. >>>> >>>>>>>> >>>> >>>>>>>> ---------- Forwarded message ---------- >>>> >>>>>>>> From: Andrey Sviyazov >>>> >>>>>>>> Date: 2012/7/18 >>>> >>>>>>>> Subject: LMS TxLO noise >>>> >>>>>>>> >>>> >>>>>>>> Hi Thomas. >>>> >>>>>>>> >>>> >>>>>>>> Here forwarded my last e-mail with noise plots when I stopped >>>> >>>>>>>> work >>>> >>>>>>>> around it at first time, please see below. >>>> >>>>>>>> >>>> >>>>>>>> Please try to play around Tx PLL charge pump current (register >>>> >>>>>>>> 0x16) >>>> >>>>>>>> for better RMS phase stability. >>>> >>>>>>>> I think we should reach 1 degree or below. >>>> >>>>>>>> >>>> >>>>>>>> Alexander gave me the second UmTRX board and after checking and >>>> >>>>>>>> fixing all known hardware issues I've got roughly the same LO >>>> >>>>>>>> noise plot. >>>> >>>>>>>> Possible Robin had no time to fixing all of our issues, so >>>> >>>>>>>> check >>>> >>>>>>>> them all please. >>>> >>>>>>>> And also check please what type of TCXO installed on your >>>> >>>>>>>> board. >>>> >>>>>>>> >>>> >>>>>>>> Best regards, >>>> >>>>>>>> Andrey Sviyazov. >>>> >>>>>>>> >>>> >>>>>>>> ---------- Forwarded message ---------- >>>> >>>>>>>> From: Andrey Sviyazov >>>> >>>>>>>> Date: 2012/4/13 >>>> >>>>>>>> Subject: Re: LMS TxLO noise >>>> >>>>>>>> >>>> >>>>>>>> Hi all. >>>> >>>>>>>> >>>> >>>>>>>> There is progress with LMS PLL :) >>>> >>>>>>>> Pictures are attached here. >>>> >>>>>>>> t was discovered that 80 kHz spurs come from Ethernet, or >>>> >>>>>>>> rather >>>> >>>>>>>> from the ET1011. >>>> >>>>>>>> I unknowingly put the choke between transistor of 1V regulator >>>> >>>>>>>> and >>>> >>>>>>>> analog power 1V. >>>> >>>>>>>> As a result, the regulator has become unstable and oscillated >>>> >>>>>>>> 80 kHz >>>> >>>>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>>> >>>>>>>> To correct this problem L46 should be replaced by jumper on all >>>> >>>>>>>> alfa >>>> >>>>>>>> version PCB's. >>>> >>>>>>>> >>>> >>>>>>>> Also I just played with current in the PLL loop, shown on the >>>> >>>>>>>> picture for clarity. >>>> >>>>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 >>>> >>>>>>>> in >>>> >>>>>>>> the register of 0x16). >>>> >>>>>>>> But, I think, for the RxPLL will be better use of the current >>>> >>>>>>>> 2.4 >>>> >>>>>>>> mA, because the nearest noises more important for Rx (you >>>> >>>>>>>> should write 0x98 >>>> >>>>>>>> in the register 0x26). >>>> >>>>>>>> >>>> >>>>>>>> Best regards, >>>> >>>>>>>> Andrey Sviyazov. >>>> >>>>>>>> >>>> >>>>>>>> >>>> >>>>>>> >>>> >>>>>> >>>> >>>>> >>>> >>>> >>>> >>> >>>> >> >>>> > >>>> >>>> >>>> >>>> -- >>>> Regards, >>>> Alexander Chemeris. >>>> CEO, Fairwaves LLC / ??? ??????? >>>> http://fairwaves.ru >>> >>> >> > From thomastsou at gmail.com Fri Jul 20 17:22:48 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Fri, 20 Jul 2012 13:22:48 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Andrey, Sorry I did answer sooner. The E4406A arrived so I have been setting that up. I have UmTRX hooked up right now, which I will be testing very shortly. Thomas On Fri, Jul 20, 2012 at 1:14 PM, Andrey Sviyazov wrote: > Hi Thomas. > > I couldn't wait your reply and start to implement 10kHz BW of PLL. > You can find here two pictures with results. > First of all I found that PLL tuning algorithm doesn't work properly at low > PLL BW. > VCOCAP register (r0x19) should contain higher value at least for +3 units > (to make CAP lower), otherwise freq's above 950MHz never locked. > Note, that you should read and change register 0x19 after autotuning. > Second, you can see some noise difference for the 925MHz because of used > DIV=8 of the VCO, instead of DIV=4 for 942 and 960MHz. > Third, you can see PLL noice dependance with the charge pump current > (r0x16). > > On the other two pictures you can find which components have to be changed. > Thomas, please make one more measure of LO noise and jitter at PLL BW=10kHz > by your instrument. > We need to know, is it real to reach modulation accuracy of 1.5 degrees RMS > or impossible, just because of LMS PLL have bigger jitter. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 Andrey Sviyazov >> >> Thomas. >> I've calculate few PIF filters for PLL by the ADIsimPLL and found that RMS >> phase jitter in case of 5kHz and 50kHz only 0.33 and 0.46 degrees. >> It is very small difference, so are you sure that I should implement 10kHz >> bandwidth filter as in USRP? >> Actually it is absolutly not an problem for me to implement it, but I have >> to be sure. >> I've calculated it for 10kHz bandwidth, noise plot will be around >> 75-80dBc/Hz @ 10kHz and 105-110 dBc/Hz @ 100kHz offset. >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/19 Andrey Sviyazov >>> >>> Alexander. >>> I think that few pulses of LMS hardware reset (LMS_NRST-1 and LMS_NRST-2 >>> pins) will be much easily than all registers checking. >>> BTW, are there reset pulses after power up or not? >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/19 Alexander Chemeris >>>> >>>> Guys, please keep track of all LMS configuration values which are not >>>> set to default during power on and we'll add them to our manual >>>> initialization script. >>>> >>>> On Thu, Jul 19, 2012 at 6:56 PM, Andrey Sviyazov >>>> wrote: >>>> > Sergey. >>>> > I'll play around GPS power and RTC supply, thank you for your help. >>>> > >>>> > Thomas. >>>> > About r0x16 please be sure that sometimes it isn't set to default >>>> > value >>>> > after power up (I saw it few times). >>>> > Also I think that possible those bad "power on reset" gave us unstable >>>> > result of LMS autocalibration. >>>> > >>>> > Best regards, >>>> > Andrey Sviyazov. >>>> > >>>> > >>>> > >>>> > 2012/7/19 sergey kostanbaev >>>> >> >>>> >> Which gives ~1.5khz cut-off, that's strange >>>> >> >>>> >> Also I'd check GPS VDD and AVDD nosies >>>> >> >>>> >> >>>> >> On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov >>>> >> wrote: >>>> >>> >>>> >>> 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC >>>> >>> input. >>>> >>> Of course I'll increase capacitance or resistance to be sure about >>>> >>> VC >>>> >>> pin. >>>> >>> >>>> >>> Best regards, >>>> >>> Andrey Sviyazov. >>>> >>> >>>> >>> >>>> >>> >>>> >>> 2012/7/19 sergey kostanbaev >>>> >>>> >>>> >>>> No :) But it may cause. >>>> >>>> >>>> >>>> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is >>>> >>>> really sensible to any noise. >>>> >>>> - caused by power supply of DAC. >>>> >>>> - output noise of DAC. >>>> >>>> - algorithm of changing values >>>> >>>> >>>> >>>> At first I'd inspect VC pin at VCTXCO and try to filter it with >>>> >>>> cut-off >>>> >>>> frequency 1-0.1 Hz >>>> >>>> >>>> >>>> >>>> >>>> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov >>>> >>>> wrote: >>>> >>>>> >>>> >>>>> Sergey. >>>> >>>>> Is it really so frequently (32k/s updates at 1pps reference)? >>>> >>>>> >>>> >>>>> Best regards, >>>> >>>>> Andrey Sviyazov. >>>> >>>>> >>>> >>>>> >>>> >>>>> >>>> >>>>> 2012/7/19 sergey kostanbaev >>>> >>>>>> >>>> >>>>>> >>>> >>>>>> >>>> >>>>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov >>>> >>>>>> wrote: >>>> >>>>>>> >>>> >>>>>>> Hi all. >>>> >>>>>>> >>>> >>>>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz >>>> >>>>>>> offset >>>> >>>>>>> when GPS antenna used and position locked. >>>> >>>>>>> This spurs begin grow up when GPS just near to lock position and >>>> >>>>>>> after locking spurs stopped to grow as you can see at picture. >>>> >>>>>>> If thereafter GPS disconnected then noise coming back to normal >>>> >>>>>>> plot. >>>> >>>>>>> I think that it is result of 32768Hz clock in the GPS module >>>> >>>>>>> EB-230, >>>> >>>>>>> but can't understant how it can impact to 26MHz clock or VCO. >>>> >>>>>> >>>> >>>>>> >>>> >>>>>> As another idea it can be caused by continues GPS correction lead >>>> >>>>>> to >>>> >>>>>> DAC changes to the VCTXCO. >>>> >>>>>> >>>> >>>>>>> >>>> >>>>>>> Please tell me something who know. >>>> >>>>>>> >>>> >>>>>>> Thomas. >>>> >>>>>>> Was GPS antenna connected when noise measured like on the >>>> >>>>>>> picture >>>> >>>>>>> which you sent us (also attached here)? >>>> >>>>>>> I would to know because of anomal peak near to 30kHz offset too. >>>> >>>>>>> >>>> >>>>>>> Best regards, >>>> >>>>>>> Andrey Sviyazov. >>>> >>>>>>> >>>> >>>>>>> >>>> >>>>>>> >>>> >>>>>>> 2012/7/19 Andrey Sviyazov >>>> >>>>>>>> >>>> >>>>>>>> Sorry, that was meant to be sent to the mailing list :) >>>> >>>>>>>> >>>> >>>>>>>> Best regards, >>>> >>>>>>>> Andrey Sviyazov. >>>> >>>>>>>> >>>> >>>>>>>> ---------- Forwarded message ---------- >>>> >>>>>>>> From: Andrey Sviyazov >>>> >>>>>>>> Date: 2012/7/18 >>>> >>>>>>>> Subject: LMS TxLO noise >>>> >>>>>>>> >>>> >>>>>>>> Hi Thomas. >>>> >>>>>>>> >>>> >>>>>>>> Here forwarded my last e-mail with noise plots when I stopped >>>> >>>>>>>> work >>>> >>>>>>>> around it at first time, please see below. >>>> >>>>>>>> >>>> >>>>>>>> Please try to play around Tx PLL charge pump current (register >>>> >>>>>>>> 0x16) >>>> >>>>>>>> for better RMS phase stability. >>>> >>>>>>>> I think we should reach 1 degree or below. >>>> >>>>>>>> >>>> >>>>>>>> Alexander gave me the second UmTRX board and after checking and >>>> >>>>>>>> fixing all known hardware issues I've got roughly the same LO >>>> >>>>>>>> noise plot. >>>> >>>>>>>> Possible Robin had no time to fixing all of our issues, so >>>> >>>>>>>> check >>>> >>>>>>>> them all please. >>>> >>>>>>>> And also check please what type of TCXO installed on your >>>> >>>>>>>> board. >>>> >>>>>>>> >>>> >>>>>>>> Best regards, >>>> >>>>>>>> Andrey Sviyazov. >>>> >>>>>>>> >>>> >>>>>>>> ---------- Forwarded message ---------- >>>> >>>>>>>> From: Andrey Sviyazov >>>> >>>>>>>> Date: 2012/4/13 >>>> >>>>>>>> Subject: Re: LMS TxLO noise >>>> >>>>>>>> >>>> >>>>>>>> Hi all. >>>> >>>>>>>> >>>> >>>>>>>> There is progress with LMS PLL :) >>>> >>>>>>>> Pictures are attached here. >>>> >>>>>>>> t was discovered that 80 kHz spurs come from Ethernet, or >>>> >>>>>>>> rather >>>> >>>>>>>> from the ET1011. >>>> >>>>>>>> I unknowingly put the choke between transistor of 1V regulator >>>> >>>>>>>> and >>>> >>>>>>>> analog power 1V. >>>> >>>>>>>> As a result, the regulator has become unstable and oscillated >>>> >>>>>>>> 80 kHz >>>> >>>>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>>> >>>>>>>> To correct this problem L46 should be replaced by jumper on all >>>> >>>>>>>> alfa >>>> >>>>>>>> version PCB's. >>>> >>>>>>>> >>>> >>>>>>>> Also I just played with current in the PLL loop, shown on the >>>> >>>>>>>> picture for clarity. >>>> >>>>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 >>>> >>>>>>>> in >>>> >>>>>>>> the register of 0x16). >>>> >>>>>>>> But, I think, for the RxPLL will be better use of the current >>>> >>>>>>>> 2.4 >>>> >>>>>>>> mA, because the nearest noises more important for Rx (you >>>> >>>>>>>> should write 0x98 >>>> >>>>>>>> in the register 0x26). >>>> >>>>>>>> >>>> >>>>>>>> Best regards, >>>> >>>>>>>> Andrey Sviyazov. >>>> >>>>>>>> >>>> >>>>>>>> >>>> >>>>>>> >>>> >>>>>> >>>> >>>>> >>>> >>>> >>>> >>> >>>> >> >>>> > >>>> >>>> >>>> >>>> -- >>>> Regards, >>>> Alexander Chemeris. >>>> CEO, Fairwaves LLC / ??? ??????? >>>> http://fairwaves.ru >>> >>> >> > From plddesigner at gmail.com Fri Jul 20 19:28:25 2012 From: plddesigner at gmail.com (Andrew Karpenkov) Date: Fri, 20 Jul 2012 23:28:25 +0400 Subject: UmTRX dual-channel Rx In-Reply-To: References: Message-ID: Hi all, I added control logic for diversity switches into fpga part of project. Now you can manage them by setting the appropriate values ??in registers sr_divsw1 (180 0 adress in decimal) and sr_divsw2 (180 1 address in decimal). But I'm not tested this options yet. The following Monday I plan to do it. All changes are availible in akarpenkov/dual-channel branch at github repository. Regards, Andrew Karpenkov 2012/7/19 Alexander Chemeris > Thanks. Looking forward for it. > > On Thu, Jul 19, 2012 at 2:42 PM, Andrew Karpenkov > wrote: > > Yes, I can add this option. I'll try to do it, and tomorrow make changes > at > > github. > > > > Regards, > > Andrew Karpenkov > > > > Sent from my Android device. > > > > 19.07.2012 14:29 ???????????? "Alexander Chemeris" > > ???????: > > > >> On Thu, Jul 19, 2012 at 1:33 PM, Andrey Sviyazov > >> wrote: > >> > Andrew Karpenkov, would you please to make this kind changes, until > >> > DIVSW > >> > will controled by host? > >> > >> That's an interesting question. Andrey Karpenkov - is there a way to > >> control them from ZPU? Some config register? > >> > >> > >> -- > >> Regards, > >> Alexander Chemeris. > >> CEO, Fairwaves LLC / ??? ??????? > >> http://fairwaves.ru > > > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: From plddesigner at gmail.com Fri Jul 20 19:28:25 2012 From: plddesigner at gmail.com (Andrew Karpenkov) Date: Fri, 20 Jul 2012 23:28:25 +0400 Subject: UmTRX dual-channel Rx In-Reply-To: References: Message-ID: Hi all, I added control logic for diversity switches into fpga part of project. Now you can manage them by setting the appropriate values ??in registers sr_divsw1 (180 0 adress in decimal) and sr_divsw2 (180 1 address in decimal). But I'm not tested this options yet. The following Monday I plan to do it. All changes are availible in akarpenkov/dual-channel branch at github repository. Regards, Andrew Karpenkov 2012/7/19 Alexander Chemeris > Thanks. Looking forward for it. > > On Thu, Jul 19, 2012 at 2:42 PM, Andrew Karpenkov > wrote: > > Yes, I can add this option. I'll try to do it, and tomorrow make changes > at > > github. > > > > Regards, > > Andrew Karpenkov > > > > Sent from my Android device. > > > > 19.07.2012 14:29 ???????????? "Alexander Chemeris" > > ???????: > > > >> On Thu, Jul 19, 2012 at 1:33 PM, Andrey Sviyazov > >> wrote: > >> > Andrew Karpenkov, would you please to make this kind changes, until > >> > DIVSW > >> > will controled by host? > >> > >> That's an interesting question. Andrey Karpenkov - is there a way to > >> control them from ZPU? Some config register? > >> > >> > >> -- > >> Regards, > >> Alexander Chemeris. > >> CEO, Fairwaves LLC / ??? ??????? > >> http://fairwaves.ru > > > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Fri Jul 20 19:31:56 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Fri, 20 Jul 2012 23:31:56 +0400 Subject: UmTRX dual-channel Rx In-Reply-To: References: Message-ID: Andrew, thank you! Could you send me compiled bitstreams? I'll put them to the server for download. Sent from my Android device. -- Regards, Alexander Chemeris CEO, Fairwaves LLC http://fairwaves.ru 20.07.2012 23:28 ???????????? "Andrew Karpenkov" ???????: > Hi all, > > I added control logic for diversity switches into fpga part of project. > Now you can manage them by setting the appropriate values ??in registers > sr_divsw1 (180 0 adress in decimal) and sr_divsw2 (180 1 address in > decimal). But I'm not tested this options yet. The following Monday I plan > to do it. > All changes are availible in akarpenkov/dual-channel branch at github > repository. > > Regards, > Andrew Karpenkov > > > 2012/7/19 Alexander Chemeris > >> Thanks. Looking forward for it. >> >> On Thu, Jul 19, 2012 at 2:42 PM, Andrew Karpenkov >> wrote: >> > Yes, I can add this option. I'll try to do it, and tomorrow make >> changes at >> > github. >> > >> > Regards, >> > Andrew Karpenkov >> > >> > Sent from my Android device. >> > >> > 19.07.2012 14:29 ???????????? "Alexander Chemeris" >> > ???????: >> > >> >> On Thu, Jul 19, 2012 at 1:33 PM, Andrey Sviyazov >> >> wrote: >> >> > Andrew Karpenkov, would you please to make this kind changes, until >> >> > DIVSW >> >> > will controled by host? >> >> >> >> That's an interesting question. Andrey Karpenkov - is there a way to >> >> control them from ZPU? Some config register? >> >> >> >> >> >> -- >> >> Regards, >> >> Alexander Chemeris. >> >> CEO, Fairwaves LLC / ??? ??????? >> >> http://fairwaves.ru >> >> >> >> -- >> Regards, >> Alexander Chemeris. >> CEO, Fairwaves LLC / ??? ??????? >> http://fairwaves.ru >> > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Fri Jul 20 19:31:56 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Fri, 20 Jul 2012 23:31:56 +0400 Subject: UmTRX dual-channel Rx In-Reply-To: References: Message-ID: Andrew, thank you! Could you send me compiled bitstreams? I'll put them to the server for download. Sent from my Android device. -- Regards, Alexander Chemeris CEO, Fairwaves LLC http://fairwaves.ru 20.07.2012 23:28 ???????????? "Andrew Karpenkov" ???????: > Hi all, > > I added control logic for diversity switches into fpga part of project. > Now you can manage them by setting the appropriate values ??in registers > sr_divsw1 (180 0 adress in decimal) and sr_divsw2 (180 1 address in > decimal). But I'm not tested this options yet. The following Monday I plan > to do it. > All changes are availible in akarpenkov/dual-channel branch at github > repository. > > Regards, > Andrew Karpenkov > > > 2012/7/19 Alexander Chemeris > >> Thanks. Looking forward for it. >> >> On Thu, Jul 19, 2012 at 2:42 PM, Andrew Karpenkov >> wrote: >> > Yes, I can add this option. I'll try to do it, and tomorrow make >> changes at >> > github. >> > >> > Regards, >> > Andrew Karpenkov >> > >> > Sent from my Android device. >> > >> > 19.07.2012 14:29 ???????????? "Alexander Chemeris" >> > ???????: >> > >> >> On Thu, Jul 19, 2012 at 1:33 PM, Andrey Sviyazov >> >> wrote: >> >> > Andrew Karpenkov, would you please to make this kind changes, until >> >> > DIVSW >> >> > will controled by host? >> >> >> >> That's an interesting question. Andrey Karpenkov - is there a way to >> >> control them from ZPU? Some config register? >> >> >> >> >> >> -- >> >> Regards, >> >> Alexander Chemeris. >> >> CEO, Fairwaves LLC / ??? ??????? >> >> http://fairwaves.ru >> >> >> >> -- >> Regards, >> Alexander Chemeris. >> CEO, Fairwaves LLC / ??? ??????? >> http://fairwaves.ru >> > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From thomastsou at gmail.com Fri Jul 20 20:22:49 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Fri, 20 Jul 2012 16:22:49 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Fri, Jul 20, 2012 at 1:14 PM, Andrey Sviyazov wrote: > Hi Thomas. > > I couldn't wait your reply and start to implement 10kHz BW of PLL. > You can find here two pictures with results. > First of all I found that PLL tuning algorithm doesn't work properly at low > PLL BW. > VCOCAP register (r0x19) should contain higher value at least for +3 units > (to make CAP lower), otherwise freq's above 950MHz never locked. > Note, that you should read and change register 0x19 after autotuning. > Second, you can see some noise difference for the 925MHz because of used > DIV=8 of the VCO, instead of DIV=4 for 942 and 960MHz. > Third, you can see PLL noice dependance with the charge pump current > (r0x16). > > On the other two pictures you can find which components have to be changed. > Thomas, please make one more measure of LO noise and jitter at PLL BW=10kHz > by your instrument. > We need to know, is it real to reach modulation accuracy of 1.5 degrees RMS > or impossible, just because of LMS PLL have bigger jitter. Here are phase noise plots with following settings measured at 925 MHz and 945 MHz. --reg 0x16 --data 0x93 --reg 0x26 --data 0x98 Charge pump current had a definite effect as did changing the frequency. Measured on the E4406A, phase error is quite high. There are still other calibration issues, but phase noise is probably still a concern. I also still have errors with auto calibration. Note that USRP1 - with better phase noise - does not reach < 1.5 degree error, but is close at < 2.0 degrees RMS. I'm currently going through the previous issues. If there is anything else I should examine or test, let me know. Thomas -------------- next part -------------- [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --lms-init [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --lms-tx-enable 1 [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --reg 0x34 --data 0x3e [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --pll-ref-clock 26e6 --lpf-bandwidth-code 0x0f --lms-auto-calibration LPF Tuning... DC_REGVAL = 31 LPF Bandwidth Tuning... FREQSEL=47 VCO_X=16 NINT=196 NFRACK=7743330 VOVCO[0]=2 VOVCO[1]=2 VOVCO[2]=2 VOVCO[3]=2 VOVCO[4]=2 VOVCO[5]=2 VOVCO[6]=2 VOVCO[7]=2 VOVCO[8]=2 VOVCO[9]=2 VOVCO[10]=2 VOVCO[11]=2 VOVCO[12]=2 VOVCO[13]=2 VOVCO[14]=2 VOVCO[15]=2 VOVCO[16]=2 VOVCO[17]=2 VOVCO[18]=2 VOVCO[19]=2 VOVCO[20]=2 VOVCO[21]=2 VOVCO[22]=2 VOVCO[23]=2 VOVCO[24]=2 VOVCO[25]=2 VOVCO[26]=2 VOVCO[27]=2 VOVCO[28]=2 VOVCO[29]=2 VOVCO[30]=2 VOVCO[31]=2 VOVCO[32]=2 VOVCO[33]=2 VOVCO[34]=2 VOVCO[35]=2 VOVCO[36]=2 VOVCO[37]=2 VOVCO[38]=2 VOVCO[39]=2 VOVCO[40]=2 VOVCO[41]=0 Norm VOVCO[42]=0 VOVCO[43]=0 VOVCO[44]=0 VOVCO[45]=0 VOVCO[46]=0 VOVCO[47]=0 VOVCO[48]=0 VOVCO[49]=0 VOVCO[50]=0 VOVCO[51]=0 VOVCO[52]=1 Low VOVCO[53]=1 VOVCO[54]=1 VOVCO[55]=1 VOVCO[56]=1 VOVCO[57]=1 VOVCO[58]=1 VOVCO[59]=1 VOVCO[60]=1 VOVCO[61]=1 VOVCO[62]=1 VOVCO[63]=1 START=41 STOP=51 SET=46 code = f f f RCCAL = 7 Tx LPF DC calibration... DC_REGVAL = 33 DC_REGVAL = 33 Rx LPF DC calibration... Error: DC Offset Calibration does not converge! RxVGA2 DC calibration... Error: DC Offset Calibration does not converge! [ttsouu at ovid utils (umtrx)]$ -------------- next part -------------- A non-text attachment was scrubbed... Name: usrp1_52_phs_noise.PNG Type: image/png Size: 74575 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_phs_noise_925.PNG Type: image/png Size: 74696 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_phs_noise_945.PNG Type: image/png Size: 74751 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: screen4.bmp Type: image/bmp Size: 70460 bytes Desc: not available URL: From thomastsou at gmail.com Fri Jul 20 20:22:49 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Fri, 20 Jul 2012 16:22:49 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Fri, Jul 20, 2012 at 1:14 PM, Andrey Sviyazov wrote: > Hi Thomas. > > I couldn't wait your reply and start to implement 10kHz BW of PLL. > You can find here two pictures with results. > First of all I found that PLL tuning algorithm doesn't work properly at low > PLL BW. > VCOCAP register (r0x19) should contain higher value at least for +3 units > (to make CAP lower), otherwise freq's above 950MHz never locked. > Note, that you should read and change register 0x19 after autotuning. > Second, you can see some noise difference for the 925MHz because of used > DIV=8 of the VCO, instead of DIV=4 for 942 and 960MHz. > Third, you can see PLL noice dependance with the charge pump current > (r0x16). > > On the other two pictures you can find which components have to be changed. > Thomas, please make one more measure of LO noise and jitter at PLL BW=10kHz > by your instrument. > We need to know, is it real to reach modulation accuracy of 1.5 degrees RMS > or impossible, just because of LMS PLL have bigger jitter. Here are phase noise plots with following settings measured at 925 MHz and 945 MHz. --reg 0x16 --data 0x93 --reg 0x26 --data 0x98 Charge pump current had a definite effect as did changing the frequency. Measured on the E4406A, phase error is quite high. There are still other calibration issues, but phase noise is probably still a concern. I also still have errors with auto calibration. Note that USRP1 - with better phase noise - does not reach < 1.5 degree error, but is close at < 2.0 degrees RMS. I'm currently going through the previous issues. If there is anything else I should examine or test, let me know. Thomas -------------- next part -------------- [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --lms-init [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --lms-tx-enable 1 [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --reg 0x34 --data 0x3e [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --pll-ref-clock 26e6 --lpf-bandwidth-code 0x0f --lms-auto-calibration LPF Tuning... DC_REGVAL = 31 LPF Bandwidth Tuning... FREQSEL=47 VCO_X=16 NINT=196 NFRACK=7743330 VOVCO[0]=2 VOVCO[1]=2 VOVCO[2]=2 VOVCO[3]=2 VOVCO[4]=2 VOVCO[5]=2 VOVCO[6]=2 VOVCO[7]=2 VOVCO[8]=2 VOVCO[9]=2 VOVCO[10]=2 VOVCO[11]=2 VOVCO[12]=2 VOVCO[13]=2 VOVCO[14]=2 VOVCO[15]=2 VOVCO[16]=2 VOVCO[17]=2 VOVCO[18]=2 VOVCO[19]=2 VOVCO[20]=2 VOVCO[21]=2 VOVCO[22]=2 VOVCO[23]=2 VOVCO[24]=2 VOVCO[25]=2 VOVCO[26]=2 VOVCO[27]=2 VOVCO[28]=2 VOVCO[29]=2 VOVCO[30]=2 VOVCO[31]=2 VOVCO[32]=2 VOVCO[33]=2 VOVCO[34]=2 VOVCO[35]=2 VOVCO[36]=2 VOVCO[37]=2 VOVCO[38]=2 VOVCO[39]=2 VOVCO[40]=2 VOVCO[41]=0 Norm VOVCO[42]=0 VOVCO[43]=0 VOVCO[44]=0 VOVCO[45]=0 VOVCO[46]=0 VOVCO[47]=0 VOVCO[48]=0 VOVCO[49]=0 VOVCO[50]=0 VOVCO[51]=0 VOVCO[52]=1 Low VOVCO[53]=1 VOVCO[54]=1 VOVCO[55]=1 VOVCO[56]=1 VOVCO[57]=1 VOVCO[58]=1 VOVCO[59]=1 VOVCO[60]=1 VOVCO[61]=1 VOVCO[62]=1 VOVCO[63]=1 START=41 STOP=51 SET=46 code = f f f RCCAL = 7 Tx LPF DC calibration... DC_REGVAL = 33 DC_REGVAL = 33 Rx LPF DC calibration... Error: DC Offset Calibration does not converge! RxVGA2 DC calibration... Error: DC Offset Calibration does not converge! [ttsouu at ovid utils (umtrx)]$ -------------- next part -------------- A non-text attachment was scrubbed... Name: usrp1_52_phs_noise.PNG Type: image/png Size: 74575 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_phs_noise_925.PNG Type: image/png Size: 74696 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_phs_noise_945.PNG Type: image/png Size: 74751 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: screen4.bmp Type: image/bmp Size: 70460 bytes Desc: not available URL: From andrey.sviyazov at fairwaves.ru Fri Jul 20 21:33:40 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Sat, 21 Jul 2012 01:33:40 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Thomas. First of all thank you very much. And of course few questions: 1 why you use too small input signal to the analyser? I saw -120dBc/Hz @ 1MHz offset. 2 do you test LO with small CP current? 3 I don't see now noise peak @ 30kHz. Do you change something? 4 can 4406 measuring noise plot with log freq? 5 what type of modulation you use now? I mean 1 sps or 2? Best regards, Andrey Sviyazov. (Sent from my mobile client) 21.07.2012 0:23 ???????????? "Thomas Tsou" ???????: > On Fri, Jul 20, 2012 at 1:14 PM, Andrey Sviyazov > wrote: > > Hi Thomas. > > > > I couldn't wait your reply and start to implement 10kHz BW of PLL. > > You can find here two pictures with results. > > First of all I found that PLL tuning algorithm doesn't work properly at > low > > PLL BW. > > VCOCAP register (r0x19) should contain higher value at least for +3 units > > (to make CAP lower), otherwise freq's above 950MHz never locked. > > Note, that you should read and change register 0x19 after autotuning. > > Second, you can see some noise difference for the 925MHz because of used > > DIV=8 of the VCO, instead of DIV=4 for 942 and 960MHz. > > Third, you can see PLL noice dependance with the charge pump current > > (r0x16). > > > > On the other two pictures you can find which components have to be > changed. > > Thomas, please make one more measure of LO noise and jitter at PLL > BW=10kHz > > by your instrument. > > We need to know, is it real to reach modulation accuracy of 1.5 degrees > RMS > > or impossible, just because of LMS PLL have bigger jitter. > > Here are phase noise plots with following settings measured at 925 MHz > and 945 MHz. > > --reg 0x16 --data 0x93 > --reg 0x26 --data 0x98 > > Charge pump current had a definite effect as did changing the > frequency. Measured on the E4406A, phase error is quite high. There > are still other calibration issues, but phase noise is probably still > a concern. I also still have errors with auto calibration. > > Note that USRP1 - with better phase noise - does not reach < 1.5 > degree error, but is close at < 2.0 degrees RMS. > > I'm currently going through the previous issues. If there is anything > else I should examine or test, let me know. > > Thomas > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andrey.sviyazov at fairwaves.ru Fri Jul 20 21:33:40 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Sat, 21 Jul 2012 01:33:40 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Thomas. First of all thank you very much. And of course few questions: 1 why you use too small input signal to the analyser? I saw -120dBc/Hz @ 1MHz offset. 2 do you test LO with small CP current? 3 I don't see now noise peak @ 30kHz. Do you change something? 4 can 4406 measuring noise plot with log freq? 5 what type of modulation you use now? I mean 1 sps or 2? Best regards, Andrey Sviyazov. (Sent from my mobile client) 21.07.2012 0:23 ???????????? "Thomas Tsou" ???????: > On Fri, Jul 20, 2012 at 1:14 PM, Andrey Sviyazov > wrote: > > Hi Thomas. > > > > I couldn't wait your reply and start to implement 10kHz BW of PLL. > > You can find here two pictures with results. > > First of all I found that PLL tuning algorithm doesn't work properly at > low > > PLL BW. > > VCOCAP register (r0x19) should contain higher value at least for +3 units > > (to make CAP lower), otherwise freq's above 950MHz never locked. > > Note, that you should read and change register 0x19 after autotuning. > > Second, you can see some noise difference for the 925MHz because of used > > DIV=8 of the VCO, instead of DIV=4 for 942 and 960MHz. > > Third, you can see PLL noice dependance with the charge pump current > > (r0x16). > > > > On the other two pictures you can find which components have to be > changed. > > Thomas, please make one more measure of LO noise and jitter at PLL > BW=10kHz > > by your instrument. > > We need to know, is it real to reach modulation accuracy of 1.5 degrees > RMS > > or impossible, just because of LMS PLL have bigger jitter. > > Here are phase noise plots with following settings measured at 925 MHz > and 945 MHz. > > --reg 0x16 --data 0x93 > --reg 0x26 --data 0x98 > > Charge pump current had a definite effect as did changing the > frequency. Measured on the E4406A, phase error is quite high. There > are still other calibration issues, but phase noise is probably still > a concern. I also still have errors with auto calibration. > > Note that USRP1 - with better phase noise - does not reach < 1.5 > degree error, but is close at < 2.0 degrees RMS. > > I'm currently going through the previous issues. If there is anything > else I should examine or test, let me know. > > Thomas > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andrey.sviyazov at fairwaves.ru Fri Jul 20 17:14:00 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Fri, 20 Jul 2012 21:14:00 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Thomas. I couldn't wait your reply and start to implement 10kHz BW of PLL. You can find here two pictures with results. First of all I found that PLL tuning algorithm doesn't work properly at low PLL BW. VCOCAP register (r0x19) should contain higher value at least for +3 units (to make CAP lower), otherwise freq's above 950MHz never locked. Note, that you should read and change register 0x19 after autotuning. Second, you can see some noise difference for the 925MHz because of used DIV=8 of the VCO, instead of DIV=4 for 942 and 960MHz. Third, you can see PLL noice dependance with the charge pump current (r0x16). On the other two pictures you can find which components have to be changed. Thomas, please make one more measure of LO noise and jitter at PLL BW=10kHz by your instrument. We need to know, is it real to reach modulation accuracy of 1.5 degrees RMS or impossible, just because of LMS PLL have bigger jitter. Best regards, Andrey Sviyazov. 2012/7/19 Andrey Sviyazov > Thomas. > I've calculate few PIF filters for PLL by the ADIsimPLL and found that RMS > phase jitter in case of 5kHz and 50kHz only 0.33 and 0.46 degrees. > It is very small difference, so are you sure that I should implement 10kHz > bandwidth filter as in USRP? > Actually it is absolutly not an problem for me to implement it, but I have > to be sure. > I've calculated it for 10kHz bandwidth, noise plot will be around > 75-80dBc/Hz @ 10kHz and 105-110 dBc/Hz @ 100kHz offset. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 Andrey Sviyazov > >> Alexander. >> I think that few pulses of LMS hardware reset (LMS_NRST-1 and LMS_NRST-2 >> pins) will be much easily than all registers checking. >> BTW, are there reset pulses after power up or not? >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/19 Alexander Chemeris >> >>> Guys, please keep track of all LMS configuration values which are not >>> set to default during power on and we'll add them to our manual >>> initialization script. >>> >>> On Thu, Jul 19, 2012 at 6:56 PM, Andrey Sviyazov >>> wrote: >>> > Sergey. >>> > I'll play around GPS power and RTC supply, thank you for your help. >>> > >>> > Thomas. >>> > About r0x16 please be sure that sometimes it isn't set to default value >>> > after power up (I saw it few times). >>> > Also I think that possible those bad "power on reset" gave us unstable >>> > result of LMS autocalibration. >>> > >>> > Best regards, >>> > Andrey Sviyazov. >>> > >>> > >>> > >>> > 2012/7/19 sergey kostanbaev >>> >> >>> >> Which gives ~1.5khz cut-off, that's strange >>> >> >>> >> Also I'd check GPS VDD and AVDD nosies >>> >> >>> >> >>> >> On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov >>> >> wrote: >>> >>> >>> >>> 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC >>> >>> input. >>> >>> Of course I'll increase capacitance or resistance to be sure about VC >>> >>> pin. >>> >>> >>> >>> Best regards, >>> >>> Andrey Sviyazov. >>> >>> >>> >>> >>> >>> >>> >>> 2012/7/19 sergey kostanbaev >>> >>>> >>> >>>> No :) But it may cause. >>> >>>> >>> >>>> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is >>> >>>> really sensible to any noise. >>> >>>> - caused by power supply of DAC. >>> >>>> - output noise of DAC. >>> >>>> - algorithm of changing values >>> >>>> >>> >>>> At first I'd inspect VC pin at VCTXCO and try to filter it with >>> cut-off >>> >>>> frequency 1-0.1 Hz >>> >>>> >>> >>>> >>> >>>> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov >>> >>>> wrote: >>> >>>>> >>> >>>>> Sergey. >>> >>>>> Is it really so frequently (32k/s updates at 1pps reference)? >>> >>>>> >>> >>>>> Best regards, >>> >>>>> Andrey Sviyazov. >>> >>>>> >>> >>>>> >>> >>>>> >>> >>>>> 2012/7/19 sergey kostanbaev >>> >>>>>> >>> >>>>>> >>> >>>>>> >>> >>>>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov >>> >>>>>> wrote: >>> >>>>>>> >>> >>>>>>> Hi all. >>> >>>>>>> >>> >>>>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz >>> offset >>> >>>>>>> when GPS antenna used and position locked. >>> >>>>>>> This spurs begin grow up when GPS just near to lock position and >>> >>>>>>> after locking spurs stopped to grow as you can see at picture. >>> >>>>>>> If thereafter GPS disconnected then noise coming back to normal >>> plot. >>> >>>>>>> I think that it is result of 32768Hz clock in the GPS module >>> EB-230, >>> >>>>>>> but can't understant how it can impact to 26MHz clock or VCO. >>> >>>>>> >>> >>>>>> >>> >>>>>> As another idea it can be caused by continues GPS correction lead >>> to >>> >>>>>> DAC changes to the VCTXCO. >>> >>>>>> >>> >>>>>>> >>> >>>>>>> Please tell me something who know. >>> >>>>>>> >>> >>>>>>> Thomas. >>> >>>>>>> Was GPS antenna connected when noise measured like on the picture >>> >>>>>>> which you sent us (also attached here)? >>> >>>>>>> I would to know because of anomal peak near to 30kHz offset too. >>> >>>>>>> >>> >>>>>>> Best regards, >>> >>>>>>> Andrey Sviyazov. >>> >>>>>>> >>> >>>>>>> >>> >>>>>>> >>> >>>>>>> 2012/7/19 Andrey Sviyazov >>> >>>>>>>> >>> >>>>>>>> Sorry, that was meant to be sent to the mailing list :) >>> >>>>>>>> >>> >>>>>>>> Best regards, >>> >>>>>>>> Andrey Sviyazov. >>> >>>>>>>> >>> >>>>>>>> ---------- Forwarded message ---------- >>> >>>>>>>> From: Andrey Sviyazov >>> >>>>>>>> Date: 2012/7/18 >>> >>>>>>>> Subject: LMS TxLO noise >>> >>>>>>>> >>> >>>>>>>> Hi Thomas. >>> >>>>>>>> >>> >>>>>>>> Here forwarded my last e-mail with noise plots when I stopped >>> work >>> >>>>>>>> around it at first time, please see below. >>> >>>>>>>> >>> >>>>>>>> Please try to play around Tx PLL charge pump current (register >>> 0x16) >>> >>>>>>>> for better RMS phase stability. >>> >>>>>>>> I think we should reach 1 degree or below. >>> >>>>>>>> >>> >>>>>>>> Alexander gave me the second UmTRX board and after checking and >>> >>>>>>>> fixing all known hardware issues I've got roughly the same LO >>> noise plot. >>> >>>>>>>> Possible Robin had no time to fixing all of our issues, so check >>> >>>>>>>> them all please. >>> >>>>>>>> And also check please what type of TCXO installed on your board. >>> >>>>>>>> >>> >>>>>>>> Best regards, >>> >>>>>>>> Andrey Sviyazov. >>> >>>>>>>> >>> >>>>>>>> ---------- Forwarded message ---------- >>> >>>>>>>> From: Andrey Sviyazov >>> >>>>>>>> Date: 2012/4/13 >>> >>>>>>>> Subject: Re: LMS TxLO noise >>> >>>>>>>> >>> >>>>>>>> Hi all. >>> >>>>>>>> >>> >>>>>>>> There is progress with LMS PLL :) >>> >>>>>>>> Pictures are attached here. >>> >>>>>>>> t was discovered that 80 kHz spurs come from Ethernet, or rather >>> >>>>>>>> from the ET1011. >>> >>>>>>>> I unknowingly put the choke between transistor of 1V regulator >>> and >>> >>>>>>>> analog power 1V. >>> >>>>>>>> As a result, the regulator has become unstable and oscillated >>> 80 kHz >>> >>>>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>> >>>>>>>> To correct this problem L46 should be replaced by jumper on all >>> alfa >>> >>>>>>>> version PCB's. >>> >>>>>>>> >>> >>>>>>>> Also I just played with current in the PLL loop, shown on the >>> >>>>>>>> picture for clarity. >>> >>>>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 >>> in >>> >>>>>>>> the register of 0x16). >>> >>>>>>>> But, I think, for the RxPLL will be better use of the current >>> 2.4 >>> >>>>>>>> mA, because the nearest noises more important for Rx (you >>> should write 0x98 >>> >>>>>>>> in the register 0x26). >>> >>>>>>>> >>> >>>>>>>> Best regards, >>> >>>>>>>> Andrey Sviyazov. >>> >>>>>>>> >>> >>>>>>>> >>> >>>>>>> >>> >>>>>> >>> >>>>> >>> >>>> >>> >>> >>> >> >>> > >>> >>> >>> >>> -- >>> Regards, >>> Alexander Chemeris. >>> CEO, Fairwaves LLC / ??? ??????? >>> http://fairwaves.ru >>> >> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: TxLO noise at PLL_BW 10kHz.png Type: image/png Size: 55241 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: TxLO noise ICP depend at PLL_BW 10kHz.png Type: image/png Size: 56133 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: PLL 10kHz BW_top side.png Type: image/png Size: 181235 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: PLL 10kHz BW_bottom side.png Type: image/png Size: 120819 bytes Desc: not available URL: From andrey.sviyazov at fairwaves.ru Fri Jul 20 17:14:00 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Fri, 20 Jul 2012 21:14:00 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Thomas. I couldn't wait your reply and start to implement 10kHz BW of PLL. You can find here two pictures with results. First of all I found that PLL tuning algorithm doesn't work properly at low PLL BW. VCOCAP register (r0x19) should contain higher value at least for +3 units (to make CAP lower), otherwise freq's above 950MHz never locked. Note, that you should read and change register 0x19 after autotuning. Second, you can see some noise difference for the 925MHz because of used DIV=8 of the VCO, instead of DIV=4 for 942 and 960MHz. Third, you can see PLL noice dependance with the charge pump current (r0x16). On the other two pictures you can find which components have to be changed. Thomas, please make one more measure of LO noise and jitter at PLL BW=10kHz by your instrument. We need to know, is it real to reach modulation accuracy of 1.5 degrees RMS or impossible, just because of LMS PLL have bigger jitter. Best regards, Andrey Sviyazov. 2012/7/19 Andrey Sviyazov > Thomas. > I've calculate few PIF filters for PLL by the ADIsimPLL and found that RMS > phase jitter in case of 5kHz and 50kHz only 0.33 and 0.46 degrees. > It is very small difference, so are you sure that I should implement 10kHz > bandwidth filter as in USRP? > Actually it is absolutly not an problem for me to implement it, but I have > to be sure. > I've calculated it for 10kHz bandwidth, noise plot will be around > 75-80dBc/Hz @ 10kHz and 105-110 dBc/Hz @ 100kHz offset. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 Andrey Sviyazov > >> Alexander. >> I think that few pulses of LMS hardware reset (LMS_NRST-1 and LMS_NRST-2 >> pins) will be much easily than all registers checking. >> BTW, are there reset pulses after power up or not? >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/19 Alexander Chemeris >> >>> Guys, please keep track of all LMS configuration values which are not >>> set to default during power on and we'll add them to our manual >>> initialization script. >>> >>> On Thu, Jul 19, 2012 at 6:56 PM, Andrey Sviyazov >>> wrote: >>> > Sergey. >>> > I'll play around GPS power and RTC supply, thank you for your help. >>> > >>> > Thomas. >>> > About r0x16 please be sure that sometimes it isn't set to default value >>> > after power up (I saw it few times). >>> > Also I think that possible those bad "power on reset" gave us unstable >>> > result of LMS autocalibration. >>> > >>> > Best regards, >>> > Andrey Sviyazov. >>> > >>> > >>> > >>> > 2012/7/19 sergey kostanbaev >>> >> >>> >> Which gives ~1.5khz cut-off, that's strange >>> >> >>> >> Also I'd check GPS VDD and AVDD nosies >>> >> >>> >> >>> >> On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov >>> >> wrote: >>> >>> >>> >>> 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC >>> >>> input. >>> >>> Of course I'll increase capacitance or resistance to be sure about VC >>> >>> pin. >>> >>> >>> >>> Best regards, >>> >>> Andrey Sviyazov. >>> >>> >>> >>> >>> >>> >>> >>> 2012/7/19 sergey kostanbaev >>> >>>> >>> >>>> No :) But it may cause. >>> >>>> >>> >>>> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is >>> >>>> really sensible to any noise. >>> >>>> - caused by power supply of DAC. >>> >>>> - output noise of DAC. >>> >>>> - algorithm of changing values >>> >>>> >>> >>>> At first I'd inspect VC pin at VCTXCO and try to filter it with >>> cut-off >>> >>>> frequency 1-0.1 Hz >>> >>>> >>> >>>> >>> >>>> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov >>> >>>> wrote: >>> >>>>> >>> >>>>> Sergey. >>> >>>>> Is it really so frequently (32k/s updates at 1pps reference)? >>> >>>>> >>> >>>>> Best regards, >>> >>>>> Andrey Sviyazov. >>> >>>>> >>> >>>>> >>> >>>>> >>> >>>>> 2012/7/19 sergey kostanbaev >>> >>>>>> >>> >>>>>> >>> >>>>>> >>> >>>>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov >>> >>>>>> wrote: >>> >>>>>>> >>> >>>>>>> Hi all. >>> >>>>>>> >>> >>>>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz >>> offset >>> >>>>>>> when GPS antenna used and position locked. >>> >>>>>>> This spurs begin grow up when GPS just near to lock position and >>> >>>>>>> after locking spurs stopped to grow as you can see at picture. >>> >>>>>>> If thereafter GPS disconnected then noise coming back to normal >>> plot. >>> >>>>>>> I think that it is result of 32768Hz clock in the GPS module >>> EB-230, >>> >>>>>>> but can't understant how it can impact to 26MHz clock or VCO. >>> >>>>>> >>> >>>>>> >>> >>>>>> As another idea it can be caused by continues GPS correction lead >>> to >>> >>>>>> DAC changes to the VCTXCO. >>> >>>>>> >>> >>>>>>> >>> >>>>>>> Please tell me something who know. >>> >>>>>>> >>> >>>>>>> Thomas. >>> >>>>>>> Was GPS antenna connected when noise measured like on the picture >>> >>>>>>> which you sent us (also attached here)? >>> >>>>>>> I would to know because of anomal peak near to 30kHz offset too. >>> >>>>>>> >>> >>>>>>> Best regards, >>> >>>>>>> Andrey Sviyazov. >>> >>>>>>> >>> >>>>>>> >>> >>>>>>> >>> >>>>>>> 2012/7/19 Andrey Sviyazov >>> >>>>>>>> >>> >>>>>>>> Sorry, that was meant to be sent to the mailing list :) >>> >>>>>>>> >>> >>>>>>>> Best regards, >>> >>>>>>>> Andrey Sviyazov. >>> >>>>>>>> >>> >>>>>>>> ---------- Forwarded message ---------- >>> >>>>>>>> From: Andrey Sviyazov >>> >>>>>>>> Date: 2012/7/18 >>> >>>>>>>> Subject: LMS TxLO noise >>> >>>>>>>> >>> >>>>>>>> Hi Thomas. >>> >>>>>>>> >>> >>>>>>>> Here forwarded my last e-mail with noise plots when I stopped >>> work >>> >>>>>>>> around it at first time, please see below. >>> >>>>>>>> >>> >>>>>>>> Please try to play around Tx PLL charge pump current (register >>> 0x16) >>> >>>>>>>> for better RMS phase stability. >>> >>>>>>>> I think we should reach 1 degree or below. >>> >>>>>>>> >>> >>>>>>>> Alexander gave me the second UmTRX board and after checking and >>> >>>>>>>> fixing all known hardware issues I've got roughly the same LO >>> noise plot. >>> >>>>>>>> Possible Robin had no time to fixing all of our issues, so check >>> >>>>>>>> them all please. >>> >>>>>>>> And also check please what type of TCXO installed on your board. >>> >>>>>>>> >>> >>>>>>>> Best regards, >>> >>>>>>>> Andrey Sviyazov. >>> >>>>>>>> >>> >>>>>>>> ---------- Forwarded message ---------- >>> >>>>>>>> From: Andrey Sviyazov >>> >>>>>>>> Date: 2012/4/13 >>> >>>>>>>> Subject: Re: LMS TxLO noise >>> >>>>>>>> >>> >>>>>>>> Hi all. >>> >>>>>>>> >>> >>>>>>>> There is progress with LMS PLL :) >>> >>>>>>>> Pictures are attached here. >>> >>>>>>>> t was discovered that 80 kHz spurs come from Ethernet, or rather >>> >>>>>>>> from the ET1011. >>> >>>>>>>> I unknowingly put the choke between transistor of 1V regulator >>> and >>> >>>>>>>> analog power 1V. >>> >>>>>>>> As a result, the regulator has become unstable and oscillated >>> 80 kHz >>> >>>>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>> >>>>>>>> To correct this problem L46 should be replaced by jumper on all >>> alfa >>> >>>>>>>> version PCB's. >>> >>>>>>>> >>> >>>>>>>> Also I just played with current in the PLL loop, shown on the >>> >>>>>>>> picture for clarity. >>> >>>>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 >>> in >>> >>>>>>>> the register of 0x16). >>> >>>>>>>> But, I think, for the RxPLL will be better use of the current >>> 2.4 >>> >>>>>>>> mA, because the nearest noises more important for Rx (you >>> should write 0x98 >>> >>>>>>>> in the register 0x26). >>> >>>>>>>> >>> >>>>>>>> Best regards, >>> >>>>>>>> Andrey Sviyazov. >>> >>>>>>>> >>> >>>>>>>> >>> >>>>>>> >>> >>>>>> >>> >>>>> >>> >>>> >>> >>> >>> >> >>> > >>> >>> >>> >>> -- >>> Regards, >>> Alexander Chemeris. >>> CEO, Fairwaves LLC / ??? ??????? >>> http://fairwaves.ru >>> >> >> > -------------- next part -------------- An HTML attachment was scrubbed... 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Name: PLL 10kHz BW_bottom side.png Type: image/png Size: 120819 bytes Desc: not available URL: From alexander.chemeris at gmail.com Fri Jul 20 22:09:58 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 00:09:58 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Fri, Jul 20, 2012 at 10:22 PM, Thomas Tsou wrote: > There are still other calibration issues, but phase noise is probably still > a concern. You mean LO leakage and I/Q balance? Have you calibrated them? They're very easy to do - I could guide you with Skype if needed. > I also still have errors with auto calibration. Well, you haven't enabled Rx chain in LMS and thus it's reasonable that Rx-related calibration is failing. You should do "--lms-rx-enable 1" before you try to do anything with Rx. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Fri Jul 20 22:09:58 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 00:09:58 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Fri, Jul 20, 2012 at 10:22 PM, Thomas Tsou wrote: > There are still other calibration issues, but phase noise is probably still > a concern. You mean LO leakage and I/Q balance? Have you calibrated them? They're very easy to do - I could guide you with Skype if needed. > I also still have errors with auto calibration. Well, you haven't enabled Rx chain in LMS and thus it's reasonable that Rx-related calibration is failing. You should do "--lms-rx-enable 1" before you try to do anything with Rx. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From 246tnt at gmail.com Fri Jul 20 22:17:53 2012 From: 246tnt at gmail.com (Sylvain Munaut) Date: Sat, 21 Jul 2012 00:17:53 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: > 4 can 4406 measuring noise plot with log freq? To answer this: The E4406 can't do phase noise measurement directly from the interface, but there is an open source software that drives it over GPIB to do it : http://www.ke5fx.com/gpib/pn.htm AFAIK you can't do it over the network interface with the original sw, but I have hacked together a small CLU to do it under linux. If you need it, I can send it to you. Cheers, Sylvain From 246tnt at gmail.com Fri Jul 20 22:17:53 2012 From: 246tnt at gmail.com (Sylvain Munaut) Date: Sat, 21 Jul 2012 00:17:53 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: > 4 can 4406 measuring noise plot with log freq? To answer this: The E4406 can't do phase noise measurement directly from the interface, but there is an open source software that drives it over GPIB to do it : http://www.ke5fx.com/gpib/pn.htm AFAIK you can't do it over the network interface with the original sw, but I have hacked together a small CLU to do it under linux. If you need it, I can send it to you. Cheers, Sylvain From thomastsou at gmail.com Fri Jul 20 22:26:36 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Fri, 20 Jul 2012 18:26:36 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Fri, Jul 20, 2012 at 5:33 PM, Andrey Sviyazov wrote: > Hi Thomas. > > First of all thank you very much. > > And of course few questions: > 1 why you use too small input signal to the analyser? I saw -120dBc/Hz @ > 1MHz offset. No reason. That's just how I had it setup at the time. > 2 do you test LO with small CP current? I went back and forth between default 0x8c and 0x93 values, which are attached for 925 and 945 MHz. > 3 I don't see now noise peak @ 30kHz. Do you change something? There is a drop in the 30 kHz peak when the frequency is at 945 MHz instead of 925. > 4 can 4406 measuring noise plot with log freq? Answered by Sylvain. > 5 what type of modulation you use now? I mean 1 sps or 2? 4 sps with corrected pulse shape. The same configuration is below 2/5 on USRP1. Thomas -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_phs_noise_925_16_8c.PNG Type: image/png Size: 76192 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_phs_noise_925_16_93.PNG Type: image/png Size: 76039 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_phs_noise_945_16_8c.PNG Type: image/png Size: 76350 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_phs_noise_945_16_93.PNG Type: image/png Size: 75877 bytes Desc: not available URL: From thomastsou at gmail.com Fri Jul 20 22:26:36 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Fri, 20 Jul 2012 18:26:36 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Fri, Jul 20, 2012 at 5:33 PM, Andrey Sviyazov wrote: > Hi Thomas. > > First of all thank you very much. > > And of course few questions: > 1 why you use too small input signal to the analyser? I saw -120dBc/Hz @ > 1MHz offset. No reason. That's just how I had it setup at the time. > 2 do you test LO with small CP current? I went back and forth between default 0x8c and 0x93 values, which are attached for 925 and 945 MHz. > 3 I don't see now noise peak @ 30kHz. Do you change something? There is a drop in the 30 kHz peak when the frequency is at 945 MHz instead of 925. > 4 can 4406 measuring noise plot with log freq? Answered by Sylvain. > 5 what type of modulation you use now? I mean 1 sps or 2? 4 sps with corrected pulse shape. The same configuration is below 2/5 on USRP1. Thomas -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_phs_noise_925_16_8c.PNG Type: image/png Size: 76192 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_phs_noise_925_16_93.PNG Type: image/png Size: 76039 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_phs_noise_945_16_8c.PNG Type: image/png Size: 76350 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_phs_noise_945_16_93.PNG Type: image/png Size: 75877 bytes Desc: not available URL: From thomastsou at gmail.com Fri Jul 20 22:44:27 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Fri, 20 Jul 2012 18:44:27 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Fri, Jul 20, 2012 at 6:09 PM, Alexander Chemeris wrote: > On Fri, Jul 20, 2012 at 10:22 PM, Thomas Tsou wrote: >> There are still other calibration issues, but phase noise is probably still >> a concern. > > You mean LO leakage and I/Q balance? Have you calibrated them? They're > very easy to do - I could guide you with Skype if needed. LO leakage is calibrated. I/Q balance is not. Are there steps for this somewhere? I read 4.10 in the calibration guide, but I'm still not sure how to proceed. >> I also still have errors with auto calibration. > > Well, you haven't enabled Rx chain in LMS and thus it's reasonable > that Rx-related calibration is failing. You should do "--lms-rx-enable > 1" before you try to do anything with Rx. Hmm. Similar error. Thomas -------------- next part -------------- [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --lms-init [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --lms-tx-enable 1 [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --lms-rx-enable 1 [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --reg 0x34 --data 0x3e [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --pll-ref-clock 26e6 --lpf-bandwidth-code 0x0f --lms-auto-calibration LPF Tuning... DC_REGVAL = 29 LPF Bandwidth Tuning... FREQSEL=47 VCO_X=16 NINT=196 NFRACK=7743330 VOVCO[0]=2 VOVCO[1]=2 VOVCO[2]=2 VOVCO[3]=2 VOVCO[4]=2 VOVCO[5]=2 VOVCO[6]=2 VOVCO[7]=2 VOVCO[8]=2 VOVCO[9]=2 VOVCO[10]=2 VOVCO[11]=2 VOVCO[12]=2 VOVCO[13]=2 VOVCO[14]=2 VOVCO[15]=2 VOVCO[16]=2 VOVCO[17]=2 VOVCO[18]=2 VOVCO[19]=2 VOVCO[20]=2 VOVCO[21]=2 VOVCO[22]=2 VOVCO[23]=2 VOVCO[24]=2 VOVCO[25]=2 VOVCO[26]=2 VOVCO[27]=2 VOVCO[28]=2 VOVCO[29]=2 VOVCO[30]=2 VOVCO[31]=2 VOVCO[32]=2 VOVCO[33]=2 VOVCO[34]=2 VOVCO[35]=2 VOVCO[36]=2 VOVCO[37]=2 VOVCO[38]=2 VOVCO[39]=2 VOVCO[40]=2 VOVCO[41]=2 VOVCO[42]=0 Norm VOVCO[43]=0 VOVCO[44]=0 VOVCO[45]=0 VOVCO[46]=0 VOVCO[47]=0 VOVCO[48]=0 VOVCO[49]=0 VOVCO[50]=0 VOVCO[51]=0 VOVCO[52]=1 Low VOVCO[53]=1 VOVCO[54]=1 VOVCO[55]=1 VOVCO[56]=1 VOVCO[57]=1 VOVCO[58]=1 VOVCO[59]=1 VOVCO[60]=1 VOVCO[61]=1 VOVCO[62]=1 VOVCO[63]=1 START=42 STOP=51 SET=46 code = f f f RCCAL = 7 Tx LPF DC calibration... Error: DC Offset Calibration does not converge! Rx LPF DC calibration... DC_REGVAL = 63 Error: DC Offset Calibration does not converge! RxVGA2 DC calibration... DC_REGVAL = 29 Error: DC Offset Calibration does not converge! [ttsou at ovid utils (umtrx)]$ From thomastsou at gmail.com Fri Jul 20 22:44:27 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Fri, 20 Jul 2012 18:44:27 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Fri, Jul 20, 2012 at 6:09 PM, Alexander Chemeris wrote: > On Fri, Jul 20, 2012 at 10:22 PM, Thomas Tsou wrote: >> There are still other calibration issues, but phase noise is probably still >> a concern. > > You mean LO leakage and I/Q balance? Have you calibrated them? They're > very easy to do - I could guide you with Skype if needed. LO leakage is calibrated. I/Q balance is not. Are there steps for this somewhere? I read 4.10 in the calibration guide, but I'm still not sure how to proceed. >> I also still have errors with auto calibration. > > Well, you haven't enabled Rx chain in LMS and thus it's reasonable > that Rx-related calibration is failing. You should do "--lms-rx-enable > 1" before you try to do anything with Rx. Hmm. Similar error. Thomas -------------- next part -------------- [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --lms-init [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --lms-tx-enable 1 [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --lms-rx-enable 1 [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --reg 0x34 --data 0x3e [ttsou at ovid utils (umtrx)]$ ./umtrx_lms.py --lms 1 --pll-ref-clock 26e6 --lpf-bandwidth-code 0x0f --lms-auto-calibration LPF Tuning... DC_REGVAL = 29 LPF Bandwidth Tuning... FREQSEL=47 VCO_X=16 NINT=196 NFRACK=7743330 VOVCO[0]=2 VOVCO[1]=2 VOVCO[2]=2 VOVCO[3]=2 VOVCO[4]=2 VOVCO[5]=2 VOVCO[6]=2 VOVCO[7]=2 VOVCO[8]=2 VOVCO[9]=2 VOVCO[10]=2 VOVCO[11]=2 VOVCO[12]=2 VOVCO[13]=2 VOVCO[14]=2 VOVCO[15]=2 VOVCO[16]=2 VOVCO[17]=2 VOVCO[18]=2 VOVCO[19]=2 VOVCO[20]=2 VOVCO[21]=2 VOVCO[22]=2 VOVCO[23]=2 VOVCO[24]=2 VOVCO[25]=2 VOVCO[26]=2 VOVCO[27]=2 VOVCO[28]=2 VOVCO[29]=2 VOVCO[30]=2 VOVCO[31]=2 VOVCO[32]=2 VOVCO[33]=2 VOVCO[34]=2 VOVCO[35]=2 VOVCO[36]=2 VOVCO[37]=2 VOVCO[38]=2 VOVCO[39]=2 VOVCO[40]=2 VOVCO[41]=2 VOVCO[42]=0 Norm VOVCO[43]=0 VOVCO[44]=0 VOVCO[45]=0 VOVCO[46]=0 VOVCO[47]=0 VOVCO[48]=0 VOVCO[49]=0 VOVCO[50]=0 VOVCO[51]=0 VOVCO[52]=1 Low VOVCO[53]=1 VOVCO[54]=1 VOVCO[55]=1 VOVCO[56]=1 VOVCO[57]=1 VOVCO[58]=1 VOVCO[59]=1 VOVCO[60]=1 VOVCO[61]=1 VOVCO[62]=1 VOVCO[63]=1 START=42 STOP=51 SET=46 code = f f f RCCAL = 7 Tx LPF DC calibration... Error: DC Offset Calibration does not converge! Rx LPF DC calibration... DC_REGVAL = 63 Error: DC Offset Calibration does not converge! RxVGA2 DC calibration... DC_REGVAL = 29 Error: DC Offset Calibration does not converge! [ttsou at ovid utils (umtrx)]$ From thomastsou at gmail.com Fri Jul 20 22:55:42 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Fri, 20 Jul 2012 18:55:42 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Fri, Jul 20, 2012 at 6:44 PM, Thomas Tsou wrote: > On Fri, Jul 20, 2012 at 6:09 PM, Alexander Chemeris > wrote: >> Well, you haven't enabled Rx chain in LMS and thus it's reasonable >> that Rx-related calibration is failing. You should do "--lms-rx-enable >> 1" before you try to do anything with Rx. > > Hmm. Similar error. Occurs only on LMS 1. No errors when I run the same sequence on LMS 2. Thomas From thomastsou at gmail.com Fri Jul 20 22:55:42 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Fri, 20 Jul 2012 18:55:42 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Fri, Jul 20, 2012 at 6:44 PM, Thomas Tsou wrote: > On Fri, Jul 20, 2012 at 6:09 PM, Alexander Chemeris > wrote: >> Well, you haven't enabled Rx chain in LMS and thus it's reasonable >> that Rx-related calibration is failing. You should do "--lms-rx-enable >> 1" before you try to do anything with Rx. > > Hmm. Similar error. Occurs only on LMS 1. No errors when I run the same sequence on LMS 2. Thomas From thomastsou at gmail.com Fri Jul 20 23:16:39 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Fri, 20 Jul 2012 19:16:39 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Fri, Jul 20, 2012 at 6:55 PM, Thomas Tsou wrote: > On Fri, Jul 20, 2012 at 6:44 PM, Thomas Tsou wrote: >> On Fri, Jul 20, 2012 at 6:09 PM, Alexander Chemeris >> wrote: >>> Well, you haven't enabled Rx chain in LMS and thus it's reasonable >>> that Rx-related calibration is failing. You should do "--lms-rx-enable >>> 1" before you try to do anything with Rx. >> >> Hmm. Similar error. > > Occurs only on LMS 1. No errors when I run the same sequence on LMS 2. Also, I didn't realize that TX LPF DC calibration actually completed in the first error log - it usually doesn't. Sorry for the confusion. I believe it is similar to the tuning issue I'm seeing. If I keep power cycling then TX calibration will eventually work. Still no luck with Rx auto-calibration though. Thomas From thomastsou at gmail.com Fri Jul 20 23:16:39 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Fri, 20 Jul 2012 19:16:39 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Fri, Jul 20, 2012 at 6:55 PM, Thomas Tsou wrote: > On Fri, Jul 20, 2012 at 6:44 PM, Thomas Tsou wrote: >> On Fri, Jul 20, 2012 at 6:09 PM, Alexander Chemeris >> wrote: >>> Well, you haven't enabled Rx chain in LMS and thus it's reasonable >>> that Rx-related calibration is failing. You should do "--lms-rx-enable >>> 1" before you try to do anything with Rx. >> >> Hmm. Similar error. > > Occurs only on LMS 1. No errors when I run the same sequence on LMS 2. Also, I didn't realize that TX LPF DC calibration actually completed in the first error log - it usually doesn't. Sorry for the confusion. I believe it is similar to the tuning issue I'm seeing. If I keep power cycling then TX calibration will eventually work. Still no luck with Rx auto-calibration though. Thomas From thomastsou at gmail.com Sat Jul 21 05:03:51 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Sat, 21 Jul 2012 01:03:51 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: I tried calibrating LO leakage cancellation again and found out that it wasn't calibrated enough. The settings are very sensitive and increasing the I and Q shifts by one made a large difference on the E4406. The RSA seems to compensate, though, because the same changes don't affect it at all. I also tried some different frequencies. At the not useful frequency of 240 MHz, we are not far from target values. At 945 MHz, it is better than before, but still too high. The 1900 MHz band is not so good. Attached measurements are all at 4 sps, with the updated linear pulse from yesterday. I played more with the CP setting; the value of 0x93 provided the best measurements. Thomas -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_240mhz.bmp Type: image/bmp Size: 41514 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_945mhz.bmp Type: image/bmp Size: 41312 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_1950mhz.bmp Type: image/bmp Size: 41546 bytes Desc: not available URL: From thomastsou at gmail.com Sat Jul 21 05:03:51 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Sat, 21 Jul 2012 01:03:51 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: I tried calibrating LO leakage cancellation again and found out that it wasn't calibrated enough. The settings are very sensitive and increasing the I and Q shifts by one made a large difference on the E4406. The RSA seems to compensate, though, because the same changes don't affect it at all. I also tried some different frequencies. At the not useful frequency of 240 MHz, we are not far from target values. At 945 MHz, it is better than before, but still too high. The 1900 MHz band is not so good. Attached measurements are all at 4 sps, with the updated linear pulse from yesterday. I played more with the CP setting; the value of 0x93 provided the best measurements. Thomas -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_240mhz.bmp Type: image/bmp Size: 41514 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_945mhz.bmp Type: image/bmp Size: 41312 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_1950mhz.bmp Type: image/bmp Size: 41546 bytes Desc: not available URL: From alexander.chemeris at gmail.com Sat Jul 21 07:51:06 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 09:51:06 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sat, Jul 21, 2012 at 7:03 AM, Thomas Tsou wrote: > I tried calibrating LO leakage cancellation again and found out that > it wasn't calibrated enough. The settings are very sensitive and > increasing the I and Q shifts by one made a large difference on the > E4406. This is my experience as well. Near the optimum point even change of calibration registers by 1 makes big difference. When you're far off, a change of a calibration register could be almost unnoticeable. I've started adding notes about LMS calibration here: http://code.google.com/p/umtrx/wiki/LMS6002DCalibration Please write down there all useful notes about all types of calibration we're doing. > The RSA seems to compensate, though, because the same changes > don't affect it at all. How could it compensate? For RSA it should look like a genuine sine signal. > I also tried some different frequencies. At the not useful frequency > of 240 MHz, we are not far from target values. At 945 MHz, it is > better than before, but still too high. The 1900 MHz band is not so > good. Well, we're more interested in GSM900, but this clearly shows that there is an issue with the LMS PLL noise. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sat Jul 21 07:51:06 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 09:51:06 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sat, Jul 21, 2012 at 7:03 AM, Thomas Tsou wrote: > I tried calibrating LO leakage cancellation again and found out that > it wasn't calibrated enough. The settings are very sensitive and > increasing the I and Q shifts by one made a large difference on the > E4406. This is my experience as well. Near the optimum point even change of calibration registers by 1 makes big difference. When you're far off, a change of a calibration register could be almost unnoticeable. I've started adding notes about LMS calibration here: http://code.google.com/p/umtrx/wiki/LMS6002DCalibration Please write down there all useful notes about all types of calibration we're doing. > The RSA seems to compensate, though, because the same changes > don't affect it at all. How could it compensate? For RSA it should look like a genuine sine signal. > I also tried some different frequencies. At the not useful frequency > of 240 MHz, we are not far from target values. At 945 MHz, it is > better than before, but still too high. The 1900 MHz band is not so > good. Well, we're more interested in GSM900, but this clearly shows that there is an issue with the LMS PLL noise. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sat Jul 21 07:56:38 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 09:56:38 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sat, Jul 21, 2012 at 12:55 AM, Thomas Tsou wrote: > On Fri, Jul 20, 2012 at 6:44 PM, Thomas Tsou wrote: >> On Fri, Jul 20, 2012 at 6:09 PM, Alexander Chemeris >> wrote: >>> Well, you haven't enabled Rx chain in LMS and thus it's reasonable >>> that Rx-related calibration is failing. You should do "--lms-rx-enable >>> 1" before you try to do anything with Rx. >> >> Hmm. Similar error. > > Occurs only on LMS 1. No errors when I run the same sequence on LMS 2. Could you send me a register dump of both LMS'es with "--dump" to see whether there are any significant differences between register settings of two? I need dumps before and after every execution of 'umtrx_lms.py'. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sat Jul 21 07:56:38 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 09:56:38 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sat, Jul 21, 2012 at 12:55 AM, Thomas Tsou wrote: > On Fri, Jul 20, 2012 at 6:44 PM, Thomas Tsou wrote: >> On Fri, Jul 20, 2012 at 6:09 PM, Alexander Chemeris >> wrote: >>> Well, you haven't enabled Rx chain in LMS and thus it's reasonable >>> that Rx-related calibration is failing. You should do "--lms-rx-enable >>> 1" before you try to do anything with Rx. >> >> Hmm. Similar error. > > Occurs only on LMS 1. No errors when I run the same sequence on LMS 2. Could you send me a register dump of both LMS'es with "--dump" to see whether there are any significant differences between register settings of two? I need dumps before and after every execution of 'umtrx_lms.py'. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sat Jul 21 07:58:49 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 09:58:49 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sat, Jul 21, 2012 at 1:16 AM, Thomas Tsou wrote: > On Fri, Jul 20, 2012 at 6:55 PM, Thomas Tsou wrote: >> On Fri, Jul 20, 2012 at 6:44 PM, Thomas Tsou wrote: >>> On Fri, Jul 20, 2012 at 6:09 PM, Alexander Chemeris >>> wrote: >>>> Well, you haven't enabled Rx chain in LMS and thus it's reasonable >>>> that Rx-related calibration is failing. You should do "--lms-rx-enable >>>> 1" before you try to do anything with Rx. >>> >>> Hmm. Similar error. >> >> Occurs only on LMS 1. No errors when I run the same sequence on LMS 2. > > Also, I didn't realize that TX LPF DC calibration actually completed > in the first error log - it usually doesn't. Sorry for the confusion. > I believe it is similar to the tuning issue I'm seeing. Send me logs with a failed calibration as well, please - with register dumps as I described earlier. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sat Jul 21 07:58:49 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 09:58:49 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sat, Jul 21, 2012 at 1:16 AM, Thomas Tsou wrote: > On Fri, Jul 20, 2012 at 6:55 PM, Thomas Tsou wrote: >> On Fri, Jul 20, 2012 at 6:44 PM, Thomas Tsou wrote: >>> On Fri, Jul 20, 2012 at 6:09 PM, Alexander Chemeris >>> wrote: >>>> Well, you haven't enabled Rx chain in LMS and thus it's reasonable >>>> that Rx-related calibration is failing. You should do "--lms-rx-enable >>>> 1" before you try to do anything with Rx. >>> >>> Hmm. Similar error. >> >> Occurs only on LMS 1. No errors when I run the same sequence on LMS 2. > > Also, I didn't realize that TX LPF DC calibration actually completed > in the first error log - it usually doesn't. Sorry for the confusion. > I believe it is similar to the tuning issue I'm seeing. Send me logs with a failed calibration as well, please - with register dumps as I described earlier. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sat Jul 21 08:24:20 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 10:24:20 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sat, Jul 21, 2012 at 9:56 AM, Alexander Chemeris wrote: > On Sat, Jul 21, 2012 at 12:55 AM, Thomas Tsou wrote: >> On Fri, Jul 20, 2012 at 6:44 PM, Thomas Tsou wrote: >>> On Fri, Jul 20, 2012 at 6:09 PM, Alexander Chemeris >>> wrote: >>>> Well, you haven't enabled Rx chain in LMS and thus it's reasonable >>>> that Rx-related calibration is failing. You should do "--lms-rx-enable >>>> 1" before you try to do anything with Rx. >>> >>> Hmm. Similar error. >> >> Occurs only on LMS 1. No errors when I run the same sequence on LMS 2. > > Could you send me a register dump of both LMS'es with "--dump" to see > whether there are any significant differences between register > settings of two? I need dumps before and after every execution of > 'umtrx_lms.py'. Also, could you do this all with the attached patch which adds verbose debug? -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx-lms-control-debug.diff Type: application/octet-stream Size: 674 bytes Desc: not available URL: From alexander.chemeris at gmail.com Sat Jul 21 08:44:34 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 10:44:34 +0200 Subject: Attachment size Message-ID: Hi all, I've set maximum message size for this mailing list to 1Mb. This means that you can't send big files or images to this mailing list. If you need to do so - upload files to some external server and provide a link. Project members could use our project hosting, others could upload to some other public services. At the same time limitation of 1Mb should be big enough to allow you to post screenshots of your measurements, schematics pictures, etc. Please make sure that you send big files as an attachments, even if they are textual. Subscribers (myself included) sometimes work from GPRS/EDGE connections and downloading huge e-mails is a true pain. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sat Jul 21 11:27:47 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 13:27:47 +0200 Subject: UmTRX dual-channel Rx In-Reply-To: References: Message-ID: Compiled FPGA bitstreams: http://people.osmocom.org/ipse/umtrx/fpga_bitsream/2012-07-20-523546e/ On Fri, Jul 20, 2012 at 9:31 PM, Alexander Chemeris wrote: > Andrew, thank you! > Could you send me compiled bitstreams? I'll put them to the server for > download. > > Sent from my Android device. > > -- > Regards, > Alexander Chemeris > CEO, Fairwaves LLC > http://fairwaves.ru > > 20.07.2012 23:28 ???????????? "Andrew Karpenkov" > ???????: > >> Hi all, >> >> I added control logic for diversity switches into fpga part of project. >> Now you can manage them by setting the appropriate values in registers >> sr_divsw1 (180 0 adress in decimal) and sr_divsw2 (180 1 address in >> decimal). But I'm not tested this options yet. The following Monday I plan >> to do it. >> All changes are availible in akarpenkov/dual-channel branch at github >> repository. >> >> Regards, >> Andrew Karpenkov >> >> >> 2012/7/19 Alexander Chemeris >>> >>> Thanks. Looking forward for it. >>> >>> On Thu, Jul 19, 2012 at 2:42 PM, Andrew Karpenkov >>> wrote: >>> > Yes, I can add this option. I'll try to do it, and tomorrow make >>> > changes at >>> > github. >>> > >>> > Regards, >>> > Andrew Karpenkov >>> > >>> > Sent from my Android device. >>> > >>> > 19.07.2012 14:29 ???????????? "Alexander Chemeris" >>> > ???????: >>> > >>> >> On Thu, Jul 19, 2012 at 1:33 PM, Andrey Sviyazov >>> >> wrote: >>> >> > Andrew Karpenkov, would you please to make this kind changes, until >>> >> > DIVSW >>> >> > will controled by host? >>> >> >>> >> That's an interesting question. Andrey Karpenkov - is there a way to >>> >> control them from ZPU? Some config register? >>> >> >>> >> >>> >> -- >>> >> Regards, >>> >> Alexander Chemeris. >>> >> CEO, Fairwaves LLC / ??? ??????? >>> >> http://fairwaves.ru >>> >>> >>> >>> -- >>> Regards, >>> Alexander Chemeris. >>> CEO, Fairwaves LLC / ??? ??????? >>> http://fairwaves.ru >> >> > -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From s.milenkovic at limemicro.com Sat Jul 21 14:33:27 2012 From: s.milenkovic at limemicro.com (Srdjan Milenkovic) Date: Sat, 21 Jul 2012 15:33:27 +0100 Subject: Improving LMS6002 phase noise Message-ID: <500ABDB7.40001@limemicro.com> Hi all, As far as I am aware, you are currently discussing how to improve LMS6002 PLL phase noise. Below are some inputs from my side which may help. Apart from playing with PLL registers we have two additional options. 1. Use clean TCXCO which provides 4 times higher reference followed by divide by 4 to generate PLL reference clock. Recently, we experimented with 30.72*4 MHz TCXCO. Dividing its output by 4 before going into LMS chip we have got improvement of 6dB in phase noise plateau region. 2. Current PLL loop filter has been designed to cover the whole LMS frequency range hence using kind of mid value for Kvco. We can customize the loop filter for a particular band. To do that we need to know frequency range China Mobile is looking for and reference clock you want to use (26MHz, 26*4/4MHz, ...). Please note that PLL reference clock does not need to be the same as system clock i.e. we can also use 30.72MHz, 30.72*4/4MHz etc. Best regards, Srdjan -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Sat Jul 21 15:28:51 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 17:28:51 +0200 Subject: Improving LMS6002 phase noise In-Reply-To: <500ABDB7.40001@limemicro.com> References: <500ABDB7.40001@limemicro.com> Message-ID: Hi Srdjan, On Sat, Jul 21, 2012 at 4:33 PM, Srdjan Milenkovic wrote: > Hi all, > > As far as I am aware, you are currently discussing how to improve LMS6002 > PLL phase noise. Below are some inputs from my side which may help. Yes, here are some pictures of phase noise we have at UmTRX right now: http://lists.osmocom.org/pipermail/umtrx/2012-July/000030.html It looks like they're 5-12dB higher then data I saw in your temperature measurement report. First thought is that this could be due to a clock source. Did you use your EVB board for those measurements? > Apart from playing with PLL registers we have two additional options. > > 1. Use clean TCXCO which provides 4 times higher reference followed by > divide by 4 to generate PLL reference clock. Recently, we experimented with > 30.72*4 MHz TCXCO. Dividing its output by 4 before going into LMS chip we > have got improvement of 6dB in phase noise plateau region. > > 2. Current PLL loop filter has been designed to cover the whole LMS > frequency range hence using kind of mid value for Kvco. We can customize the > loop filter for a particular band. Well, we're working with GSM and it has only four main bands: GSM-850: 824.2?849.2 UL / 869.2?894.2 DL E-GSM 900: 880.0?915.0 UL / 925.0?960.0 DL DCS-1800: 1,710.2?1,784.8 UL / 1,805.2?1,879.8 DL PCS-1900: 1,850.2?1,909.8 UL / 1,930.2?1,989.8 DL It would be great if we could optimize for the use in these bands -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sat Jul 21 16:09:12 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 18:09:12 +0200 Subject: Testing reception Message-ID: Andrey Sviyazov, You wanted to know how to plot received signal under Windows without installing Matlab or something as big and as expensive. Dmitri Stolnikov recommended to use a free version of Signals Analyzer software which should be very powerful. You could download it as "SA free" here: http://signals.radioscanner.ru/info/item1/ Dmitri says that the free version of SA could only import .wav files, so you will need to convert raw files into .wav files. My preferred way to do this is to use 'sox' command line utility like that: sox -r 270833 -e signed -b 16 -c 2 record.cfile record.wav Windows binaries of 'sox' is available from the official web-site: http://sox.sourceforge.net/ -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sat Jul 21 16:17:07 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 18:17:07 +0200 Subject: Running OpenBTS with UmTRX Message-ID: Hi Thomas, Could you hack together a quick guide how to run OpenBTS with UmTRX at the wiki? http://code.google.com/p/umtrx/wiki/RunningOpenBTS This should basically include which branch to use, what patches to apply (if any), and a script for umtrx_lms.py to tune LMS to the correct frequency. I was meaning to write this for about a week, but turns out it's very hard to allocate enough time to do that accurately. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sat Jul 21 20:43:27 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 22:43:27 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sat, Jul 21, 2012 at 12:44 AM, Thomas Tsou wrote: > On Fri, Jul 20, 2012 at 6:09 PM, Alexander Chemeris > wrote: >> On Fri, Jul 20, 2012 at 10:22 PM, Thomas Tsou wrote: >>> I also still have errors with auto calibration. >> >> Well, you haven't enabled Rx chain in LMS and thus it's reasonable >> that Rx-related calibration is failing. You should do "--lms-rx-enable >> 1" before you try to do anything with Rx. > > Hmm. Similar error. Hum. I just realized that we set register 0x09 to 0x80 in lms_init(), which means we set RXOUTSW to 1 and pins 113-116 of the chip are connected directly to the ADC. While this should not make any difference in theory, it's better to set this register to 0x00 on init to avoid any external interference. One more interesting find is that EVB Quick Starter Manual recommends to power down SPI blocks inside of the chip if they're not used (see below). Could you try to set 0x09 register to 0x00 after the tuning and check whether it affects phase noise? Clock Buffers control ----------------------------- Enable pins turn the internal clock buffers on and off. These should be enabled when control of the device is needed, however during operation SPI clocks which are not being used should be disabled to reduce the risk of SPI clock spurious. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sat Jul 21 20:48:43 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 22:48:43 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Andrew, On Thu, Jul 19, 2012 at 5:33 PM, Andrey Sviyazov wrote: > I think that few pulses of LMS hardware reset (LMS_NRST-1 and LMS_NRST-2 > pins) will be much easily than all registers checking. > BTW, are there reset pulses after power up or not? Do we pulse those reset pins on a hardware reset? I think we should have a way to perform this reset from software as well. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sat Jul 21 20:53:58 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 22:53:58 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sat, Jul 21, 2012 at 10:43 PM, Alexander Chemeris wrote: > On Sat, Jul 21, 2012 at 12:44 AM, Thomas Tsou wrote: >> On Fri, Jul 20, 2012 at 6:09 PM, Alexander Chemeris >> wrote: >>> On Fri, Jul 20, 2012 at 10:22 PM, Thomas Tsou wrote: >>>> I also still have errors with auto calibration. >>> >>> Well, you haven't enabled Rx chain in LMS and thus it's reasonable >>> that Rx-related calibration is failing. You should do "--lms-rx-enable >>> 1" before you try to do anything with Rx. >> >> Hmm. Similar error. > > Hum. I just realized that we set register 0x09 to 0x80 in lms_init(), > which means we set RXOUTSW to 1 and pins 113-116 of the chip are > connected directly to the ADC. While this should not make any > difference in theory, it's better to set this register to 0x00 on init > to avoid any external interference. Note, that I've checked in this change and now 0x09 is initialized to 0x00 in the fairwaves/umtrx branch. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sat Jul 21 21:57:39 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 21 Jul 2012 23:57:39 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sat, Jul 21, 2012 at 12:44 AM, Thomas Tsou wrote: > On Fri, Jul 20, 2012 at 6:09 PM, Alexander Chemeris > wrote: >> On Fri, Jul 20, 2012 at 10:22 PM, Thomas Tsou wrote: >>> There are still other calibration issues, but phase noise is probably still >>> a concern. >> >> You mean LO leakage and I/Q balance? Have you calibrated them? They're >> very easy to do - I could guide you with Skype if needed. > > LO leakage is calibrated. I/Q balance is not. Are there steps for this > somewhere? I read 4.10 in the calibration guide, but I'm still not > sure how to proceed. I've started documenting this at the wiki: http://code.google.com/p/umtrx/wiki/LMS6002DCalibration#Tx_I/Q_balance_calibration Is that a good enough description for you? Note, that FPGA registers which control I/Q imbalance compensation has been changed in the commit which introduced dual-channel Tx: https://github.com/chemeris/UHD-Fairwaves/commit/3d80d881d82e93ed39e83f72d5ef5fac4f8ea56e Host side hasn't been updated to accommodate those register changes yet. I would appreciate if you could do that. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From thomastsou at gmail.com Sun Jul 22 04:40:58 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Sun, 22 Jul 2012 00:40:58 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sat, Jul 21, 2012 at 5:57 PM, Alexander Chemeris wrote: > I've started documenting this at the wiki: > http://code.google.com/p/umtrx/wiki/LMS6002DCalibration#Tx_I/Q_balance_calibration > Is that a good enough description for you? Added: - IQ balance correction - Laurent C1 pulse We are below the target threshold. Thomas -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_945mhz_3.bmp Type: image/bmp Size: 36796 bytes Desc: not available URL: From alexander.chemeris at gmail.com Sun Jul 22 04:59:53 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sun, 22 Jul 2012 08:59:53 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sun, Jul 22, 2012 at 6:40 AM, Thomas Tsou wrote: > On Sat, Jul 21, 2012 at 5:57 PM, Alexander Chemeris > wrote: >> I've started documenting this at the wiki: >> http://code.google.com/p/umtrx/wiki/LMS6002DCalibration#Tx_I/Q_balance_calibration >> Is that a good enough description for you? > > Added: > > - IQ balance correction > - Laurent C1 pulse > > We are below the target threshold. Great achievement! Is it consistent over the whole 900 band, i.e. is that the worst case? I guess in 1800 band we're above the threshold yet. Could you measure by how much we're off there? -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From s.milenkovic at limemicro.com Sun Jul 22 11:11:55 2012 From: s.milenkovic at limemicro.com (Srdjan Milenkovic) Date: Sun, 22 Jul 2012 12:11:55 +0100 Subject: Improving LMS6002 phase noise In-Reply-To: References: <500ABDB7.40001@limemicro.com> Message-ID: <500BDFFB.7050806@limemicro.com> On 21/07/2012 16:28, Alexander Chemeris wrote: > Hi Srdjan, > > On Sat, Jul 21, 2012 at 4:33 PM, Srdjan Milenkovic > wrote: >> Hi all, >> >> As far as I am aware, you are currently discussing how to improve LMS6002 >> PLL phase noise. Below are some inputs from my side which may help. > Yes, here are some pictures of phase noise we have at UmTRX right now: > http://lists.osmocom.org/pipermail/umtrx/2012-July/000030.html > > It looks like they're 5-12dB higher then data I saw in your > temperature measurement report. First thought is that this could be > due to a clock source. Did you use your EVB board for those > measurements? Yes, we used Lime EVB, 30.72MHz TCXCO. However, using 26MHz instead of 30.72MHz TCXCO should not affect phase noise so much (5-12dB). Do you have an alternative 26MHz TCXCO with better PN? As you quite rightly mentioned, you are probably limited by TCXCO PN at the moment. > >> Apart from playing with PLL registers we have two additional options. >> >> 1. Use clean TCXCO which provides 4 times higher reference followed by >> divide by 4 to generate PLL reference clock. Recently, we experimented with >> 30.72*4 MHz TCXCO. Dividing its output by 4 before going into LMS chip we >> have got improvement of 6dB in phase noise plateau region. >> >> 2. Current PLL loop filter has been designed to cover the whole LMS >> frequency range hence using kind of mid value for Kvco. We can customize the >> loop filter for a particular band. > Well, we're working with GSM and it has only four main bands: > GSM-850: 824.2?849.2 UL / 869.2?894.2 DL > E-GSM 900: 880.0?915.0 UL / 925.0?960.0 DL > DCS-1800: 1,710.2?1,784.8 UL / 1,805.2?1,879.8 DL > PCS-1900: 1,850.2?1,909.8 UL / 1,930.2?1,989.8 DL > > It would be great if we could optimize for the use in these bands Let us first try to recover 5-12dB PN as mentioned above. Redesigning loop filter will not help at all if we are limited by TCXCO. From alexander.chemeris at gmail.com Sun Jul 22 11:16:43 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sun, 22 Jul 2012 15:16:43 +0400 Subject: Improving LMS6002 phase noise In-Reply-To: <500BDFFB.7050806@limemicro.com> References: <500ABDB7.40001@limemicro.com> <500BDFFB.7050806@limemicro.com> Message-ID: On Sun, Jul 22, 2012 at 3:11 PM, Srdjan Milenkovic wrote: > On 21/07/2012 16:28, Alexander Chemeris wrote: >> >> Hi Srdjan, >> >> On Sat, Jul 21, 2012 at 4:33 PM, Srdjan Milenkovic >> wrote: >>> >>> Hi all, >>> >>> As far as I am aware, you are currently discussing how to improve LMS6002 >>> PLL phase noise. Below are some inputs from my side which may help. >> >> Yes, here are some pictures of phase noise we have at UmTRX right now: >> http://lists.osmocom.org/pipermail/umtrx/2012-July/000030.html >> >> It looks like they're 5-12dB higher then data I saw in your >> temperature measurement report. First thought is that this could be >> due to a clock source. Did you use your EVB board for those >> measurements? > > Yes, we used Lime EVB, 30.72MHz TCXCO. However, using 26MHz instead of > 30.72MHz TCXCO should not affect phase noise so much (5-12dB). Do you have > an alternative 26MHz TCXCO with better PN? As you quite rightly mentioned, > you are probably limited by TCXCO PN at the moment. We'll look for a one. UmTRX has Clock In connector, so it should not be an issue to feed it with an other clock source. Btw, for everyone's reference, the aforementioned document with LMS performance measurements is now published here: https://github.com/chemeris/lms6002-documentation/blob/master/LMS6002D-Temperature%20testing%20July%202011.pdf -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From andrey.sviyazov at fairwaves.ru Sun Jul 22 14:12:40 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Sun, 22 Jul 2012 18:12:40 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Thomas. It is very good new. Please let us know more information how you wins! I mean which PLL filter, ICP and other LMS paremeters do you use or its done by just only IQ balance correction and Laurent C1 pulse and all other by default? Best regards, Andrey Sviyazov. 2012/7/22 Thomas Tsou > On Sat, Jul 21, 2012 at 5:57 PM, Alexander Chemeris > wrote: > > I've started documenting this at the wiki: > > > http://code.google.com/p/umtrx/wiki/LMS6002DCalibration#Tx_I/Q_balance_calibration > > Is that a good enough description for you? > > Added: > > - IQ balance correction > - Laurent C1 pulse > > We are below the target threshold. > > Thomas > -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Sun Jul 22 14:16:56 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sun, 22 Jul 2012 18:16:56 +0400 Subject: Improving LMS6002 phase noise In-Reply-To: <500BDFFB.7050806@limemicro.com> References: <500ABDB7.40001@limemicro.com> <500BDFFB.7050806@limemicro.com> Message-ID: On Sun, Jul 22, 2012 at 3:11 PM, Srdjan Milenkovic wrote: > On 21/07/2012 16:28, Alexander Chemeris wrote: >> >> Hi Srdjan, >> >> On Sat, Jul 21, 2012 at 4:33 PM, Srdjan Milenkovic >> wrote: >>> >>> Hi all, >>> >>> As far as I am aware, you are currently discussing how to improve LMS6002 >>> PLL phase noise. Below are some inputs from my side which may help. >> >> Yes, here are some pictures of phase noise we have at UmTRX right now: >> http://lists.osmocom.org/pipermail/umtrx/2012-July/000030.html >> >> It looks like they're 5-12dB higher then data I saw in your >> temperature measurement report. First thought is that this could be >> due to a clock source. Did you use your EVB board for those >> measurements? > > Yes, we used Lime EVB, 30.72MHz TCXCO. However, using 26MHz instead of > 30.72MHz TCXCO should not affect phase noise so much (5-12dB). Do you have > an alternative 26MHz TCXCO with better PN? As you quite rightly mentioned, > you are probably limited by TCXCO PN at the moment. Could you please share LMS configuration you used during this test, so we could re-create it locally with the EVB we have. A full register dump of the chip would be ideal. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From s.milenkovic at limemicro.com Sun Jul 22 15:38:47 2012 From: s.milenkovic at limemicro.com (Srdjan Milenkovic) Date: Sun, 22 Jul 2012 16:38:47 +0100 Subject: Improving LMS6002 phase noise In-Reply-To: References: <500ABDB7.40001@limemicro.com> <500BDFFB.7050806@limemicro.com> Message-ID: <500C1E87.2090106@limemicro.com> Hi Alexander, We usually do chip tests as close to the defaults as possible. All the changes from the defaults which lead to significant improvement would be recorded and shared with customers. Below is test description. I do not see any major changes from the defaults. We do not have register dump. However, Lime GUI project file used in this experiment is attached. You can use GUI File->Open Project option to import it. I see Ichp and Ichp offset currents are different from defaults but these still do not justify 5-12dB worse PN in your reports. You can give it a try though before changing TCXCO. Best regards, Srdjan *Test Description:* * DC MAX applied through analogue inputs, DACs off * TXVGA1 and TXVGA2 at max gain * Loop filter redesigned for 100kHz loop bandwidth and 40MHz reference * Icp and Icp offset optimized at 25 deg. Same set up used at all other temperatures * Cap code and VCO picked up by PLL tune routine * Span 1kHz to 10 MHz * Measure integrated PN * Measure PN at decade frequency points * Measure LO level * Record VCOCAP code * Using Tune log, record VCOCAP code range * Record VCO and FF divider Dr Srdjan Milenkovic On 22/07/2012 15:16, Alexander Chemeris wrote: > On Sun, Jul 22, 2012 at 3:11 PM, Srdjan Milenkovic > wrote: >> On 21/07/2012 16:28, Alexander Chemeris wrote: >>> Hi Srdjan, >>> >>> On Sat, Jul 21, 2012 at 4:33 PM, Srdjan Milenkovic >>> wrote: >>>> Hi all, >>>> >>>> As far as I am aware, you are currently discussing how to improve LMS6002 >>>> PLL phase noise. Below are some inputs from my side which may help. >>> Yes, here are some pictures of phase noise we have at UmTRX right now: >>> http://lists.osmocom.org/pipermail/umtrx/2012-July/000030.html >>> >>> It looks like they're 5-12dB higher then data I saw in your >>> temperature measurement report. First thought is that this could be >>> due to a clock source. Did you use your EVB board for those >>> measurements? >> Yes, we used Lime EVB, 30.72MHz TCXCO. However, using 26MHz instead of >> 30.72MHz TCXCO should not affect phase noise so much (5-12dB). Do you have >> an alternative 26MHz TCXCO with better PN? As you quite rightly mentioned, >> you are probably limited by TCXCO PN at the moment. > Could you please share LMS configuration you used during this test, so > we could re-create it locally with the EVB we have. A full register > dump of the chip would be ideal. > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- [BNDS] I=1 II=1 III=1 IV=1 V=1 VI=1 VII=1 VIII=1 IX=1 X=1 XI=1 XII=1 XIII=1 XIV=1 [0] cmbDCCalAddr=0 cmbCalVal=31 LPF_dco_CAL=31 rgrDecode=0 rgrDsmRst=1 chbPwrTopMods=1 chbPwrSoftTx=1 chbPwrSoftRx=0 rgrSpiMode=1 rgrCLKSEL_LPFCAL=1 chbPD_CLKLPFCAL=1 chkLpfCalEnEnf=0 chkLpfCalRst=1 chkLpfCalEn=0 cmbLpfCalCode=0 cmbLpfCalBw=0 chbRxTestModeEn=0 rgrBBLB=0 rgrRFLB=0 rgrRXOUTSW=1 chbSpiClkBuf_0=1 chbSpiClkBuf_1=0 chbSpiClkBuf_2=0 chbSpiClkBuf_3=0 chbSpiClkBuf_4=0 chbSpiClkBuf_5=0 chbSpiClkBuf_6=0 rgrFDDTDD=0 rgrTDDMOD=0 chbPDXCOBUF=0 chbSLFBXCOBUF=1 chbBYPXCOBUF=0 chbPwrLpfCal=1 chbPwrRfLbsw=0 [3] cmbDCCalAddr=1 cmbCalVal=31 LPF_dco_I=31 LPF_dco_Q=31 cmbLpfBw=0 chbPwrLpfMods=1 rgrDecode=0 rgrLpfByp=0 cmbDCOffset=12 chbTX_DACBUF_EN=1 cmbRcCal=3 chbPwrDCCmpr=1 chbPwrDCDac=1 chbPwrDCRef=1 chbPwrLpf=1 [5] cmbDCCalAddr=0 cmbCalVal=31 LPF_dco_I=31 LPF_dco_Q=31 cmbLpfBw=0 chbPwrLpfMods=1 rgrDecode=0 rgrLpfByp=0 cmbDCOffset=12 chbTX_DACBUF_EN=0 cmbRcCal=3 chbPwrDCCmpr=1 chbPwrDCDac=1 chbPwrDCRef=1 chbPwrLpf=1 [4] chbPwrTxRfMods=1 rgrDecode=0 cmbVga1G_u=31 cmbVga1DcI=128 cmbVga1DcQ=128 rgrPA=2 chbPD_DRVAUX=1 chbPD_PKDET=1 cmbVga2G_u=25 cmbENVD=0 cmbENVD2=0 cmbPKDBW=0 rgrLOOPBBEN=0 chbFST_PKDET=0 chbFST_TXHFBIAS=0 cmbICT_TXLOBUF=4 cmbVBCAS_TXDRV=0 cmbICT_TXMIX=12 cmbICT_TXDRV=12 chbPwrVga1_I=1 chbPwrVga1_Q=1 chbPD_TXDRV=0 chbPD_TXLOBUF=0 chbPwrVga2=0 cmbVga1G_t=21 cmbVga2G_t=0 [6] cmbDCCalAddr=0 cmbCalVal=31 dc_ref=31 dc2a_I=31 dc2a_Q=31 dc2b_I=31 dc2b_Q=31 cmbVCM=12 chbPwrVGA2Mods=1 rgrDecode=0 cmbVga2G_u=1 chbPwrDCCurrR=1 chbPwrDCDACB=1 chbPwrDCCmpB=1 chbPwrDCDACA=1 chbPwrDCCmpA=1 chbPwrBG=1 chbPwrBypAB=1 chbPwrBypB=1 chbPwrBypA=1 chbPwrCurrRef=1 cmbVga2GB_t=0 cmbVga2GA_t=1 [7] rgrDecode=0 chbPwrRxFeMods=1 cmbIN1SEL_MIX_RXFE=1 cmbDCOFF_I_RXFE=63 chkINLOAD_LNA_RXFE=1 cmbDCOFF_Q_RXFE=63 chkXLOAD_LNA_RXFE=0 cmbIP2TRIM_I_RXFE=63 cmbIP2TRIM_Q_RXFE=63 cmbG_LNA_RXFE=2 cmbLNASEL_RXFE=1 cmbCBE_LNA_RXFE=0 cmbRFB_TIA_RXFE=120 cmbCFB_TIA_RXFE=0 cmbRDLEXT_LNA_RXFE=28 cmbRDLINT_LNA_RXFE=55 cmbICT_MIX_RXFE=7 cmbICT_LNA_RXFE=7 cmbICT_TIA_RXFE=7 cmbICT_MXLOB_RXFE=7 cmbLOBN_MIX_RXFE=3 chkRINEN_MIX_RXFE=0 cmbG_FINE_LNA3_RXFE=0 chkPD_TIA_RXFE=1 chkPD_MXLOB_RXFE=1 chkPD_MIX_RXFE=1 chkPD_LNA_RXFE=1 [1] txtDesFreq=3.2 chkDITHEN=1 cmbDITHN=0 chbPwrPllMods=1 chbAUTOBYP=0 rgrDecode=0 rgrMODE=0 rgrSELVCO=3 rgrFRANGE=1 cmbSELOUT=1 chbEN_PFD_UP=1 chkOEN_TSTD_SX=0 chkPASSEN_TSTOD_SD=0 cmbICHP=14 chbBYPVCOREG=1 chbPDVCOREG=1 chbFSTVCOBG=1 cmbOFFUP=0 cmbVOVCOREG=5 cmbOFFDOWN=3 cmbVCOCAP=36 cmbBCODE=5 cmbACODE=0 cmbPD_VCOCOMP_SX=0 chkENLOBUF=1 chkENLAMP=1 chkTRI=0 chkPOL=0 chkPFDPD=1 chkENFEEDDIV=1 chkPFDCLKP=1 rgrBCLKSEL=2 rgrBINSEL=0 RefClk=40000000 [2] txtDesFreq=1.95 chkDITHEN=1 cmbDITHN=0 chbPwrPllMods=1 chbAUTOBYP=0 rgrDecode=0 rgrMODE=0 rgrSELVCO=1 rgrFRANGE=1 cmbSELOUT=1 chbEN_PFD_UP=1 chkOEN_TSTD_SX=0 chkPASSEN_TSTOD_SD=0 cmbICHP=12 chbBYPVCOREG=1 chbPDVCOREG=1 chbFSTVCOBG=1 cmbOFFUP=3 cmbVOVCOREG=5 cmbOFFDOWN=0 cmbVCOCAP=16 cmbBCODE=5 cmbACODE=0 cmbPD_VCOCOMP_SX=1 chkENLOBUF=1 chkENLAMP=1 chkTRI=0 chkPOL=0 chkPFDPD=1 chkENFEEDDIV=1 chkPFDCLKP=1 rgrBCLKSEL=2 rgrBINSEL=0 RefClk=40000000 [15] chbEN_ADC_DAC=0 rgrDecode=0 cmbDACInternalOutputLoadResistor=2 rgrDACReferenceCurrentResistor=1 cmbDACFullScaleOutputCurrent=0 cmbRefResistorBiasAdj=0 cmbRefBiasUp=0 cmbRefBiasDn=0 cmbRefGainAdj=0 cmbCoomonModeAdj=1 cmbRefBufferBoost=0 chkInputBufferDisable=1 rgrRX_FSYNC_P=0 rgrRX_INTER=0 rgrDAC_CLK_P=1 rgrTX_FSYNC_P=0 rgrTX_INTER=0 cmbADCSamplingPhase=0 cmbClockNonOverlapAdjust=0 rgrADCBiasResistorAdjust=0 cmbMainBiasDN=0 rgrADCAmp1Stage1BasUp=0 rgrADCAmp24Stage1BasUp=0 rgrADCAmp1Stage2BasUp=0 rgrADCAmp24Stage2BasUp=0 rgrQuantizerBiasUp=0 rgrInputBufferBiasUp=0 cmbBandgapTemp=8 cmbBandgapGain=8 cmbRefAmpsBiasAdj=0 cmbRefAmpsBiasUp=0 cmbRefAmpsBiasDn=0 chkEN_DAC=1 chkEN_ADC_I=1 chkEN_ADC_Q=1 chkEN_ADC_REF=1 chkEN_M_REF=1 From thomastsou at gmail.com Sun Jul 22 18:51:26 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Sun, 22 Jul 2012 14:51:26 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sun, Jul 22, 2012 at 12:59 AM, Alexander Chemeris wrote: > On Sun, Jul 22, 2012 at 6:40 AM, Thomas Tsou wrote: >> On Sat, Jul 21, 2012 at 5:57 PM, Alexander Chemeris >> wrote: >>> I've started documenting this at the wiki: >>> http://code.google.com/p/umtrx/wiki/LMS6002DCalibration#Tx_I/Q_balance_calibration >>> Is that a good enough description for you? >> >> Added: >> >> - IQ balance correction >> - Laurent C1 pulse >> >> We are below the target threshold. > > Great achievement! > Is it consistent over the whole 900 band, i.e. is that the worst case? Overall measurements are close (either above or below) to 1.5/5 for the 900 band in general. 945 MHz is currently the best case, but that is the frequency I spent the most time on with calibration. Do we need to be consistently below 1.5/5 or just close? > I guess in 1800 band we're above the threshold yet. Could you measure > by how much we're off there? At 1945 MHz,the best I could do was roughly 2.3/7.2 with IQ balance and LO leakage corrections. I didn't try any 1800 band frequencies. Thomas From thomastsou at gmail.com Sun Jul 22 19:11:13 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Sun, 22 Jul 2012 15:11:13 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sun, Jul 22, 2012 at 10:12 AM, Andrey Sviyazov wrote: > Hi Thomas. > > It is very good new. > Please let us know more information how you wins! > I mean which PLL filter, ICP and other LMS paremeters do you use or its done > by just only IQ balance correction and Laurent C1 pulse and all other by > default? Register dump and startup sequence are attached. LO leakage was also recalibrated for different frequencies. For comparison, after C1 pulse is added USRP1 is 1.3/3.5 and USRP2 is 1.2/3.0 when measured at 925 MHz. Thomas -------------- next part -------------- # 0x00: LMS1=0x1D LMS2=0x17 DIFF # 0x01: LMS1=0xF5 LMS2=0xE9 DIFF # 0x02: LMS1=0x1F LMS2=0x1F OK # 0x03: LMS1=0x08 LMS2=0x08 OK # 0x04: LMS1=0x22 LMS2=0x22 OK # 0x05: LMS1=0x3A LMS2=0x32 DIFF # 0x06: LMS1=0x0D LMS2=0x0D OK # 0x07: LMS1=0x0F LMS2=0x0F OK # 0x08: LMS1=0x00 LMS2=0x00 OK # 0x09: LMS1=0x81 LMS2=0x80 DIFF # 0x0A: LMS1=0x00 LMS2=0x00 OK # 0x0B: LMS1=0x08 LMS2=0x08 OK # 0x0C: LMS1=0x16 LMS2=0x21 DIFF # 0x0D: LMS1=0x6E LMS2=0xBD DIFF # 0x0E: LMS1=0x01 LMS2=0x01 OK # 0x0F: LMS1=0x00 LMS2=0x00 OK # 0x10: LMS1=0x48 LMS2=0x62 DIFF # 0x11: LMS1=0xB1 LMS2=0x76 DIFF # 0x12: LMS1=0x3B LMS2=0x27 DIFF # 0x13: LMS1=0x13 LMS2=0x62 DIFF # 0x14: LMS1=0x88 LMS2=0x88 OK # 0x15: LMS1=0x95 LMS2=0xBD DIFF # 0x16: LMS1=0x93 LMS2=0x8C DIFF # 0x17: LMS1=0xE0 LMS2=0xE0 OK # 0x18: LMS1=0x40 LMS2=0x40 OK # 0x19: LMS1=0x8E LMS2=0xAE DIFF # 0x1A: LMS1=0x03 LMS2=0x03 OK # 0x1B: LMS1=0x76 LMS2=0x76 OK # 0x1C: LMS1=0x38 LMS2=0x38 OK # 0x1D: LMS1=0x40 LMS2=0x40 OK # 0x1E: LMS1=0x00 LMS2=0x00 OK # 0x1F: LMS1=0x00 LMS2=0x00 OK # 0x20: LMS1=0x41 LMS2=0x41 OK # 0x21: LMS1=0x20 LMS2=0x20 OK # 0x22: LMS1=0x00 LMS2=0x00 OK # 0x23: LMS1=0x00 LMS2=0x00 OK # 0x24: LMS1=0x88 LMS2=0x88 OK # 0x25: LMS1=0xB1 LMS2=0xB1 OK # 0x26: LMS1=0x8C LMS2=0x8C OK # 0x27: LMS1=0xE3 LMS2=0xE3 OK # 0x28: LMS1=0x40 LMS2=0x40 OK # 0x29: LMS1=0x94 LMS2=0x94 OK # 0x2A: LMS1=0x03 LMS2=0x03 OK # 0x2B: LMS1=0x76 LMS2=0x76 OK # 0x2C: LMS1=0x38 LMS2=0x38 OK # 0x2D: LMS1=0x40 LMS2=0x40 OK # 0x2E: LMS1=0x00 LMS2=0x00 OK # 0x2F: LMS1=0x00 LMS2=0x00 OK # 0x30: LMS1=0x21 LMS2=0x25 DIFF # 0x31: LMS1=0x09 LMS2=0x08 DIFF # 0x32: LMS1=0x1F LMS2=0x1F OK # 0x33: LMS1=0x09 LMS2=0x09 OK # 0x34: LMS1=0x3E LMS2=0x3E OK # 0x35: LMS1=0x1D LMS2=0x17 DIFF # 0x36: LMS1=0x70 LMS2=0x70 OK # 0x37: LMS1=0x41 LMS2=0xCA DIFF # 0x38: LMS1=0x87 LMS2=0x9E DIFF # 0x39: LMS1=0x5D LMS2=0x7D DIFF # 0x3A: LMS1=0xE7 LMS2=0x4F DIFF # 0x3B: LMS1=0x0D LMS2=0xCF DIFF # 0x3C: LMS1=0x7E LMS2=0xCE DIFF # 0x3D: LMS1=0x93 LMS2=0x0E DIFF # 0x3E: LMS1=0x00 LMS2=0x00 OK # 0x3F: LMS1=0x11 LMS2=0x00 DIFF # 0x40: LMS1=0x02 LMS2=0x02 OK # 0x41: LMS1=0x15 LMS2=0x15 OK # 0x42: LMS1=0x67 LMS2=0x80 DIFF # 0x43: LMS1=0x89 LMS2=0x80 DIFF # 0x44: LMS1=0x13 LMS2=0x0B DIFF # 0x45: LMS1=0xC8 LMS2=0x00 DIFF # 0x46: LMS1=0x00 LMS2=0x00 OK # 0x47: LMS1=0x40 LMS2=0x40 OK # 0x48: LMS1=0x0C LMS2=0x0C OK # 0x49: LMS1=0x0C LMS2=0x0C OK # 0x4A: LMS1=0x18 LMS2=0x18 OK # 0x4B: LMS1=0x50 LMS2=0x50 OK # 0x4C: LMS1=0x00 LMS2=0x00 OK # 0x4D: LMS1=0x00 LMS2=0x00 OK # 0x4E: LMS1=0x00 LMS2=0x01 DIFF # 0x4F: LMS1=0x01 LMS2=0x00 DIFF # 0x50: LMS1=0x1F LMS2=0x09 DIFF # 0x51: LMS1=0x00 LMS2=0x14 DIFF # 0x52: LMS1=0x1F LMS2=0x1F OK # 0x53: LMS1=0x08 LMS2=0x09 DIFF # 0x54: LMS1=0x02 LMS2=0x02 OK # 0x55: LMS1=0x1D LMS2=0x17 DIFF # 0x56: LMS1=0x70 LMS2=0x70 OK # 0x57: LMS1=0x94 LMS2=0x94 OK # 0x58: LMS1=0x00 LMS2=0x00 OK # 0x59: LMS1=0x09 LMS2=0x09 OK # 0x5A: LMS1=0x20 LMS2=0x20 OK # 0x5B: LMS1=0x00 LMS2=0x00 OK # 0x5C: LMS1=0x00 LMS2=0x00 OK # 0x5D: LMS1=0x40 LMS2=0x00 DIFF # 0x5E: LMS1=0x00 LMS2=0x00 OK # 0x5F: LMS1=0x1F LMS2=0x5F DIFF # 0x60: LMS1=0x1F LMS2=0x19 DIFF # 0x61: LMS1=0x00 LMS2=0x1C DIFF # 0x62: LMS1=0x1F LMS2=0x1F OK # 0x63: LMS1=0x08 LMS2=0x0C DIFF # 0x64: LMS1=0x32 LMS2=0x32 OK # 0x65: LMS1=0x01 LMS2=0x01 OK # 0x66: LMS1=0x00 LMS2=0x00 OK # 0x67: LMS1=0x00 LMS2=0x00 OK # 0x68: LMS1=0x01 LMS2=0x01 OK # 0x69: LMS1=0xF6 LMS2=0x89 DIFF # 0x6A: LMS1=0x7F LMS2=0x7E DIFF # 0x6B: LMS1=0x7B LMS2=0xBF DIFF # 0x6C: LMS1=0xAF LMS2=0xDD DIFF # 0x6D: LMS1=0xAE LMS2=0x4F DIFF # 0x6E: LMS1=0x00 LMS2=0x00 OK # 0x6F: LMS1=0x00 LMS2=0x00 OK # 0x70: LMS1=0x01 LMS2=0x01 OK # 0x71: LMS1=0x80 LMS2=0x80 OK # 0x72: LMS1=0x80 LMS2=0x80 OK # 0x73: LMS1=0x00 LMS2=0x00 OK # 0x74: LMS1=0x00 LMS2=0x00 OK # 0x75: LMS1=0xD0 LMS2=0xD0 OK # 0x76: LMS1=0x78 LMS2=0x78 OK # 0x77: LMS1=0x00 LMS2=0x00 OK # 0x78: LMS1=0x1C LMS2=0x1C OK # 0x79: LMS1=0x37 LMS2=0x37 OK # 0x7A: LMS1=0x77 LMS2=0x77 OK # 0x7B: LMS1=0x77 LMS2=0x77 OK # 0x7C: LMS1=0x18 LMS2=0x18 OK # 0x7D: LMS1=0x00 LMS2=0x00 OK # 0x7E: LMS1=0x01 LMS2=0x10 DIFF # 0x7F: LMS1=0x00 LMS2=0x00 OK -------------- next part -------------- A non-text attachment was scrubbed... Name: umtrx_tx_init.sh Type: application/x-sh Size: 482 bytes Desc: not available URL: From alexander.chemeris at gmail.com Sun Jul 22 19:21:30 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sun, 22 Jul 2012 23:21:30 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sun, Jul 22, 2012 at 10:51 PM, Thomas Tsou wrote: > On Sun, Jul 22, 2012 at 12:59 AM, Alexander Chemeris > wrote: >> On Sun, Jul 22, 2012 at 6:40 AM, Thomas Tsou wrote: >>> On Sat, Jul 21, 2012 at 5:57 PM, Alexander Chemeris >>> wrote: >>>> I've started documenting this at the wiki: >>>> http://code.google.com/p/umtrx/wiki/LMS6002DCalibration#Tx_I/Q_balance_calibration >>>> Is that a good enough description for you? >>> >>> Added: >>> >>> - IQ balance correction >>> - Laurent C1 pulse >>> >>> We are below the target threshold. >> >> Great achievement! >> Is it consistent over the whole 900 band, i.e. is that the worst case? > > Overall measurements are close (either above or below) to 1.5/5 for > the 900 band in general. 945 MHz is currently the best case, but that > is the frequency I spent the most time on with calibration. Do we need > to be consistently below 1.5/5 or just close? Thanks for the measurements. At the end we should be below that at all GSM bands. For now it's fine to be close. I also noticed that your frequency is far off - could you calibrate it and make pictures of the best and worst case in the 900 band? And just to be sure - could you check what TCXO do you have on the UmTRX? It should be TCD4029-26.0M, probably marked like PLEU4030Z. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Sun Jul 22 19:27:34 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sun, 22 Jul 2012 23:27:34 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sun, Jul 22, 2012 at 11:11 PM, Thomas Tsou wrote: > On Sun, Jul 22, 2012 at 10:12 AM, Andrey Sviyazov > wrote: >> Hi Thomas. >> >> It is very good new. >> Please let us know more information how you wins! >> I mean which PLL filter, ICP and other LMS paremeters do you use or its done >> by just only IQ balance correction and Laurent C1 pulse and all other by >> default? > > Register dump and startup sequence are attached. Uhm, this is a register dump at what time? Originally I asked for the dump before and after every line in the umtrx_tx_init.sh. > LO leakage was also recalibrated for different frequencies. How different are calibration values? I've never checked how is it related to the PLL frequency. > For comparison, after C1 pulse is added USRP1 is 1.3/3.5 and USRP2 is > 1.2/3.0 when measured at 925 MHz. tip: Would be great if you push this to github just as you send e-mail :) PS Sylvain is waiting for a howto to run OpenBTS with UmTRX to test his setup. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From andreysviyaz at gmail.com Sun Jul 22 19:53:04 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Sun, 22 Jul 2012 23:53:04 +0400 Subject: Improving LMS6002 phase noise In-Reply-To: <500C1E87.2090106@limemicro.com> References: <500ABDB7.40001@limemicro.com> <500BDFFB.7050806@limemicro.com> <500C1E87.2090106@limemicro.com> Message-ID: Hi Srdjan. First of all thank you for support. We do not have register dump. However, Lime GUI project file used in this > experiment is attached. You can use GUI File->Open Project option to import > it. I see Ichp and Ichp offset currents are different from defaults but > these still do not justify 5-12dB worse PN in your reports. You can give it > a try though before changing TCXCO. > We will try to adjust Ichp and offset first off all. Thank you for hint. *Test Description:* > > - DC MAX applied through analogue inputs, DACs off > > It is quite important detail too. > > > > - TXVGA1 and TXVGA2 at max gain > > Similar. > > > > - Loop filter redesigned for 100kHz loop bandwidth and 40MHz reference > > > - Icp and Icp offset optimized at 25 deg. Same set up used at all > other temperatures > > Please inform us values of components for 100kHz BW filter. But we are forced to use one clock 26MHz for all because of target price. > > > > - Cap code and VCO picked up by PLL tune routine > > I implemented 10kHz BW filter for PLL and found that frequency locking become unstable because of calculated VCOCAP value a bit lower then required (too high capacity). If VCOCAP incremented manualy (after auto-tuned) then no any problems. What do you think about it. And could you please inform me values for 10 kHz BW filter, just to compare with my calculations. Best regards, Andrey Sviyazov. -------------- next part -------------- An HTML attachment was scrubbed... URL: From andrey.sviyazov at fairwaves.ru Sun Jul 22 19:59:44 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Sun, 22 Jul 2012 23:59:44 +0400 Subject: Improving LMS6002 phase noise In-Reply-To: References: <500ABDB7.40001@limemicro.com> <500BDFFB.7050806@limemicro.com> <500C1E87.2090106@limemicro.com> Message-ID: Hi Srdjan. First of all thank you for support. We do not have register dump. However, Lime GUI project file used in this > experiment is attached. You can use GUI File->Open Project option to import > it. I see Ichp and Ichp offset currents are different from defaults but > these still do not justify 5-12dB worse PN in your reports. You can give it > a try though before changing TCXCO. > We will try to adjust Ichp and offset first off all. Thank you for hint. *Test Description:* > > - DC MAX applied through analogue inputs, DACs off > > It is quite important detail too. > > > > - TXVGA1 and TXVGA2 at max gain > > Similar. > > > > - Loop filter redesigned for 100kHz loop bandwidth and 40MHz reference > > > - Icp and Icp offset optimized at 25 deg. Same set up used at all > other temperatures > > Please inform us values of components for 100kHz BW filter. But we are forced to use one clock 26MHz for all because of target price. > > > > - Cap code and VCO picked up by PLL tune routine > > I implemented 10kHz BW filter for PLL and found that frequency locking become unstable because of calculated VCOCAP value a bit lower then required (too high capacity). If VCOCAP incremented manualy (after auto-tuned) then no any problems. What do you think about it. And could you please inform me values for 10 kHz BW filter, just to compare with my calculations. Best regards, Andrey Sviyazov. -------------- next part -------------- An HTML attachment was scrubbed... URL: From thomastsou at gmail.com Sun Jul 22 20:14:25 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Sun, 22 Jul 2012 16:14:25 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sun, Jul 22, 2012 at 3:27 PM, Alexander Chemeris wrote: > On Sun, Jul 22, 2012 at 11:11 PM, Thomas Tsou wrote: >> On Sun, Jul 22, 2012 at 10:12 AM, Andrey Sviyazov >> wrote: >>> Hi Thomas. >>> >>> It is very good new. >>> Please let us know more information how you wins! >>> I mean which PLL filter, ICP and other LMS paremeters do you use or its done >>> by just only IQ balance correction and Laurent C1 pulse and all other by >>> default? >> >> Register dump and startup sequence are attached. > > Uhm, this is a register dump at what time? Originally I asked for the > dump before and after every line in the umtrx_tx_init.sh. That was for Andrey. That dump was taken during the previous 945 MHz measurement. These dumps are for the calibration failure, which are taken at the following points. 0 ./umtrx_lms.py --lms 1 --lms-init 1 ./umtrx_lms.py --lms 1 --lms-tx-enable 1 2 ./umtrx_lms.py --lms 1 --pll-ref-clock 26e6 --lpf-bandwidth-code 0x0f --lms-auto-calibration 3 >> LO leakage was also recalibrated for different frequencies. > > How different are calibration values? I've never checked how is it > related to the PLL frequency. A single value within 900 MHz. At 1900 MHz it's maybe up to 3 or 4. LO leakage is easy to calibrate though. IQ calibration is rather tedious - calibration values at 900 MHz are useless at 1900 MHz. >> For comparison, after C1 pulse is added USRP1 is 1.3/3.5 and USRP2 is >> 1.2/3.0 when measured at 925 MHz. > > tip: Would be great if you push this to github just as you send e-mail :) I'm posting the measurement captures and the Matlab for the pulse sequence generation. The transceiver code is pretty ugly right now. There are many stuffing bits and zero padding added to minimize the start / end error on the E4406. It may not even work with real phones now. > PS Sylvain is waiting for a howto to run OpenBTS with UmTRX to test his setup. I'll hack something together later tonight. Can he receive a tone? If yes, then everything else is straightforward. Thomas -------------- next part -------------- # 0x00: LMS1=0x1F LMS2=0x1F OK # 0x01: LMS1=0xE0 LMS2=0xE0 OK # 0x02: LMS1=0x1F LMS2=0x1F OK # 0x03: LMS1=0x08 LMS2=0x08 OK # 0x04: LMS1=0x22 LMS2=0x22 OK # 0x05: LMS1=0x32 LMS2=0x32 OK # 0x06: LMS1=0x0D LMS2=0x0D OK # 0x07: LMS1=0x00 LMS2=0x00 OK # 0x08: LMS1=0x00 LMS2=0x00 OK # 0x09: LMS1=0x40 LMS2=0x40 OK # 0x0A: LMS1=0x00 LMS2=0x00 OK # 0x0B: LMS1=0x08 LMS2=0x08 OK # 0x0C: LMS1=0x16 LMS2=0x21 DIFF # 0x0D: LMS1=0x6E LMS2=0x3D DIFF # 0x0E: LMS1=0x01 LMS2=0x01 OK # 0x0F: LMS1=0x00 LMS2=0x00 OK # 0x10: LMS1=0x41 LMS2=0x41 OK # 0x11: LMS1=0x20 LMS2=0x20 OK # 0x12: LMS1=0x00 LMS2=0x00 OK # 0x13: LMS1=0x00 LMS2=0x00 OK # 0x14: LMS1=0x88 LMS2=0x88 OK # 0x15: LMS1=0xB1 LMS2=0xB1 OK # 0x16: LMS1=0x8C LMS2=0x8C OK # 0x17: LMS1=0xE0 LMS2=0xE0 OK # 0x18: LMS1=0x40 LMS2=0x40 OK # 0x19: LMS1=0x94 LMS2=0x94 OK # 0x1A: LMS1=0x03 LMS2=0x03 OK # 0x1B: LMS1=0x76 LMS2=0x76 OK # 0x1C: LMS1=0x38 LMS2=0x38 OK # 0x1D: LMS1=0x40 LMS2=0x40 OK # 0x1E: LMS1=0x00 LMS2=0x00 OK # 0x1F: LMS1=0x00 LMS2=0x00 OK # 0x20: LMS1=0x41 LMS2=0x41 OK # 0x21: LMS1=0x20 LMS2=0x20 OK # 0x22: LMS1=0x00 LMS2=0x00 OK # 0x23: LMS1=0x00 LMS2=0x00 OK # 0x24: LMS1=0x88 LMS2=0x88 OK # 0x25: LMS1=0xB1 LMS2=0xB1 OK # 0x26: LMS1=0x8C LMS2=0x8C OK # 0x27: LMS1=0xE0 LMS2=0xE0 OK # 0x28: LMS1=0x40 LMS2=0x40 OK # 0x29: LMS1=0x94 LMS2=0x94 OK # 0x2A: LMS1=0x03 LMS2=0x03 OK # 0x2B: LMS1=0x76 LMS2=0x76 OK # 0x2C: LMS1=0x38 LMS2=0x38 OK # 0x2D: LMS1=0x40 LMS2=0x40 OK # 0x2E: LMS1=0x00 LMS2=0x00 OK # 0x2F: LMS1=0x00 LMS2=0x00 OK # 0x30: LMS1=0x1F LMS2=0x1F OK # 0x31: LMS1=0x00 LMS2=0x00 OK # 0x32: LMS1=0x1F LMS2=0x1F OK # 0x33: LMS1=0x08 LMS2=0x08 OK # 0x34: LMS1=0x02 LMS2=0x02 OK # 0x35: LMS1=0x0E LMS2=0x0C DIFF # 0x36: LMS1=0x30 LMS2=0x30 OK # 0x37: LMS1=0x41 LMS2=0xCA DIFF # 0x38: LMS1=0x87 LMS2=0x9E DIFF # 0x39: LMS1=0x5F LMS2=0x7D DIFF # 0x3A: LMS1=0xE7 LMS2=0x4F DIFF # 0x3B: LMS1=0x0F LMS2=0xCF DIFF # 0x3C: LMS1=0x7E LMS2=0xCE DIFF # 0x3D: LMS1=0x93 LMS2=0x2C DIFF # 0x3E: LMS1=0x40 LMS2=0x00 DIFF # 0x3F: LMS1=0x91 LMS2=0x00 DIFF # 0x40: LMS1=0x02 LMS2=0x02 OK # 0x41: LMS1=0x15 LMS2=0x15 OK # 0x42: LMS1=0x80 LMS2=0x80 OK # 0x43: LMS1=0x84 LMS2=0x80 DIFF # 0x44: LMS1=0x0B LMS2=0x0B OK # 0x45: LMS1=0x00 LMS2=0x00 OK # 0x46: LMS1=0x00 LMS2=0x00 OK # 0x47: LMS1=0x60 LMS2=0x60 OK # 0x48: LMS1=0x0C LMS2=0x0C OK # 0x49: LMS1=0x0C LMS2=0x0C OK # 0x4A: LMS1=0x18 LMS2=0x18 OK # 0x4B: LMS1=0x50 LMS2=0x50 OK # 0x4C: LMS1=0x00 LMS2=0x00 OK # 0x4D: LMS1=0x00 LMS2=0x00 OK # 0x4E: LMS1=0x00 LMS2=0x01 DIFF # 0x4F: LMS1=0x01 LMS2=0x00 DIFF # 0x50: LMS1=0x1F LMS2=0x1F OK # 0x51: LMS1=0x00 LMS2=0x00 OK # 0x52: LMS1=0x1F LMS2=0x1F OK # 0x53: LMS1=0x08 LMS2=0x08 OK # 0x54: LMS1=0x02 LMS2=0x02 OK # 0x55: LMS1=0x0C LMS2=0x0C OK # 0x56: LMS1=0x30 LMS2=0x30 OK # 0x57: LMS1=0x94 LMS2=0x94 OK # 0x58: LMS1=0x00 LMS2=0x00 OK # 0x59: LMS1=0x01 LMS2=0x01 OK # 0x5A: LMS1=0x20 LMS2=0x20 OK # 0x5B: LMS1=0x00 LMS2=0x00 OK # 0x5C: LMS1=0x00 LMS2=0x00 OK # 0x5D: LMS1=0x40 LMS2=0x00 DIFF # 0x5E: LMS1=0x00 LMS2=0x00 OK # 0x5F: LMS1=0x1F LMS2=0x5F DIFF # 0x60: LMS1=0x1F LMS2=0x1F OK # 0x61: LMS1=0x00 LMS2=0x00 OK # 0x62: LMS1=0x1F LMS2=0x1F OK # 0x63: LMS1=0x08 LMS2=0x08 OK # 0x64: LMS1=0x1E LMS2=0x1E OK # 0x65: LMS1=0x01 LMS2=0x01 OK # 0x66: LMS1=0x00 LMS2=0x00 OK # 0x67: LMS1=0x00 LMS2=0x00 OK # 0x68: LMS1=0x01 LMS2=0x01 OK # 0x69: LMS1=0xF6 LMS2=0x89 DIFF # 0x6A: LMS1=0x2F LMS2=0x7E DIFF # 0x6B: LMS1=0x7B LMS2=0xBF DIFF # 0x6C: LMS1=0xEF LMS2=0xD4 DIFF # 0x6D: LMS1=0xAE LMS2=0x5F DIFF # 0x6E: LMS1=0x00 LMS2=0x00 OK # 0x6F: LMS1=0x00 LMS2=0x00 OK # 0x70: LMS1=0x01 LMS2=0x01 OK # 0x71: LMS1=0x80 LMS2=0x80 OK # 0x72: LMS1=0x80 LMS2=0x80 OK # 0x73: LMS1=0x00 LMS2=0x00 OK # 0x74: LMS1=0x00 LMS2=0x00 OK # 0x75: LMS1=0xD0 LMS2=0xD0 OK # 0x76: LMS1=0x78 LMS2=0x78 OK # 0x77: LMS1=0x00 LMS2=0x00 OK # 0x78: LMS1=0x1C LMS2=0x1C OK # 0x79: LMS1=0x1C LMS2=0x1C OK # 0x7A: LMS1=0x77 LMS2=0x77 OK # 0x7B: LMS1=0x77 LMS2=0x77 OK # 0x7C: LMS1=0x18 LMS2=0x18 OK # 0x7D: LMS1=0x00 LMS2=0x00 OK # 0x7E: LMS1=0x01 LMS2=0x10 DIFF # 0x7F: LMS1=0x00 LMS2=0x00 OK -------------- next part -------------- # 0x00: LMS1=0x1F LMS2=0x1F OK # 0x01: LMS1=0xE0 LMS2=0xE0 OK # 0x02: LMS1=0x1F LMS2=0x1F OK # 0x03: LMS1=0x08 LMS2=0x08 OK # 0x04: LMS1=0x22 LMS2=0x22 OK # 0x05: LMS1=0x32 LMS2=0x32 OK # 0x06: LMS1=0x0D LMS2=0x0D OK # 0x07: LMS1=0x00 LMS2=0x00 OK # 0x08: LMS1=0x00 LMS2=0x00 OK # 0x09: LMS1=0x80 LMS2=0x40 DIFF # 0x0A: LMS1=0x00 LMS2=0x00 OK # 0x0B: LMS1=0x08 LMS2=0x08 OK # 0x0C: LMS1=0x16 LMS2=0x21 DIFF # 0x0D: LMS1=0x6E LMS2=0x3D DIFF # 0x0E: LMS1=0x01 LMS2=0x01 OK # 0x0F: LMS1=0x00 LMS2=0x00 OK # 0x10: LMS1=0x41 LMS2=0x41 OK # 0x11: LMS1=0x20 LMS2=0x20 OK # 0x12: LMS1=0x00 LMS2=0x00 OK # 0x13: LMS1=0x00 LMS2=0x00 OK # 0x14: LMS1=0x88 LMS2=0x88 OK # 0x15: LMS1=0xB1 LMS2=0xB1 OK # 0x16: LMS1=0x8C LMS2=0x8C OK # 0x17: LMS1=0xE0 LMS2=0xE0 OK # 0x18: LMS1=0x40 LMS2=0x40 OK # 0x19: LMS1=0x94 LMS2=0x94 OK # 0x1A: LMS1=0x03 LMS2=0x03 OK # 0x1B: LMS1=0x76 LMS2=0x76 OK # 0x1C: LMS1=0x38 LMS2=0x38 OK # 0x1D: LMS1=0x40 LMS2=0x40 OK # 0x1E: LMS1=0x00 LMS2=0x00 OK # 0x1F: LMS1=0x00 LMS2=0x00 OK # 0x20: LMS1=0x41 LMS2=0x41 OK # 0x21: LMS1=0x20 LMS2=0x20 OK # 0x22: LMS1=0x00 LMS2=0x00 OK # 0x23: LMS1=0x00 LMS2=0x00 OK # 0x24: LMS1=0x88 LMS2=0x88 OK # 0x25: LMS1=0xB1 LMS2=0xB1 OK # 0x26: LMS1=0x8C LMS2=0x8C OK # 0x27: LMS1=0xE3 LMS2=0xE0 DIFF # 0x28: LMS1=0x40 LMS2=0x40 OK # 0x29: LMS1=0x94 LMS2=0x94 OK # 0x2A: LMS1=0x03 LMS2=0x03 OK # 0x2B: LMS1=0x76 LMS2=0x76 OK # 0x2C: LMS1=0x38 LMS2=0x38 OK # 0x2D: LMS1=0x40 LMS2=0x40 OK # 0x2E: LMS1=0x00 LMS2=0x00 OK # 0x2F: LMS1=0x00 LMS2=0x00 OK # 0x30: LMS1=0x1F LMS2=0x1F OK # 0x31: LMS1=0x00 LMS2=0x00 OK # 0x32: LMS1=0x1F LMS2=0x1F OK # 0x33: LMS1=0x08 LMS2=0x08 OK # 0x34: LMS1=0x02 LMS2=0x02 OK # 0x35: LMS1=0x0E LMS2=0x0C DIFF # 0x36: LMS1=0x30 LMS2=0x30 OK # 0x37: LMS1=0x41 LMS2=0xCA DIFF # 0x38: LMS1=0x87 LMS2=0x9E DIFF # 0x39: LMS1=0x5F LMS2=0x7D DIFF # 0x3A: LMS1=0xE7 LMS2=0x4F DIFF # 0x3B: LMS1=0x0F LMS2=0xCF DIFF # 0x3C: LMS1=0x7E LMS2=0xCE DIFF # 0x3D: LMS1=0x93 LMS2=0x2C DIFF # 0x3E: LMS1=0x40 LMS2=0x00 DIFF # 0x3F: LMS1=0x91 LMS2=0x00 DIFF # 0x40: LMS1=0x02 LMS2=0x02 OK # 0x41: LMS1=0x15 LMS2=0x15 OK # 0x42: LMS1=0x80 LMS2=0x80 OK # 0x43: LMS1=0x84 LMS2=0x80 DIFF # 0x44: LMS1=0x0B LMS2=0x0B OK # 0x45: LMS1=0x00 LMS2=0x00 OK # 0x46: LMS1=0x00 LMS2=0x00 OK # 0x47: LMS1=0x40 LMS2=0x60 DIFF # 0x48: LMS1=0x0C LMS2=0x0C OK # 0x49: LMS1=0x0C LMS2=0x0C OK # 0x4A: LMS1=0x18 LMS2=0x18 OK # 0x4B: LMS1=0x50 LMS2=0x50 OK # 0x4C: LMS1=0x00 LMS2=0x00 OK # 0x4D: LMS1=0x00 LMS2=0x00 OK # 0x4E: LMS1=0x00 LMS2=0x01 DIFF # 0x4F: LMS1=0x01 LMS2=0x00 DIFF # 0x50: LMS1=0x1F LMS2=0x1F OK # 0x51: LMS1=0x00 LMS2=0x00 OK # 0x52: LMS1=0x1F LMS2=0x1F OK # 0x53: LMS1=0x08 LMS2=0x08 OK # 0x54: LMS1=0x02 LMS2=0x02 OK # 0x55: LMS1=0x0C LMS2=0x0C OK # 0x56: LMS1=0x30 LMS2=0x30 OK # 0x57: LMS1=0x94 LMS2=0x94 OK # 0x58: LMS1=0x00 LMS2=0x00 OK # 0x59: LMS1=0x09 LMS2=0x01 DIFF # 0x5A: LMS1=0x20 LMS2=0x20 OK # 0x5B: LMS1=0x00 LMS2=0x00 OK # 0x5C: LMS1=0x00 LMS2=0x00 OK # 0x5D: LMS1=0x40 LMS2=0x00 DIFF # 0x5E: LMS1=0x00 LMS2=0x00 OK # 0x5F: LMS1=0x1F LMS2=0x5F DIFF # 0x60: LMS1=0x1F LMS2=0x1F OK # 0x61: LMS1=0x00 LMS2=0x00 OK # 0x62: LMS1=0x1F LMS2=0x1F OK # 0x63: LMS1=0x08 LMS2=0x08 OK # 0x64: LMS1=0x32 LMS2=0x1E DIFF # 0x65: LMS1=0x01 LMS2=0x01 OK # 0x66: LMS1=0x00 LMS2=0x00 OK # 0x67: LMS1=0x00 LMS2=0x00 OK # 0x68: LMS1=0x01 LMS2=0x01 OK # 0x69: LMS1=0xF6 LMS2=0x89 DIFF # 0x6A: LMS1=0x2F LMS2=0x7E DIFF # 0x6B: LMS1=0x7B LMS2=0xBF DIFF # 0x6C: LMS1=0xEF LMS2=0xD4 DIFF # 0x6D: LMS1=0xAE LMS2=0x5F DIFF # 0x6E: LMS1=0x00 LMS2=0x00 OK # 0x6F: LMS1=0x00 LMS2=0x00 OK # 0x70: LMS1=0x01 LMS2=0x01 OK # 0x71: LMS1=0x80 LMS2=0x80 OK # 0x72: LMS1=0x80 LMS2=0x80 OK # 0x73: LMS1=0x00 LMS2=0x00 OK # 0x74: LMS1=0x00 LMS2=0x00 OK # 0x75: LMS1=0xD0 LMS2=0xD0 OK # 0x76: LMS1=0x78 LMS2=0x78 OK # 0x77: LMS1=0x00 LMS2=0x00 OK # 0x78: LMS1=0x1C LMS2=0x1C OK # 0x79: LMS1=0x37 LMS2=0x1C DIFF # 0x7A: LMS1=0x77 LMS2=0x77 OK # 0x7B: LMS1=0x77 LMS2=0x77 OK # 0x7C: LMS1=0x18 LMS2=0x18 OK # 0x7D: LMS1=0x00 LMS2=0x00 OK # 0x7E: LMS1=0x01 LMS2=0x10 DIFF # 0x7F: LMS1=0x00 LMS2=0x00 OK -------------- next part -------------- # 0x00: LMS1=0x1F LMS2=0x1F OK # 0x01: LMS1=0xE0 LMS2=0xE0 OK # 0x02: LMS1=0x1F LMS2=0x1F OK # 0x03: LMS1=0x08 LMS2=0x08 OK # 0x04: LMS1=0x22 LMS2=0x22 OK # 0x05: LMS1=0x3A LMS2=0x32 DIFF # 0x06: LMS1=0x0D LMS2=0x0D OK # 0x07: LMS1=0x00 LMS2=0x00 OK # 0x08: LMS1=0x00 LMS2=0x00 OK # 0x09: LMS1=0x81 LMS2=0x40 DIFF # 0x0A: LMS1=0x00 LMS2=0x00 OK # 0x0B: LMS1=0x08 LMS2=0x08 OK # 0x0C: LMS1=0x16 LMS2=0x21 DIFF # 0x0D: LMS1=0x6E LMS2=0x3D DIFF # 0x0E: LMS1=0x01 LMS2=0x01 OK # 0x0F: LMS1=0x00 LMS2=0x00 OK # 0x10: LMS1=0x41 LMS2=0x41 OK # 0x11: LMS1=0x20 LMS2=0x20 OK # 0x12: LMS1=0x00 LMS2=0x00 OK # 0x13: LMS1=0x00 LMS2=0x00 OK # 0x14: LMS1=0x88 LMS2=0x88 OK # 0x15: LMS1=0xB1 LMS2=0xB1 OK # 0x16: LMS1=0x8C LMS2=0x8C OK # 0x17: LMS1=0xE0 LMS2=0xE0 OK # 0x18: LMS1=0x40 LMS2=0x40 OK # 0x19: LMS1=0x94 LMS2=0x94 OK # 0x1A: LMS1=0x43 LMS2=0x03 DIFF # 0x1B: LMS1=0x76 LMS2=0x76 OK # 0x1C: LMS1=0x38 LMS2=0x38 OK # 0x1D: LMS1=0x40 LMS2=0x40 OK # 0x1E: LMS1=0x00 LMS2=0x00 OK # 0x1F: LMS1=0x00 LMS2=0x00 OK # 0x20: LMS1=0x41 LMS2=0x41 OK # 0x21: LMS1=0x20 LMS2=0x20 OK # 0x22: LMS1=0x00 LMS2=0x00 OK # 0x23: LMS1=0x00 LMS2=0x00 OK # 0x24: LMS1=0x88 LMS2=0x88 OK # 0x25: LMS1=0xB1 LMS2=0xB1 OK # 0x26: LMS1=0x8C LMS2=0x8C OK # 0x27: LMS1=0xE3 LMS2=0xE0 DIFF # 0x28: LMS1=0x40 LMS2=0x40 OK # 0x29: LMS1=0x94 LMS2=0x94 OK # 0x2A: LMS1=0x03 LMS2=0x03 OK # 0x2B: LMS1=0x76 LMS2=0x76 OK # 0x2C: LMS1=0x38 LMS2=0x38 OK # 0x2D: LMS1=0x40 LMS2=0x40 OK # 0x2E: LMS1=0x00 LMS2=0x00 OK # 0x2F: LMS1=0x00 LMS2=0x00 OK # 0x30: LMS1=0x1F LMS2=0x1F OK # 0x31: LMS1=0x00 LMS2=0x00 OK # 0x32: LMS1=0x1F LMS2=0x1F OK # 0x33: LMS1=0x08 LMS2=0x08 OK # 0x34: LMS1=0x02 LMS2=0x02 OK # 0x35: LMS1=0x0E LMS2=0x0C DIFF # 0x36: LMS1=0x30 LMS2=0x30 OK # 0x37: LMS1=0x41 LMS2=0xCA DIFF # 0x38: LMS1=0x87 LMS2=0x9E DIFF # 0x39: LMS1=0x5F LMS2=0x7D DIFF # 0x3A: LMS1=0xE7 LMS2=0x4F DIFF # 0x3B: LMS1=0x0F LMS2=0xCF DIFF # 0x3C: LMS1=0x7E LMS2=0xCE DIFF # 0x3D: LMS1=0x93 LMS2=0x2C DIFF # 0x3E: LMS1=0x40 LMS2=0x00 DIFF # 0x3F: LMS1=0x91 LMS2=0x00 DIFF # 0x40: LMS1=0x02 LMS2=0x02 OK # 0x41: LMS1=0x15 LMS2=0x15 OK # 0x42: LMS1=0x80 LMS2=0x80 OK # 0x43: LMS1=0x84 LMS2=0x80 DIFF # 0x44: LMS1=0x0B LMS2=0x0B OK # 0x45: LMS1=0x00 LMS2=0x00 OK # 0x46: LMS1=0x00 LMS2=0x00 OK # 0x47: LMS1=0x40 LMS2=0x60 DIFF # 0x48: LMS1=0x0C LMS2=0x0C OK # 0x49: LMS1=0x0C LMS2=0x0C OK # 0x4A: LMS1=0x18 LMS2=0x18 OK # 0x4B: LMS1=0x50 LMS2=0x50 OK # 0x4C: LMS1=0x00 LMS2=0x00 OK # 0x4D: LMS1=0x00 LMS2=0x00 OK # 0x4E: LMS1=0x00 LMS2=0x01 DIFF # 0x4F: LMS1=0x01 LMS2=0x00 DIFF # 0x50: LMS1=0x1F LMS2=0x1F OK # 0x51: LMS1=0x00 LMS2=0x00 OK # 0x52: LMS1=0x1F LMS2=0x1F OK # 0x53: LMS1=0x08 LMS2=0x08 OK # 0x54: LMS1=0x02 LMS2=0x02 OK # 0x55: LMS1=0x0C LMS2=0x0C OK # 0x56: LMS1=0x30 LMS2=0x30 OK # 0x57: LMS1=0x94 LMS2=0x94 OK # 0x58: LMS1=0x00 LMS2=0x00 OK # 0x59: LMS1=0x09 LMS2=0x01 DIFF # 0x5A: LMS1=0x20 LMS2=0x20 OK # 0x5B: LMS1=0x00 LMS2=0x00 OK # 0x5C: LMS1=0x00 LMS2=0x00 OK # 0x5D: LMS1=0x40 LMS2=0x00 DIFF # 0x5E: LMS1=0x00 LMS2=0x00 OK # 0x5F: LMS1=0x1F LMS2=0x5F DIFF # 0x60: LMS1=0x1F LMS2=0x1F OK # 0x61: LMS1=0x00 LMS2=0x00 OK # 0x62: LMS1=0x1F LMS2=0x1F OK # 0x63: LMS1=0x08 LMS2=0x08 OK # 0x64: LMS1=0x32 LMS2=0x1E DIFF # 0x65: LMS1=0x01 LMS2=0x01 OK # 0x66: LMS1=0x00 LMS2=0x00 OK # 0x67: LMS1=0x00 LMS2=0x00 OK # 0x68: LMS1=0x01 LMS2=0x01 OK # 0x69: LMS1=0xF6 LMS2=0x89 DIFF # 0x6A: LMS1=0x2F LMS2=0x7E DIFF # 0x6B: LMS1=0x7B LMS2=0xBF DIFF # 0x6C: LMS1=0xEF LMS2=0xD4 DIFF # 0x6D: LMS1=0xAE LMS2=0x5F DIFF # 0x6E: LMS1=0x00 LMS2=0x00 OK # 0x6F: LMS1=0x00 LMS2=0x00 OK # 0x70: LMS1=0x01 LMS2=0x01 OK # 0x71: LMS1=0x80 LMS2=0x80 OK # 0x72: LMS1=0x80 LMS2=0x80 OK # 0x73: LMS1=0x00 LMS2=0x00 OK # 0x74: LMS1=0x00 LMS2=0x00 OK # 0x75: LMS1=0xD0 LMS2=0xD0 OK # 0x76: LMS1=0x78 LMS2=0x78 OK # 0x77: LMS1=0x00 LMS2=0x00 OK # 0x78: LMS1=0x1C LMS2=0x1C OK # 0x79: LMS1=0x37 LMS2=0x1C DIFF # 0x7A: LMS1=0x77 LMS2=0x77 OK # 0x7B: LMS1=0x77 LMS2=0x77 OK # 0x7C: LMS1=0x18 LMS2=0x18 OK # 0x7D: LMS1=0x00 LMS2=0x00 OK # 0x7E: LMS1=0x01 LMS2=0x10 DIFF # 0x7F: LMS1=0x00 LMS2=0x00 OK -------------- next part -------------- # 0x00: LMS1=0x1D LMS2=0x1F DIFF # 0x01: LMS1=0xE9 LMS2=0xE0 DIFF # 0x02: LMS1=0x1F LMS2=0x1F OK # 0x03: LMS1=0x08 LMS2=0x08 OK # 0x04: LMS1=0x22 LMS2=0x22 OK # 0x05: LMS1=0x3A LMS2=0x32 DIFF # 0x06: LMS1=0x0D LMS2=0x0D OK # 0x07: LMS1=0x0F LMS2=0x00 DIFF # 0x08: LMS1=0x00 LMS2=0x00 OK # 0x09: LMS1=0x81 LMS2=0x40 DIFF # 0x0A: LMS1=0x00 LMS2=0x00 OK # 0x0B: LMS1=0x08 LMS2=0x08 OK # 0x0C: LMS1=0x16 LMS2=0x21 DIFF # 0x0D: LMS1=0x6E LMS2=0x3D DIFF # 0x0E: LMS1=0x01 LMS2=0x01 OK # 0x0F: LMS1=0x00 LMS2=0x00 OK # 0x10: LMS1=0x62 LMS2=0x41 DIFF # 0x11: LMS1=0x76 LMS2=0x20 DIFF # 0x12: LMS1=0x27 LMS2=0x00 DIFF # 0x13: LMS1=0x62 LMS2=0x00 DIFF # 0x14: LMS1=0x88 LMS2=0x88 OK # 0x15: LMS1=0xBD LMS2=0xB1 DIFF # 0x16: LMS1=0x8C LMS2=0x8C OK # 0x17: LMS1=0xE0 LMS2=0xE0 OK # 0x18: LMS1=0x40 LMS2=0x40 OK # 0x19: LMS1=0xAE LMS2=0x94 DIFF # 0x1A: LMS1=0x03 LMS2=0x03 OK # 0x1B: LMS1=0x76 LMS2=0x76 OK # 0x1C: LMS1=0x38 LMS2=0x38 OK # 0x1D: LMS1=0x40 LMS2=0x40 OK # 0x1E: LMS1=0x00 LMS2=0x00 OK # 0x1F: LMS1=0x00 LMS2=0x00 OK # 0x20: LMS1=0x41 LMS2=0x41 OK # 0x21: LMS1=0x20 LMS2=0x20 OK # 0x22: LMS1=0x00 LMS2=0x00 OK # 0x23: LMS1=0x00 LMS2=0x00 OK # 0x24: LMS1=0x88 LMS2=0x88 OK # 0x25: LMS1=0xB1 LMS2=0xB1 OK # 0x26: LMS1=0x8C LMS2=0x8C OK # 0x27: LMS1=0xE3 LMS2=0xE0 DIFF # 0x28: LMS1=0x40 LMS2=0x40 OK # 0x29: LMS1=0x94 LMS2=0x94 OK # 0x2A: LMS1=0x03 LMS2=0x03 OK # 0x2B: LMS1=0x76 LMS2=0x76 OK # 0x2C: LMS1=0x38 LMS2=0x38 OK # 0x2D: LMS1=0x40 LMS2=0x40 OK # 0x2E: LMS1=0x00 LMS2=0x00 OK # 0x2F: LMS1=0x00 LMS2=0x00 OK # 0x30: LMS1=0x1F LMS2=0x1F OK # 0x31: LMS1=0x00 LMS2=0x00 OK # 0x32: LMS1=0x1F LMS2=0x1F OK # 0x33: LMS1=0x08 LMS2=0x08 OK # 0x34: LMS1=0x02 LMS2=0x02 OK # 0x35: LMS1=0x1D LMS2=0x0C DIFF # 0x36: LMS1=0x70 LMS2=0x30 DIFF # 0x37: LMS1=0x41 LMS2=0xCA DIFF # 0x38: LMS1=0x87 LMS2=0x9E DIFF # 0x39: LMS1=0x5F LMS2=0x7D DIFF # 0x3A: LMS1=0xE7 LMS2=0x4F DIFF # 0x3B: LMS1=0x0F LMS2=0xCF DIFF # 0x3C: LMS1=0x7E LMS2=0xCE DIFF # 0x3D: LMS1=0x93 LMS2=0x2C DIFF # 0x3E: LMS1=0x40 LMS2=0x00 DIFF # 0x3F: LMS1=0x91 LMS2=0x00 DIFF # 0x40: LMS1=0x02 LMS2=0x02 OK # 0x41: LMS1=0x15 LMS2=0x15 OK # 0x42: LMS1=0x80 LMS2=0x80 OK # 0x43: LMS1=0x84 LMS2=0x80 DIFF # 0x44: LMS1=0x0B LMS2=0x0B OK # 0x45: LMS1=0x00 LMS2=0x00 OK # 0x46: LMS1=0x00 LMS2=0x00 OK # 0x47: LMS1=0x40 LMS2=0x60 DIFF # 0x48: LMS1=0x0C LMS2=0x0C OK # 0x49: LMS1=0x0C LMS2=0x0C OK # 0x4A: LMS1=0x18 LMS2=0x18 OK # 0x4B: LMS1=0x50 LMS2=0x50 OK # 0x4C: LMS1=0x00 LMS2=0x00 OK # 0x4D: LMS1=0x00 LMS2=0x00 OK # 0x4E: LMS1=0x00 LMS2=0x01 DIFF # 0x4F: LMS1=0x01 LMS2=0x00 DIFF # 0x50: LMS1=0x1F LMS2=0x1F OK # 0x51: LMS1=0x00 LMS2=0x00 OK # 0x52: LMS1=0x1F LMS2=0x1F OK # 0x53: LMS1=0x08 LMS2=0x08 OK # 0x54: LMS1=0x02 LMS2=0x02 OK # 0x55: LMS1=0x1D LMS2=0x0C DIFF # 0x56: LMS1=0x70 LMS2=0x30 DIFF # 0x57: LMS1=0x94 LMS2=0x94 OK # 0x58: LMS1=0x00 LMS2=0x00 OK # 0x59: LMS1=0x09 LMS2=0x01 DIFF # 0x5A: LMS1=0x20 LMS2=0x20 OK # 0x5B: LMS1=0x00 LMS2=0x00 OK # 0x5C: LMS1=0x00 LMS2=0x00 OK # 0x5D: LMS1=0x40 LMS2=0x00 DIFF # 0x5E: LMS1=0x00 LMS2=0x00 OK # 0x5F: LMS1=0x1F LMS2=0x5F DIFF # 0x60: LMS1=0x1F LMS2=0x1F OK # 0x61: LMS1=0x00 LMS2=0x00 OK # 0x62: LMS1=0x1F LMS2=0x1F OK # 0x63: LMS1=0x08 LMS2=0x08 OK # 0x64: LMS1=0x32 LMS2=0x1E DIFF # 0x65: LMS1=0x01 LMS2=0x01 OK # 0x66: LMS1=0x00 LMS2=0x00 OK # 0x67: LMS1=0x00 LMS2=0x00 OK # 0x68: LMS1=0x01 LMS2=0x01 OK # 0x69: LMS1=0xF6 LMS2=0x89 DIFF # 0x6A: LMS1=0x2F LMS2=0x7E DIFF # 0x6B: LMS1=0x7B LMS2=0xBF DIFF # 0x6C: LMS1=0xEF LMS2=0xD4 DIFF # 0x6D: LMS1=0xAE LMS2=0x5F DIFF # 0x6E: LMS1=0x00 LMS2=0x00 OK # 0x6F: LMS1=0x00 LMS2=0x00 OK # 0x70: LMS1=0x01 LMS2=0x01 OK # 0x71: LMS1=0x80 LMS2=0x80 OK # 0x72: LMS1=0x80 LMS2=0x80 OK # 0x73: LMS1=0x00 LMS2=0x00 OK # 0x74: LMS1=0x00 LMS2=0x00 OK # 0x75: LMS1=0xD0 LMS2=0xD0 OK # 0x76: LMS1=0x78 LMS2=0x78 OK # 0x77: LMS1=0x00 LMS2=0x00 OK # 0x78: LMS1=0x1C LMS2=0x1C OK # 0x79: LMS1=0x37 LMS2=0x1C DIFF # 0x7A: LMS1=0x77 LMS2=0x77 OK # 0x7B: LMS1=0x77 LMS2=0x77 OK # 0x7C: LMS1=0x18 LMS2=0x18 OK # 0x7D: LMS1=0x00 LMS2=0x00 OK # 0x7E: LMS1=0x01 LMS2=0x10 DIFF # 0x7F: LMS1=0x00 LMS2=0x00 OK -------------- next part -------------- # 0x00: LMS1=0x1F LMS2=0x1F OK # 0x01: LMS1=0xE0 LMS2=0xE0 OK # 0x02: LMS1=0x1F LMS2=0x1F OK # 0x03: LMS1=0x08 LMS2=0x08 OK # 0x04: LMS1=0x22 LMS2=0x22 OK # 0x05: LMS1=0x32 LMS2=0x32 OK # 0x06: LMS1=0x0D LMS2=0x0D OK # 0x07: LMS1=0x00 LMS2=0x00 OK # 0x08: LMS1=0x00 LMS2=0x00 OK # 0x09: LMS1=0x40 LMS2=0x40 OK # 0x0A: LMS1=0x00 LMS2=0x00 OK # 0x0B: LMS1=0x08 LMS2=0x08 OK # 0x0C: LMS1=0x16 LMS2=0x21 DIFF # 0x0D: LMS1=0x2E LMS2=0x3D DIFF # 0x0E: LMS1=0x01 LMS2=0x01 OK # 0x0F: LMS1=0x00 LMS2=0x00 OK # 0x10: LMS1=0x41 LMS2=0x41 OK # 0x11: LMS1=0x20 LMS2=0x20 OK # 0x12: LMS1=0x00 LMS2=0x00 OK # 0x13: LMS1=0x00 LMS2=0x00 OK # 0x14: LMS1=0x88 LMS2=0x88 OK # 0x15: LMS1=0xB1 LMS2=0xB1 OK # 0x16: LMS1=0x8C LMS2=0x8C OK # 0x17: LMS1=0xE0 LMS2=0xE0 OK # 0x18: LMS1=0x40 LMS2=0x40 OK # 0x19: LMS1=0x94 LMS2=0x94 OK # 0x1A: LMS1=0x03 LMS2=0x03 OK # 0x1B: LMS1=0x76 LMS2=0x76 OK # 0x1C: LMS1=0x38 LMS2=0x38 OK # 0x1D: LMS1=0x40 LMS2=0x40 OK # 0x1E: LMS1=0x00 LMS2=0x00 OK # 0x1F: LMS1=0x00 LMS2=0x00 OK # 0x20: LMS1=0x41 LMS2=0x41 OK # 0x21: LMS1=0x20 LMS2=0x20 OK # 0x22: LMS1=0x00 LMS2=0x00 OK # 0x23: LMS1=0x00 LMS2=0x00 OK # 0x24: LMS1=0x88 LMS2=0x88 OK # 0x25: LMS1=0xB1 LMS2=0xB1 OK # 0x26: LMS1=0x8C LMS2=0x8C OK # 0x27: LMS1=0xE0 LMS2=0xE0 OK # 0x28: LMS1=0x40 LMS2=0x40 OK # 0x29: LMS1=0x94 LMS2=0x94 OK # 0x2A: LMS1=0x03 LMS2=0x03 OK # 0x2B: LMS1=0x76 LMS2=0x76 OK # 0x2C: LMS1=0x38 LMS2=0x38 OK # 0x2D: LMS1=0x40 LMS2=0x40 OK # 0x2E: LMS1=0x00 LMS2=0x00 OK # 0x2F: LMS1=0x00 LMS2=0x00 OK # 0x30: LMS1=0x1F LMS2=0x1F OK # 0x31: LMS1=0x00 LMS2=0x00 OK # 0x32: LMS1=0x1F LMS2=0x1F OK # 0x33: LMS1=0x08 LMS2=0x08 OK # 0x34: LMS1=0x02 LMS2=0x02 OK # 0x35: LMS1=0x0E LMS2=0x0C DIFF # 0x36: LMS1=0x30 LMS2=0x30 OK # 0x37: LMS1=0x41 LMS2=0xCA DIFF # 0x38: LMS1=0x8F LMS2=0x1E DIFF # 0x39: LMS1=0x5F LMS2=0x7D DIFF # 0x3A: LMS1=0xE5 LMS2=0x4F DIFF # 0x3B: LMS1=0x0F LMS2=0xCF DIFF # 0x3C: LMS1=0x7E LMS2=0xCE DIFF # 0x3D: LMS1=0x93 LMS2=0x0E DIFF # 0x3E: LMS1=0x40 LMS2=0x00 DIFF # 0x3F: LMS1=0x11 LMS2=0x00 DIFF # 0x40: LMS1=0x02 LMS2=0x02 OK # 0x41: LMS1=0x15 LMS2=0x15 OK # 0x42: LMS1=0x80 LMS2=0x80 OK # 0x43: LMS1=0x84 LMS2=0x80 DIFF # 0x44: LMS1=0x0B LMS2=0x0B OK # 0x45: LMS1=0x00 LMS2=0x00 OK # 0x46: LMS1=0x00 LMS2=0x00 OK # 0x47: LMS1=0x60 LMS2=0x60 OK # 0x48: LMS1=0x0C LMS2=0x0C OK # 0x49: LMS1=0x0C LMS2=0x0C OK # 0x4A: LMS1=0x18 LMS2=0x18 OK # 0x4B: LMS1=0x50 LMS2=0x50 OK # 0x4C: LMS1=0x00 LMS2=0x00 OK # 0x4D: LMS1=0x00 LMS2=0x00 OK # 0x4E: LMS1=0x00 LMS2=0x01 DIFF # 0x4F: LMS1=0x01 LMS2=0x00 DIFF # 0x50: LMS1=0x1F LMS2=0x1F OK # 0x51: LMS1=0x00 LMS2=0x00 OK # 0x52: LMS1=0x1F LMS2=0x1F OK # 0x53: LMS1=0x08 LMS2=0x08 OK # 0x54: LMS1=0x02 LMS2=0x02 OK # 0x55: LMS1=0x0C LMS2=0x0C OK # 0x56: LMS1=0x30 LMS2=0x30 OK # 0x57: LMS1=0x94 LMS2=0x94 OK # 0x58: LMS1=0x00 LMS2=0x00 OK # 0x59: LMS1=0x01 LMS2=0x01 OK # 0x5A: LMS1=0x20 LMS2=0x20 OK # 0x5B: LMS1=0x00 LMS2=0x00 OK # 0x5C: LMS1=0x00 LMS2=0x00 OK # 0x5D: LMS1=0x40 LMS2=0x00 DIFF # 0x5E: LMS1=0x00 LMS2=0x00 OK # 0x5F: LMS1=0x1F LMS2=0x5F DIFF # 0x60: LMS1=0x1F LMS2=0x1F OK # 0x61: LMS1=0x00 LMS2=0x00 OK # 0x62: LMS1=0x1F LMS2=0x1F OK # 0x63: LMS1=0x08 LMS2=0x08 OK # 0x64: LMS1=0x1E LMS2=0x1E OK # 0x65: LMS1=0x01 LMS2=0x01 OK # 0x66: LMS1=0x00 LMS2=0x00 OK # 0x67: LMS1=0x00 LMS2=0x00 OK # 0x68: LMS1=0x01 LMS2=0x01 OK # 0x69: LMS1=0xF6 LMS2=0x89 DIFF # 0x6A: LMS1=0x2F LMS2=0x7E DIFF # 0x6B: LMS1=0x5B LMS2=0xFF DIFF # 0x6C: LMS1=0xEF LMS2=0xD5 DIFF # 0x6D: LMS1=0xAE LMS2=0x5F DIFF # 0x6E: LMS1=0x00 LMS2=0x00 OK # 0x6F: LMS1=0x00 LMS2=0x00 OK # 0x70: LMS1=0x01 LMS2=0x01 OK # 0x71: LMS1=0x80 LMS2=0x80 OK # 0x72: LMS1=0x80 LMS2=0x80 OK # 0x73: LMS1=0x00 LMS2=0x00 OK # 0x74: LMS1=0x00 LMS2=0x00 OK # 0x75: LMS1=0xD0 LMS2=0xD0 OK # 0x76: LMS1=0x78 LMS2=0x78 OK # 0x77: LMS1=0x00 LMS2=0x00 OK # 0x78: LMS1=0x1C LMS2=0x1C OK # 0x79: LMS1=0x1C LMS2=0x1C OK # 0x7A: LMS1=0x77 LMS2=0x77 OK # 0x7B: LMS1=0x77 LMS2=0x77 OK # 0x7C: LMS1=0x18 LMS2=0x18 OK # 0x7D: LMS1=0x00 LMS2=0x00 OK # 0x7E: LMS1=0x01 LMS2=0x10 DIFF # 0x7F: LMS1=0x00 LMS2=0x00 OK -------------- next part -------------- # 0x00: LMS1=0x1F LMS2=0x1F OK # 0x01: LMS1=0xE0 LMS2=0xE0 OK # 0x02: LMS1=0x1F LMS2=0x1F OK # 0x03: LMS1=0x08 LMS2=0x08 OK # 0x04: LMS1=0x22 LMS2=0x22 OK # 0x05: LMS1=0x32 LMS2=0x32 OK # 0x06: LMS1=0x0D LMS2=0x0D OK # 0x07: LMS1=0x00 LMS2=0x00 OK # 0x08: LMS1=0x00 LMS2=0x00 OK # 0x09: LMS1=0x80 LMS2=0x40 DIFF # 0x0A: LMS1=0x00 LMS2=0x00 OK # 0x0B: LMS1=0x08 LMS2=0x08 OK # 0x0C: LMS1=0x16 LMS2=0x21 DIFF # 0x0D: LMS1=0x2E LMS2=0x3D DIFF # 0x0E: LMS1=0x01 LMS2=0x01 OK # 0x0F: LMS1=0x00 LMS2=0x00 OK # 0x10: LMS1=0x41 LMS2=0x41 OK # 0x11: LMS1=0x20 LMS2=0x20 OK # 0x12: LMS1=0x00 LMS2=0x00 OK # 0x13: LMS1=0x00 LMS2=0x00 OK # 0x14: LMS1=0x88 LMS2=0x88 OK # 0x15: LMS1=0xB1 LMS2=0xB1 OK # 0x16: LMS1=0x8C LMS2=0x8C OK # 0x17: LMS1=0xE0 LMS2=0xE0 OK # 0x18: LMS1=0x40 LMS2=0x40 OK # 0x19: LMS1=0x94 LMS2=0x94 OK # 0x1A: LMS1=0x03 LMS2=0x03 OK # 0x1B: LMS1=0x76 LMS2=0x76 OK # 0x1C: LMS1=0x38 LMS2=0x38 OK # 0x1D: LMS1=0x40 LMS2=0x40 OK # 0x1E: LMS1=0x00 LMS2=0x00 OK # 0x1F: LMS1=0x00 LMS2=0x00 OK # 0x20: LMS1=0x41 LMS2=0x41 OK # 0x21: LMS1=0x20 LMS2=0x20 OK # 0x22: LMS1=0x00 LMS2=0x00 OK # 0x23: LMS1=0x00 LMS2=0x00 OK # 0x24: LMS1=0x88 LMS2=0x88 OK # 0x25: LMS1=0xB1 LMS2=0xB1 OK # 0x26: LMS1=0x8C LMS2=0x8C OK # 0x27: LMS1=0xE3 LMS2=0xE0 DIFF # 0x28: LMS1=0x40 LMS2=0x40 OK # 0x29: LMS1=0x94 LMS2=0x94 OK # 0x2A: LMS1=0x03 LMS2=0x03 OK # 0x2B: LMS1=0x76 LMS2=0x76 OK # 0x2C: LMS1=0x38 LMS2=0x38 OK # 0x2D: LMS1=0x40 LMS2=0x40 OK # 0x2E: LMS1=0x00 LMS2=0x00 OK # 0x2F: LMS1=0x00 LMS2=0x00 OK # 0x30: LMS1=0x1F LMS2=0x1F OK # 0x31: LMS1=0x00 LMS2=0x00 OK # 0x32: LMS1=0x1F LMS2=0x1F OK # 0x33: LMS1=0x08 LMS2=0x08 OK # 0x34: LMS1=0x02 LMS2=0x02 OK # 0x35: LMS1=0x0E LMS2=0x0C DIFF # 0x36: LMS1=0x30 LMS2=0x30 OK # 0x37: LMS1=0x41 LMS2=0xCA DIFF # 0x38: LMS1=0x8F LMS2=0x1E DIFF # 0x39: LMS1=0x5F LMS2=0x7D DIFF # 0x3A: LMS1=0xE5 LMS2=0x4F DIFF # 0x3B: LMS1=0x0F LMS2=0xCF DIFF # 0x3C: LMS1=0x7E LMS2=0xCE DIFF # 0x3D: LMS1=0x93 LMS2=0x0E DIFF # 0x3E: LMS1=0x40 LMS2=0x00 DIFF # 0x3F: LMS1=0x11 LMS2=0x00 DIFF # 0x40: LMS1=0x02 LMS2=0x02 OK # 0x41: LMS1=0x15 LMS2=0x15 OK # 0x42: LMS1=0x80 LMS2=0x80 OK # 0x43: LMS1=0x84 LMS2=0x80 DIFF # 0x44: LMS1=0x0B LMS2=0x0B OK # 0x45: LMS1=0x00 LMS2=0x00 OK # 0x46: LMS1=0x00 LMS2=0x00 OK # 0x47: LMS1=0x40 LMS2=0x60 DIFF # 0x48: LMS1=0x0C LMS2=0x0C OK # 0x49: LMS1=0x0C LMS2=0x0C OK # 0x4A: LMS1=0x18 LMS2=0x18 OK # 0x4B: LMS1=0x50 LMS2=0x50 OK # 0x4C: LMS1=0x00 LMS2=0x00 OK # 0x4D: LMS1=0x00 LMS2=0x00 OK # 0x4E: LMS1=0x00 LMS2=0x01 DIFF # 0x4F: LMS1=0x01 LMS2=0x00 DIFF # 0x50: LMS1=0x1F LMS2=0x1F OK # 0x51: LMS1=0x00 LMS2=0x00 OK # 0x52: LMS1=0x1F LMS2=0x1F OK # 0x53: LMS1=0x08 LMS2=0x08 OK # 0x54: LMS1=0x02 LMS2=0x02 OK # 0x55: LMS1=0x0C LMS2=0x0C OK # 0x56: LMS1=0x30 LMS2=0x30 OK # 0x57: LMS1=0x94 LMS2=0x94 OK # 0x58: LMS1=0x00 LMS2=0x00 OK # 0x59: LMS1=0x09 LMS2=0x01 DIFF # 0x5A: LMS1=0x20 LMS2=0x20 OK # 0x5B: LMS1=0x00 LMS2=0x00 OK # 0x5C: LMS1=0x00 LMS2=0x00 OK # 0x5D: LMS1=0x40 LMS2=0x00 DIFF # 0x5E: LMS1=0x00 LMS2=0x00 OK # 0x5F: LMS1=0x1F LMS2=0x5F DIFF # 0x60: LMS1=0x1F LMS2=0x1F OK # 0x61: LMS1=0x00 LMS2=0x00 OK # 0x62: LMS1=0x1F LMS2=0x1F OK # 0x63: LMS1=0x08 LMS2=0x08 OK # 0x64: LMS1=0x32 LMS2=0x1E DIFF # 0x65: LMS1=0x01 LMS2=0x01 OK # 0x66: LMS1=0x00 LMS2=0x00 OK # 0x67: LMS1=0x00 LMS2=0x00 OK # 0x68: LMS1=0x01 LMS2=0x01 OK # 0x69: LMS1=0xF6 LMS2=0x89 DIFF # 0x6A: LMS1=0x2F LMS2=0x7E DIFF # 0x6B: LMS1=0x5B LMS2=0xFF DIFF # 0x6C: LMS1=0xEF LMS2=0xD5 DIFF # 0x6D: LMS1=0xAE LMS2=0x5F DIFF # 0x6E: LMS1=0x00 LMS2=0x00 OK # 0x6F: LMS1=0x00 LMS2=0x00 OK # 0x70: LMS1=0x01 LMS2=0x01 OK # 0x71: LMS1=0x80 LMS2=0x80 OK # 0x72: LMS1=0x80 LMS2=0x80 OK # 0x73: LMS1=0x00 LMS2=0x00 OK # 0x74: LMS1=0x00 LMS2=0x00 OK # 0x75: LMS1=0xD0 LMS2=0xD0 OK # 0x76: LMS1=0x78 LMS2=0x78 OK # 0x77: LMS1=0x00 LMS2=0x00 OK # 0x78: LMS1=0x1C LMS2=0x1C OK # 0x79: LMS1=0x37 LMS2=0x1C DIFF # 0x7A: LMS1=0x77 LMS2=0x77 OK # 0x7B: LMS1=0x77 LMS2=0x77 OK # 0x7C: LMS1=0x18 LMS2=0x18 OK # 0x7D: LMS1=0x00 LMS2=0x00 OK # 0x7E: LMS1=0x01 LMS2=0x10 DIFF # 0x7F: LMS1=0x00 LMS2=0x00 OK -------------- next part -------------- # 0x00: LMS1=0x1F LMS2=0x1F OK # 0x01: LMS1=0xE0 LMS2=0xE0 OK # 0x02: LMS1=0x1F LMS2=0x1F OK # 0x03: LMS1=0x08 LMS2=0x08 OK # 0x04: LMS1=0x22 LMS2=0x22 OK # 0x05: LMS1=0x3A LMS2=0x32 DIFF # 0x06: LMS1=0x0D LMS2=0x0D OK # 0x07: LMS1=0x00 LMS2=0x00 OK # 0x08: LMS1=0x00 LMS2=0x00 OK # 0x09: LMS1=0x81 LMS2=0x40 DIFF # 0x0A: LMS1=0x00 LMS2=0x00 OK # 0x0B: LMS1=0x08 LMS2=0x08 OK # 0x0C: LMS1=0x16 LMS2=0x21 DIFF # 0x0D: LMS1=0x2E LMS2=0x3D DIFF # 0x0E: LMS1=0x01 LMS2=0x01 OK # 0x0F: LMS1=0x00 LMS2=0x00 OK # 0x10: LMS1=0x41 LMS2=0x41 OK # 0x11: LMS1=0x20 LMS2=0x20 OK # 0x12: LMS1=0x00 LMS2=0x00 OK # 0x13: LMS1=0x00 LMS2=0x00 OK # 0x14: LMS1=0x88 LMS2=0x88 OK # 0x15: LMS1=0xB1 LMS2=0xB1 OK # 0x16: LMS1=0x8C LMS2=0x8C OK # 0x17: LMS1=0xE0 LMS2=0xE0 OK # 0x18: LMS1=0x40 LMS2=0x40 OK # 0x19: LMS1=0x94 LMS2=0x94 OK # 0x1A: LMS1=0x43 LMS2=0x03 DIFF # 0x1B: LMS1=0x76 LMS2=0x76 OK # 0x1C: LMS1=0x38 LMS2=0x38 OK # 0x1D: LMS1=0x40 LMS2=0x40 OK # 0x1E: LMS1=0x00 LMS2=0x00 OK # 0x1F: LMS1=0x00 LMS2=0x00 OK # 0x20: LMS1=0x41 LMS2=0x41 OK # 0x21: LMS1=0x20 LMS2=0x20 OK # 0x22: LMS1=0x00 LMS2=0x00 OK # 0x23: LMS1=0x00 LMS2=0x00 OK # 0x24: LMS1=0x88 LMS2=0x88 OK # 0x25: LMS1=0xB1 LMS2=0xB1 OK # 0x26: LMS1=0x8C LMS2=0x8C OK # 0x27: LMS1=0xE3 LMS2=0xE0 DIFF # 0x28: LMS1=0x40 LMS2=0x40 OK # 0x29: LMS1=0x94 LMS2=0x94 OK # 0x2A: LMS1=0x03 LMS2=0x03 OK # 0x2B: LMS1=0x76 LMS2=0x76 OK # 0x2C: LMS1=0x38 LMS2=0x38 OK # 0x2D: LMS1=0x40 LMS2=0x40 OK # 0x2E: LMS1=0x00 LMS2=0x00 OK # 0x2F: LMS1=0x00 LMS2=0x00 OK # 0x30: LMS1=0x1F LMS2=0x1F OK # 0x31: LMS1=0x01 LMS2=0x00 DIFF # 0x32: LMS1=0x1F LMS2=0x1F OK # 0x33: LMS1=0x08 LMS2=0x08 OK # 0x34: LMS1=0x02 LMS2=0x02 OK # 0x35: LMS1=0x0E LMS2=0x0C DIFF # 0x36: LMS1=0x30 LMS2=0x30 OK # 0x37: LMS1=0x41 LMS2=0xCA DIFF # 0x38: LMS1=0x8F LMS2=0x1E DIFF # 0x39: LMS1=0x5F LMS2=0x7D DIFF # 0x3A: LMS1=0xE5 LMS2=0x4F DIFF # 0x3B: LMS1=0x0F LMS2=0xCF DIFF # 0x3C: LMS1=0x7E LMS2=0xCE DIFF # 0x3D: LMS1=0x93 LMS2=0x0E DIFF # 0x3E: LMS1=0x40 LMS2=0x00 DIFF # 0x3F: LMS1=0x11 LMS2=0x00 DIFF # 0x40: LMS1=0x02 LMS2=0x02 OK # 0x41: LMS1=0x15 LMS2=0x15 OK # 0x42: LMS1=0x80 LMS2=0x80 OK # 0x43: LMS1=0x84 LMS2=0x80 DIFF # 0x44: LMS1=0x0B LMS2=0x0B OK # 0x45: LMS1=0x00 LMS2=0x00 OK # 0x46: LMS1=0x00 LMS2=0x00 OK # 0x47: LMS1=0x40 LMS2=0x60 DIFF # 0x48: LMS1=0x0C LMS2=0x0C OK # 0x49: LMS1=0x0C LMS2=0x0C OK # 0x4A: LMS1=0x18 LMS2=0x18 OK # 0x4B: LMS1=0x50 LMS2=0x50 OK # 0x4C: LMS1=0x00 LMS2=0x00 OK # 0x4D: LMS1=0x00 LMS2=0x00 OK # 0x4E: LMS1=0x00 LMS2=0x01 DIFF # 0x4F: LMS1=0x01 LMS2=0x00 DIFF # 0x50: LMS1=0x1F LMS2=0x1F OK # 0x51: LMS1=0x00 LMS2=0x00 OK # 0x52: LMS1=0x1F LMS2=0x1F OK # 0x53: LMS1=0x08 LMS2=0x08 OK # 0x54: LMS1=0x02 LMS2=0x02 OK # 0x55: LMS1=0x0C LMS2=0x0C OK # 0x56: LMS1=0x30 LMS2=0x30 OK # 0x57: LMS1=0x94 LMS2=0x94 OK # 0x58: LMS1=0x00 LMS2=0x00 OK # 0x59: LMS1=0x09 LMS2=0x01 DIFF # 0x5A: LMS1=0x20 LMS2=0x20 OK # 0x5B: LMS1=0x00 LMS2=0x00 OK # 0x5C: LMS1=0x00 LMS2=0x00 OK # 0x5D: LMS1=0x40 LMS2=0x00 DIFF # 0x5E: LMS1=0x00 LMS2=0x00 OK # 0x5F: LMS1=0x1F LMS2=0x5F DIFF # 0x60: LMS1=0x1F LMS2=0x1F OK # 0x61: LMS1=0x00 LMS2=0x00 OK # 0x62: LMS1=0x1F LMS2=0x1F OK # 0x63: LMS1=0x08 LMS2=0x08 OK # 0x64: LMS1=0x32 LMS2=0x1E DIFF # 0x65: LMS1=0x01 LMS2=0x01 OK # 0x66: LMS1=0x00 LMS2=0x00 OK # 0x67: LMS1=0x00 LMS2=0x00 OK # 0x68: LMS1=0x01 LMS2=0x01 OK # 0x69: LMS1=0xF6 LMS2=0x89 DIFF # 0x6A: LMS1=0x2F LMS2=0x7E DIFF # 0x6B: LMS1=0x5B LMS2=0xFF DIFF # 0x6C: LMS1=0xEF LMS2=0xD5 DIFF # 0x6D: LMS1=0xAE LMS2=0x5F DIFF # 0x6E: LMS1=0x00 LMS2=0x00 OK # 0x6F: LMS1=0x00 LMS2=0x00 OK # 0x70: LMS1=0x01 LMS2=0x01 OK # 0x71: LMS1=0x80 LMS2=0x80 OK # 0x72: LMS1=0x80 LMS2=0x80 OK # 0x73: LMS1=0x00 LMS2=0x00 OK # 0x74: LMS1=0x00 LMS2=0x00 OK # 0x75: LMS1=0xD0 LMS2=0xD0 OK # 0x76: LMS1=0x78 LMS2=0x78 OK # 0x77: LMS1=0x00 LMS2=0x00 OK # 0x78: LMS1=0x1C LMS2=0x1C OK # 0x79: LMS1=0x37 LMS2=0x1C DIFF # 0x7A: LMS1=0x77 LMS2=0x77 OK # 0x7B: LMS1=0x77 LMS2=0x77 OK # 0x7C: LMS1=0x18 LMS2=0x18 OK # 0x7D: LMS1=0x00 LMS2=0x00 OK # 0x7E: LMS1=0x01 LMS2=0x10 DIFF # 0x7F: LMS1=0x00 LMS2=0x00 OK -------------- next part -------------- # 0x00: LMS1=0x1D LMS2=0x1F DIFF # 0x01: LMS1=0xE9 LMS2=0xE0 DIFF # 0x02: LMS1=0x1F LMS2=0x1F OK # 0x03: LMS1=0x08 LMS2=0x08 OK # 0x04: LMS1=0x22 LMS2=0x22 OK # 0x05: LMS1=0x3A LMS2=0x32 DIFF # 0x06: LMS1=0x0D LMS2=0x0D OK # 0x07: LMS1=0x0F LMS2=0x00 DIFF # 0x08: LMS1=0x00 LMS2=0x00 OK # 0x09: LMS1=0x81 LMS2=0x40 DIFF # 0x0A: LMS1=0x00 LMS2=0x00 OK # 0x0B: LMS1=0x08 LMS2=0x08 OK # 0x0C: LMS1=0x16 LMS2=0x21 DIFF # 0x0D: LMS1=0x2E LMS2=0x3D DIFF # 0x0E: LMS1=0x01 LMS2=0x01 OK # 0x0F: LMS1=0x00 LMS2=0x00 OK # 0x10: LMS1=0x62 LMS2=0x41 DIFF # 0x11: LMS1=0x76 LMS2=0x20 DIFF # 0x12: LMS1=0x27 LMS2=0x00 DIFF # 0x13: LMS1=0x62 LMS2=0x00 DIFF # 0x14: LMS1=0x88 LMS2=0x88 OK # 0x15: LMS1=0xBD LMS2=0xB1 DIFF # 0x16: LMS1=0x8C LMS2=0x8C OK # 0x17: LMS1=0xE0 LMS2=0xE0 OK # 0x18: LMS1=0x40 LMS2=0x40 OK # 0x19: LMS1=0xAE LMS2=0x94 DIFF # 0x1A: LMS1=0x03 LMS2=0x03 OK # 0x1B: LMS1=0x76 LMS2=0x76 OK # 0x1C: LMS1=0x38 LMS2=0x38 OK # 0x1D: LMS1=0x40 LMS2=0x40 OK # 0x1E: LMS1=0x00 LMS2=0x00 OK # 0x1F: LMS1=0x00 LMS2=0x00 OK # 0x20: LMS1=0x41 LMS2=0x41 OK # 0x21: LMS1=0x20 LMS2=0x20 OK # 0x22: LMS1=0x00 LMS2=0x00 OK # 0x23: LMS1=0x00 LMS2=0x00 OK # 0x24: LMS1=0x88 LMS2=0x88 OK # 0x25: LMS1=0xB1 LMS2=0xB1 OK # 0x26: LMS1=0x8C LMS2=0x8C OK # 0x27: LMS1=0xE3 LMS2=0xE0 DIFF # 0x28: LMS1=0x40 LMS2=0x40 OK # 0x29: LMS1=0x94 LMS2=0x94 OK # 0x2A: LMS1=0x03 LMS2=0x03 OK # 0x2B: LMS1=0x76 LMS2=0x76 OK # 0x2C: LMS1=0x38 LMS2=0x38 OK # 0x2D: LMS1=0x40 LMS2=0x40 OK # 0x2E: LMS1=0x00 LMS2=0x00 OK # 0x2F: LMS1=0x00 LMS2=0x00 OK # 0x30: LMS1=0x21 LMS2=0x1F DIFF # 0x31: LMS1=0x09 LMS2=0x00 DIFF # 0x32: LMS1=0x1F LMS2=0x1F OK # 0x33: LMS1=0x09 LMS2=0x08 DIFF # 0x34: LMS1=0x02 LMS2=0x02 OK # 0x35: LMS1=0x1D LMS2=0x0C DIFF # 0x36: LMS1=0x70 LMS2=0x30 DIFF # 0x37: LMS1=0x41 LMS2=0xCA DIFF # 0x38: LMS1=0x8F LMS2=0x1E DIFF # 0x39: LMS1=0x5F LMS2=0x7D DIFF # 0x3A: LMS1=0xE5 LMS2=0x4F DIFF # 0x3B: LMS1=0x0F LMS2=0xCF DIFF # 0x3C: LMS1=0x7E LMS2=0xCE DIFF # 0x3D: LMS1=0x93 LMS2=0x0E DIFF # 0x3E: LMS1=0x40 LMS2=0x00 DIFF # 0x3F: LMS1=0x11 LMS2=0x00 DIFF # 0x40: LMS1=0x02 LMS2=0x02 OK # 0x41: LMS1=0x15 LMS2=0x15 OK # 0x42: LMS1=0x80 LMS2=0x80 OK # 0x43: LMS1=0x84 LMS2=0x80 DIFF # 0x44: LMS1=0x0B LMS2=0x0B OK # 0x45: LMS1=0x00 LMS2=0x00 OK # 0x46: LMS1=0x00 LMS2=0x00 OK # 0x47: LMS1=0x40 LMS2=0x60 DIFF # 0x48: LMS1=0x0C LMS2=0x0C OK # 0x49: LMS1=0x0C LMS2=0x0C OK # 0x4A: LMS1=0x18 LMS2=0x18 OK # 0x4B: LMS1=0x50 LMS2=0x50 OK # 0x4C: LMS1=0x00 LMS2=0x00 OK # 0x4D: LMS1=0x00 LMS2=0x00 OK # 0x4E: LMS1=0x00 LMS2=0x01 DIFF # 0x4F: LMS1=0x01 LMS2=0x00 DIFF # 0x50: LMS1=0x1F LMS2=0x1F OK # 0x51: LMS1=0x00 LMS2=0x00 OK # 0x52: LMS1=0x1F LMS2=0x1F OK # 0x53: LMS1=0x08 LMS2=0x08 OK # 0x54: LMS1=0x02 LMS2=0x02 OK # 0x55: LMS1=0x1D LMS2=0x0C DIFF # 0x56: LMS1=0x70 LMS2=0x30 DIFF # 0x57: LMS1=0x94 LMS2=0x94 OK # 0x58: LMS1=0x00 LMS2=0x00 OK # 0x59: LMS1=0x09 LMS2=0x01 DIFF # 0x5A: LMS1=0x20 LMS2=0x20 OK # 0x5B: LMS1=0x00 LMS2=0x00 OK # 0x5C: LMS1=0x00 LMS2=0x00 OK # 0x5D: LMS1=0x40 LMS2=0x00 DIFF # 0x5E: LMS1=0x00 LMS2=0x00 OK # 0x5F: LMS1=0x1F LMS2=0x5F DIFF # 0x60: LMS1=0x1F LMS2=0x1F OK # 0x61: LMS1=0x00 LMS2=0x00 OK # 0x62: LMS1=0x1F LMS2=0x1F OK # 0x63: LMS1=0x08 LMS2=0x08 OK # 0x64: LMS1=0x32 LMS2=0x1E DIFF # 0x65: LMS1=0x01 LMS2=0x01 OK # 0x66: LMS1=0x00 LMS2=0x00 OK # 0x67: LMS1=0x00 LMS2=0x00 OK # 0x68: LMS1=0x01 LMS2=0x01 OK # 0x69: LMS1=0xF6 LMS2=0x89 DIFF # 0x6A: LMS1=0x2F LMS2=0x7E DIFF # 0x6B: LMS1=0x5B LMS2=0xFF DIFF # 0x6C: LMS1=0xEF LMS2=0xD5 DIFF # 0x6D: LMS1=0xAE LMS2=0x5F DIFF # 0x6E: LMS1=0x00 LMS2=0x00 OK # 0x6F: LMS1=0x00 LMS2=0x00 OK # 0x70: LMS1=0x01 LMS2=0x01 OK # 0x71: LMS1=0x80 LMS2=0x80 OK # 0x72: LMS1=0x80 LMS2=0x80 OK # 0x73: LMS1=0x00 LMS2=0x00 OK # 0x74: LMS1=0x00 LMS2=0x00 OK # 0x75: LMS1=0xD0 LMS2=0xD0 OK # 0x76: LMS1=0x78 LMS2=0x78 OK # 0x77: LMS1=0x00 LMS2=0x00 OK # 0x78: LMS1=0x1C LMS2=0x1C OK # 0x79: LMS1=0x37 LMS2=0x1C DIFF # 0x7A: LMS1=0x77 LMS2=0x77 OK # 0x7B: LMS1=0x77 LMS2=0x77 OK # 0x7C: LMS1=0x18 LMS2=0x18 OK # 0x7D: LMS1=0x00 LMS2=0x00 OK # 0x7E: LMS1=0x01 LMS2=0x10 DIFF # 0x7F: LMS1=0x00 LMS2=0x00 OK From andrey.sviyazov at fairwaves.ru Sun Jul 22 20:48:26 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Mon, 23 Jul 2012 00:48:26 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Thomas. Could you please make an file from the OpenBTS stream as an cycled sequence to use with tx_samples_from_file.exe. I would like to test my UmTRX under windows with good instrument in Moscow (I hope to find it soon). Best regards, Andrey Sviyazov. 2012/7/23 Thomas Tsou > On Sun, Jul 22, 2012 at 3:27 PM, Alexander Chemeris > wrote: > > On Sun, Jul 22, 2012 at 11:11 PM, Thomas Tsou > wrote: > >> On Sun, Jul 22, 2012 at 10:12 AM, Andrey Sviyazov > >> wrote: > >>> Hi Thomas. > >>> > >>> It is very good new. > >>> Please let us know more information how you wins! > >>> I mean which PLL filter, ICP and other LMS paremeters do you use or > its done > >>> by just only IQ balance correction and Laurent C1 pulse and all other > by > >>> default? > >> > >> Register dump and startup sequence are attached. > > > > Uhm, this is a register dump at what time? Originally I asked for the > > dump before and after every line in the umtrx_tx_init.sh. > > That was for Andrey. That dump was taken during the previous 945 MHz > measurement. > > These dumps are for the calibration failure, which are taken at the > following points. > > 0 > ./umtrx_lms.py --lms 1 --lms-init > 1 > ./umtrx_lms.py --lms 1 --lms-tx-enable 1 > 2 > ./umtrx_lms.py --lms 1 --pll-ref-clock 26e6 --lpf-bandwidth-code > 0x0f --lms-auto-calibration > 3 > > >> LO leakage was also recalibrated for different frequencies. > > > > How different are calibration values? I've never checked how is it > > related to the PLL frequency. > > A single value within 900 MHz. At 1900 MHz it's maybe up to 3 or 4. LO > leakage is easy to calibrate though. IQ calibration is rather tedious > - calibration values at 900 MHz are useless at 1900 MHz. > > >> For comparison, after C1 pulse is added USRP1 is 1.3/3.5 and USRP2 is > >> 1.2/3.0 when measured at 925 MHz. > > > > tip: Would be great if you push this to github just as you send e-mail :) > > I'm posting the measurement captures and the Matlab for the pulse > sequence generation. The transceiver code is pretty ugly right now. > There are many stuffing bits and zero padding added to minimize the > start / end error on the E4406. It may not even work with real phones > now. > > > PS Sylvain is waiting for a howto to run OpenBTS with UmTRX to test his > setup. > > I'll hack something together later tonight. Can he receive a tone? If > yes, then everything else is straightforward. > > Thomas > -------------- next part -------------- An HTML attachment was scrubbed... URL: From thomastsou at gmail.com Sun Jul 22 21:30:24 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Sun, 22 Jul 2012 17:30:24 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sun, Jul 22, 2012 at 4:48 PM, Andrey Sviyazov wrote: > Hi Thomas. > > Could you please make an file from the OpenBTS stream as an cycled sequence > to use with tx_samples_from_file.exe. > I would like to test my UmTRX under windows with good instrument in Moscow > (I hope to find it soon). OpenBTS output written to file at 4 sps / 1083.333 ksps. Tested on E4406. https://github.com/downloads/ttsou/openbts-p2.8/capture.dat Thomas From thomastsou at gmail.com Sun Jul 22 22:17:34 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Sun, 22 Jul 2012 18:17:34 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Sun, Jul 22, 2012 at 3:21 PM, Alexander Chemeris wrote: > On Sun, Jul 22, 2012 at 10:51 PM, Thomas Tsou wrote: >> Overall measurements are close (either above or below) to 1.5/5 for >> the 900 band in general. 945 MHz is currently the best case, but that >> is the frequency I spent the most time on with calibration. Do we need >> to be consistently below 1.5/5 or just close? > > Thanks for the measurements. At the end we should be below that at all > GSM bands. For now it's fine to be close. > > I also noticed that your frequency is far off - could you calibrate it > and make pictures of the best and worst case in the 900 band? Perhaps this is a silly question, but how do I calibrate the clock? or use an external reference signal? > And just to be sure - could you check what TCXO do you have on the > UmTRX? It should be TCD4029-26.0M, probably marked like PLEU4030Z. 2600 028 PLEU 4030Z Thomas From 246tnt at gmail.com Sun Jul 22 22:23:34 2012 From: 246tnt at gmail.com (Sylvain Munaut) Date: Mon, 23 Jul 2012 00:23:34 +0200 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: > Perhaps this is a silly question, but how do I calibrate the clock? or > use an external reference signal? Plug a GPS antenna, wait for 5 min or so ... Cheers, Sylvain From alexander.chemeris at gmail.com Mon Jul 23 02:40:16 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Mon, 23 Jul 2012 06:40:16 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Mon, Jul 23, 2012 at 3:07 AM, Thomas Tsou wrote: > On Jul 22, 2012 6:23 PM, "Sylvain Munaut" <246tnt at gmail.com> wrote: >> >> > Perhaps this is a silly question, but how do I calibrate the clock? or >> > use an external reference signal? >> >> Plug a GPS antenna, wait for 5 min or so ... > > That is rather challenging indoors. > > Let me find out what antennas are on the roof. I'll just retune the LMS in > the meantime. You could also use host/utils/umtrx_vcxo.py to tune it manually. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Mon Jul 23 02:44:00 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Mon, 23 Jul 2012 06:44:00 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Mon, Jul 23, 2012 at 2:37 AM, Andrey Sviyazov wrote: > Thomas, thanks for file. > But, may be you know, how to convert it to *.cfile for > tx_samples_from_file.exe? > Here attached zip with example of *.cfile which Alexander made for me in > somewhere like MathLab, I think so. > Rename zi_ to zip first. > > Alexander, may be you know and then you can convert this file or part of it? You do not need to convert, AFAIK. >> >> Overall measurements are close (either above or below) to 1.5/5 for >> >> the 900 band in general. 945 MHz is currently the best case, but that >> >> is the frequency I spent the most time on with calibration. Do we need >> >> to be consistently below 1.5/5 or just close? >> > >> > Thanks for the measurements. At the end we should be below that at all >> > GSM bands. For now it's fine to be close. >> > >> > I also noticed that your frequency is far off - could you calibrate it >> > and make pictures of the best and worst case in the 900 band? >> >> Perhaps this is a silly question, but how do I calibrate the clock? or >> use an external reference signal? > > > Actually you can tune LMS frequensy with 1Hz step to compensate known error. This won't produce correct symbol speed. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Mon Jul 23 03:17:07 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Mon, 23 Jul 2012 07:17:07 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Mon, Jul 23, 2012 at 2:17 AM, Thomas Tsou wrote: > On Sun, Jul 22, 2012 at 3:21 PM, Alexander Chemeris > wrote: >> On Sun, Jul 22, 2012 at 10:51 PM, Thomas Tsou wrote: >>> Overall measurements are close (either above or below) to 1.5/5 for >>> the 900 band in general. 945 MHz is currently the best case, but that >>> is the frequency I spent the most time on with calibration. Do we need >>> to be consistently below 1.5/5 or just close? >> >> Thanks for the measurements. At the end we should be below that at all >> GSM bands. For now it's fine to be close. >> >> I also noticed that your frequency is far off - could you calibrate it >> and make pictures of the best and worst case in the 900 band? > > Perhaps this is a silly question, but how do I calibrate the clock? or > use an external reference signal? Andrey Sviyazov - does ClockIn works as external input in UmTRXv1? >> And just to be sure - could you check what TCXO do you have on the >> UmTRX? It should be TCD4029-26.0M, probably marked like PLEU4030Z. > > 2600 028 > PLEU 4030Z Ok, the correct one. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From ttsou at vt.edu Sun Jul 22 23:07:27 2012 From: ttsou at vt.edu (Thomas Tsou) Date: Sun, 22 Jul 2012 19:07:27 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Jul 22, 2012 6:23 PM, "Sylvain Munaut" <246tnt at gmail.com> wrote: > > > Perhaps this is a silly question, but how do I calibrate the clock? or > > use an external reference signal? > > Plug a GPS antenna, wait for 5 min or so ... That is rather challenging indoors. Let me find out what antennas are on the roof. I'll just retune the LMS in the meantime. Thomas -------------- next part -------------- An HTML attachment was scrubbed... URL: From andrey.sviyazov at fairwaves.ru Sun Jul 22 22:37:42 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Mon, 23 Jul 2012 02:37:42 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Thomas, thanks for file. But, may be you know, how to convert it to *.cfile for tx_samples_from_file.exe? Here attached zip with example of *.cfile which Alexander made for me in somewhere like MathLab, I think so. Rename zi_ to zip first. Alexander, may be you know and then you can convert this file or part of it? >> Overall measurements are close (either above or below) to 1.5/5 for > >> the 900 band in general. 945 MHz is currently the best case, but that > >> is the frequency I spent the most time on with calibration. Do we need > >> to be consistently below 1.5/5 or just close? > > > > Thanks for the measurements. At the end we should be below that at all > > GSM bands. For now it's fine to be close. > > > > I also noticed that your frequency is far off - could you calibrate it > > and make pictures of the best and worst case in the 900 band? > > Perhaps this is a silly question, but how do I calibrate the clock? or > use an external reference signal? > Actually you can tune LMS frequensy with 1Hz step to compensate known error. Best regards, Andrey Sviyazov. -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: tx_samples_from_file.zi_ Type: application/octet-stream Size: 827192 bytes Desc: not available URL: From andrey.sviyazov at fairwaves.ru Mon Jul 23 06:17:42 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Mon, 23 Jul 2012 10:17:42 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: > > Perhaps this is a silly question, but how do I calibrate the clock? or > > use an external reference signal? > > Andrey Sviyazov - does ClockIn works as external input in UmTRXv1? Yes, 5V cmos level required or smaller with DC offset to get 2.5V symmetry. Turn switches to MHz and slave positions. Best regards, Andrey Sviyazov. (Sent from my mobile client) -------------- next part -------------- An HTML attachment was scrubbed... URL: From s.milenkovic at limemicro.com Mon Jul 23 09:30:32 2012 From: s.milenkovic at limemicro.com (Srdjan Milenkovic) Date: Mon, 23 Jul 2012 10:30:32 +0100 Subject: Improving LMS6002 phase noise In-Reply-To: References: <500ABDB7.40001@limemicro.com> <500BDFFB.7050806@limemicro.com> <500C1E87.2090106@limemicro.com> Message-ID: <500D19B8.5010703@limemicro.com> Hi Andrey, Below is the loop filter for 100kHz loop bandwidth, 26MHz reference clock, 400uA charge pump current. It has been tested and should give you around -90dBc/Hz plateau. C1 R2 C2 R3 C3 9.01E-11 2.46E+03 1.42E-09 3280.93 2.56E-11 Loop filter components for 10kHz bandwidth, 26MHz reference clock, 400uA charge pump current are below: C1 R2 C2 R3 C3 9.01E-09 2.46E+02 1.42E-07 328.09 2.56E-09 There should not be any issue with loop stability even with 10kHz filter. However, PLL settling time is increased so you have to slow down VCOCAP auto-tune. I would recommend to use 100kHz filter. Regards, Srdjan On 22/07/2012 20:53, Andrey Sviyazov wrote: > Hi Srdjan. > > First of all thank you for support. > > We do not have register dump. However, Lime GUI project file used > in this experiment is attached. You can use GUI File->Open Project > option to import it. I see Ichp and Ichp offset currents are > different from defaults but these still do not justify 5-12dB > worse PN in your reports. You can give it a try though before > changing TCXCO. > > > We will try to adjust Ichp and offset first off all. Thank you for hint. > > *Test Description:* > > * DC MAX applied through analogue inputs, DACs off > > It is quite important detail too. > > * TXVGA1 and TXVGA2 at max gain > > Similar. > > * Loop filter redesigned for 100kHz loop bandwidth and 40MHz > reference > > * Icp and Icp offset optimized at 25 deg. Same set up used at > all other temperatures > > Please inform us values of components for 100kHz BW filter. > But we are forced to use one clock 26MHz for all because of target price. > > * Cap code and VCO picked up by PLL tune routine > > I implemented 10kHz BW filter for PLL and found that frequency locking > become unstable because of calculated VCOCAP value a bit lower then > required (too high capacity). > If VCOCAP incremented manualy (after auto-tuned) then no any problems. > What do you think about it. > And could you please inform me values for 10 kHz BW filter, just to > compare with my calculations. > > Best regards, > Andrey Sviyazov. > > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: adibgfic.png Type: image/png Size: 7290 bytes Desc: not available URL: From andrey.sviyazov at fairwaves.ru Mon Jul 23 18:44:10 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Mon, 23 Jul 2012 22:44:10 +0400 Subject: Improving LMS6002 phase noise In-Reply-To: <500D19B8.5010703@limemicro.com> References: <500ABDB7.40001@limemicro.com> <500BDFFB.7050806@limemicro.com> <500C1E87.2090106@limemicro.com> <500D19B8.5010703@limemicro.com> Message-ID: Hi Srdjan. Today I found why noises and spurs are really happens in UmTRXv1. 1) Only full disabling (no power) GPS module can kill all near spurs. 2) To get good noises the next changes are required: - replace choke L6 by capacitor 10nF..0.1uF. - remove C45. I've assembled 100kHz loop filter with the next components: C82 = 100pF, C83=1500pF, C84=33pF, R106=2.2k, R109=3.3k. Result without GPS for IChP=0.4mA and due to several XO attached here. Also attached comparison of 50kHz/100kHz loop filters with optimal IChp 1.2mA/0.4mA but with GPS module (no antenna). So, now we need to measure integrated LO noise (degrees) to understand which filter and IChP better. Best regards, Andrey Sviyazov. 2012/7/23 Srdjan Milenkovic > Hi Andrey, > > Below is the loop filter for 100kHz loop bandwidth, 26MHz reference clock, > 400uA charge pump current. It has been tested and should give you around > -90dBc/Hz plateau. > > > > C1 R2 C2 R3 C3 9.01E-11 2.46E+03 1.42E-09 3280.93 2.56E-11 > > Loop filter components for 10kHz bandwidth, 26MHz reference clock, 400uA > charge pump current are below: > > C1 R2 C2 R3 C3 9.01E-09 2.46E+02 1.42E-07 328.09 2.56E-09 > There should not be any issue with loop stability even with 10kHz filter. > However, PLL settling time is increased so you have to slow down VCOCAP > auto-tune. > > I would recommend to use 100kHz filter. > > Regards, Srdjan > > > **** **** > On 22/07/2012 20:53, Andrey Sviyazov wrote: > > Hi Srdjan. > > First of all thank you for support. > > We do not have register dump. However, Lime GUI project file used in >> this experiment is attached. You can use GUI File->Open Project option to >> import it. I see Ichp and Ichp offset currents are different from defaults >> but these still do not justify 5-12dB worse PN in your reports. You can >> give it a try though before changing TCXCO. >> > > We will try to adjust Ichp and offset first off all. Thank you for hint. > > *Test Description:* >> >> - DC MAX applied through analogue inputs, DACs off >> >> It is quite important detail too. > >> >> >> >> - TXVGA1 and TXVGA2 at max gain >> >> Similar. > >> >> >> >> - Loop filter redesigned for 100kHz loop bandwidth and 40MHz reference >> >> >> - Icp and Icp offset optimized at 25 deg. Same set up used at all >> other temperatures >> >> Please inform us values of components for 100kHz BW filter. > But we are forced to use one clock 26MHz for all because of target price. > >> >> >> >> - Cap code and VCO picked up by PLL tune routine >> >> I implemented 10kHz BW filter for PLL and found that frequency locking > become unstable because of calculated VCOCAP value a bit lower then > required (too high capacity). > If VCOCAP incremented manualy (after auto-tuned) then no any problems. > What do you think about it. > And could you please inform me values for 10 kHz BW filter, just to > compare with my calculations. > > Best regards, > Andrey Sviyazov. > > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: TxLO noise at PLL_BW 100kHz due XO.png Type: image/png Size: 39764 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: TxLO noise depend PLL_BW50-100.png Type: image/png Size: 36952 bytes Desc: not available URL: From thomastsou at gmail.com Mon Jul 23 18:54:17 2012 From: thomastsou at gmail.com (Thomas Tsou) Date: Mon, 23 Jul 2012 14:54:17 -0400 Subject: OpenBTS with UmTRX Message-ID: Google project hosting is currently read only for network maintenance. Here are general OpenBTS / UmTRX setup instructions. I'll post them when write access is restored. Download ======= UHD git://github.com/chemeris/UHD-Fairwaves.git fairwaves/umtrx-dboard OpenBTS git://github.com/ttsou/openbts-p2.8 umtrx Follow standard build instructions. http://files.ettus.com/uhd_docs/manual/html/build.html http://wush.net/trac/rangepublic/wiki/BuildInstallRun UmTRX Setup =========== Configuration of the LMS6003D is through the control script 'umtrx_lms.py', which is installed in '/usr/local/share/uhd/utils'. Calibration prior to operation is strongly recommended. Example setup for ARFCN 925: Initialization and auto-calibration: ./umtrx_lms.py --lms 1 --lms-init ./umtrx_lms.py --lms 1 --lms-tx-enable 1 ./umtrx_lms.py --lms 1 --lms-rx-enable 1 ./umtrx_lms.py --lms 1 --pll-ref-clock 26e6 --lpf-bandwidth-code 0x0f --lms-auto-calibration RX LNA and RXVGA2 selection and gain control ./umtrx_lms.py --lms 1 --reg 0x75 --data 0xf0 ./umtrx_lms.py --lms 1 --reg 0x65 --data 10 TX LPF control ./umtrx_lms.py --lms 1 --reg 0x34 --data 0x3e LO leakage cancellation (calibration data values may vary) ./umtrx_lms.py --lms 1 --reg 0x42 --data 0x67 ./umtrx_lms.py --lms 1 --reg 0x43 --data 0x89 TX/RX PLL charge pump current ./umtrx_lms.py --lms 1 --reg 0x16 --data 0x93 Tuning ./umtrx_lms.py --lms 1 --lms-rx-pll-tune 925.2e6 ./umtrx_lms.py --lms 1 --lms-tx-pll-tune 880.2e6 TXVGA2 gain to max and enable PA ./umtrx_lms.py --lms 1 --reg 0x45 --data 0xc8 ./umtrx_lms.py --lms 1 --lms-pa-on 2 Running OpenBTS ============== Follow standard instructions. http://wush.net/trac/rangepublic/wiki/BuildInstallRun Thomas From s.milenkovic at limemicro.com Mon Jul 23 19:43:03 2012 From: s.milenkovic at limemicro.com (Srdjan Milenkovic) Date: Mon, 23 Jul 2012 20:43:03 +0100 Subject: Improving LMS6002 phase noise In-Reply-To: References: <500ABDB7.40001@limemicro.com> <500BDFFB.7050806@limemicro.com> <500C1E87.2090106@limemicro.com> <500D19B8.5010703@limemicro.com> Message-ID: <500DA947.1060105@limemicro.com> Hi Andrey, Plots are looking good. Just for your information, we reduced Ichp to 400uA to reduce close to integer i.e. fractional spurs which you may have not seen yet but they are there. These have noting to do with GPS module on UmTRX board neither with LMS chip, it is just PLL nature. Please be aware of this while comparing different loop filters, especially different Ichp values, ... Best regards, Srdjan On 23/07/2012 19:44, Andrey Sviyazov wrote: > Hi Srdjan. > > Today I found why noises and spurs are really happens in UmTRXv1. > > 1) Only full disabling (no power) GPS module can kill all near spurs. > 2) To get good noises the next changes are required: > - replace choke L6 by capacitor 10nF..0.1uF. > - remove C45. > > I've assembled 100kHz loop filter with the next components: > C82 = 100pF, C83=1500pF, C84=33pF, R106=2.2k, R109=3.3k. > > Result without GPS for IChP=0.4mA and due to several XO attached here. > Also attached comparison of 50kHz/100kHz loop filters with optimal > IChp 1.2mA/0.4mA but with GPS module (no antenna). > So, now we need to measure integrated LO noise (degrees) to understand > which filter and IChP better. > > Best regards, > Andrey Sviyazov. > > > > > 2012/7/23 Srdjan Milenkovic > > > Hi Andrey, > > Below is the loop filter for 100kHz loop bandwidth, 26MHz > reference clock, 400uA charge pump current. It has been tested and > should give you around -90dBc/Hz plateau. > > > > C1 R2 C2 R3 C3 > > 9.01E-11 2.46E+03 1.42E-09 3280.93 2.56E-11 > > > > Loop filter components for 10kHz bandwidth, 26MHz reference clock, > 400uA charge pump current are below: > > C1 R2 C2 R3 C3 > > 9.01E-09 2.46E+02 1.42E-07 328.09 2.56E-09 > > > There should not be any issue with loop stability even with 10kHz > filter. However, PLL settling time is increased so you have to > slow down VCOCAP auto-tune. > > I would recommend to use 100kHz filter. > > Regards, Srdjan > > > On 22/07/2012 20:53, Andrey Sviyazov wrote: >> Hi Srdjan. >> >> First of all thank you for support. >> >> We do not have register dump. However, Lime GUI project file >> used in this experiment is attached. You can use GUI >> File->Open Project option to import it. I see Ichp and Ichp >> offset currents are different from defaults but these still >> do not justify 5-12dB worse PN in your reports. You can give >> it a try though before changing TCXCO. >> >> >> We will try to adjust Ichp and offset first off all. Thank you >> for hint. >> >> *Test Description:* >> >> * DC MAX applied through analogue inputs, DACs off >> >> It is quite important detail too. >> >> * TXVGA1 and TXVGA2 at max gain >> >> Similar. >> >> * Loop filter redesigned for 100kHz loop bandwidth and >> 40MHz reference >> >> * Icp and Icp offset optimized at 25 deg. Same set up used >> at all other temperatures >> >> Please inform us values of components for 100kHz BW filter. >> But we are forced to use one clock 26MHz for all because of >> target price. >> >> * Cap code and VCO picked up by PLL tune routine >> >> I implemented 10kHz BW filter for PLL and found that frequency >> locking become unstable because of calculated VCOCAP value a bit >> lower then required (too high capacity). >> If VCOCAP incremented manualy (after auto-tuned) then no any >> problems. >> What do you think about it. >> And could you please inform me values for 10 kHz BW filter, just >> to compare with my calculations. >> >> Best regards, >> Andrey Sviyazov. >> >> > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From Alexander.Chemeris at fairwaves.ru Mon Jul 23 20:25:16 2012 From: Alexander.Chemeris at fairwaves.ru (Alexander Chemeris) Date: Tue, 24 Jul 2012 00:25:16 +0400 Subject: Improving LMS6002 phase noise In-Reply-To: References: <500ABDB7.40001@limemicro.com> <500BDFFB.7050806@limemicro.com> <500C1E87.2090106@limemicro.com> <500D19B8.5010703@limemicro.com> Message-ID: Hi Andrey, On Mon, Jul 23, 2012 at 10:44 PM, Andrey Sviyazov wrote: > Today I found why noises and spurs are really happens in UmTRXv1. Finally, we could say UmTRX is good at phase noise. > 1) Only full disabling (no power) GPS module can kill all near spurs. I wonder whether EB-570 is any better. And if EB-570 is no better - how could we protect LMS from this noise? > 2) To get good noises the next changes are required: > - replace choke L6 by capacitor 10nF..0.1uF. > - remove C45. Is it possible to apply those changes for UmTRXv2 without PCB changes? -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From Alexander.Chemeris at fairwaves.ru Mon Jul 23 20:32:32 2012 From: Alexander.Chemeris at fairwaves.ru (Alexander Chemeris) Date: Tue, 24 Jul 2012 00:32:32 +0400 Subject: Improving LMS6002 phase noise In-Reply-To: References: <500ABDB7.40001@limemicro.com> <500BDFFB.7050806@limemicro.com> <500C1E87.2090106@limemicro.com> <500D19B8.5010703@limemicro.com> Message-ID: On Tue, Jul 24, 2012 at 12:25 AM, Alexander Chemeris wrote: > Hi Andrey, > > On Mon, Jul 23, 2012 at 10:44 PM, Andrey Sviyazov > wrote: >> Today I found why noises and spurs are really happens in UmTRXv1. > > Finally, we could say UmTRX is good at phase noise. > >> 1) Only full disabling (no power) GPS module can kill all near spurs. > > I wonder whether EB-570 is any better. And if EB-570 is no better - > how could we protect LMS from this noise? > >> 2) To get good noises the next changes are required: >> - replace choke L6 by capacitor 10nF..0.1uF. >> - remove C45. > > Is it possible to apply those changes for UmTRXv2 without PCB changes? PS Please add both points to the tracker, so we don't forget. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From andreysviyaz at gmail.com Mon Jul 23 20:47:28 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Tue, 24 Jul 2012 00:47:28 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Jean-Samuel. Please let me know fabrication progress, a specially PCB. I ask you because of few changes required to improve LMS phase noises. BOM required changes in passive components only. If PCB doesn't yet ordered, then possible I'll make changes too. Best regards, Andrey Sviyazov. (Sent from my mobile client) 04.07.2012 20:01 ???????????? "Jean-Samuel Najnudel - BJT PARTNERS SARL" < jsn at bjtpartners.com> ???????: > Hi Andrey, > > Thank you very much for your help. > > I will forward this to the fab. > Yes, you are all right, the FBMH2012HM121-T price is much better than the > MLB-201209-0120PU. However, availability on Farnell France is not as good > as the MLB-201209-0120PU. Price difference is quite big but we only use 5 > beads per boards. Difference makes only about 1 euro per board. I will let > the fab decide between these 2 references. > > Best regards. > > Jean-Samuel. > :-) > > > On Wed, Jul 4, 2012 at 4:30 PM, Andrey Sviyazov wrote: > >> Hi Jean-Samuel. >> >> Yes, you are all right and you can order TDK - MPZ1608S601A instead of >> MLB-160808-0600PL. >> And also possible to use 3 times cheaper FBMH2012HM121-T, 0805, 2.5A instead >> of MLB-201209-0120PU. >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >> >>> Hi Andrey, >>> >>> Thank you very much for your reply. >>> Now, I better understand. >>> >>> You are all right. I do not have anything as high current as >>> MLB-201209-0120PU at a lower price. >>> >>> However, I have a 0603 600 ohm 1A bead, as MLB-160808-0600PL, at a much >>> lower price. >>> >>> http://ru.farnell.com/tdk/mpz1608s601a/ferrite-bead-0603-600-ohm/dp/1669747RL >>> What do you think about this component (TDK MPZ1608S601A)? >>> >>> Best regards. >>> >>> Jean-Samuel. >>> :-) >>> >>> >>> >>> On Wed, Jul 4, 2012 at 3:22 PM, Andrey Sviyazov wrote: >>> >>>> Hi Jean-Samuel. >>>> >>>> If Farnell better for you, then please order exactly MLB-201209-0120PU >>>> and MLB-160808-0600PL >>>> . >>>> They are HI_CURRENT beads and it is really required. >>>> >>>> Please find attached here new SCH and BOM files with new part numbers >>>> and links. >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> >>>> >>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>>> >>>>> Hi Andrey, >>>>> >>>>> Thank you very much for your reply. >>>>> >>>>> Could you please confirm the components bellow are fine ? >>>>> http://fr.farnell.com/murata/blm18tg601tn1d/ferrite-600ohm/dp/1115050RL >>>>> >>>>> http://fr.farnell.com/tdk/mmz2012121b/perle-de-ferrite-0805-120-ohm/dp/1669728RL >>>>> >>>>> Please let me know if this is fine. >>>>> If not, which would you suggest ? >>>>> http://ru.farnell.com/ferrite-beads >>>>> >>>>> >>>>> Thanks a lot for your help. >>>>> >>>>> Best regards. >>>>> >>>>> Jean-Samuel. >>>>> :-) >>>>> >>>>> >>>>> On Wed, Jul 4, 2012 at 2:02 PM, Andrey Sviyazov < >>>>> andreysviyaz at gmail.com> wrote: >>>>> >>>>>> Hi Jean-Samuel. >>>>>> >>>>>> For the TI160808U601 and TI201209U121 you can use any high current >>>>>> ferrite chip bead with 600 Ohm and 120 Ohm impedance respectively. >>>>>> For example you could order similar partnumbers from the ELFAcatalogue in the >>>>>> 0603and >>>>>> 0805 SMD >>>>>> cases respectively, datasheet here pdf >>>>>> . >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> >>>>>> >>>>>> >>>>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL < >>>>>> jsn at bjtpartners.com> >>>>>> >>>>>>> Hi Andrey, >>>>>>> >>>>>>> Thank you very much for your reply. >>>>>>> >>>>>>> I try to find where to buy the TI160808U601 and TI201209-121 chokes. >>>>>>> I do not know where I should find these. Would you know where I should >>>>>>> order these components ? >>>>>>> >>>>>>> By the way, do you confirm the ISSI SRAM is pin compatible with the >>>>>>> Cypress chip ? >>>>>>> >>>>>>> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >>>>>>> >>>>>>> Is this ISSI chip fine for our application ? Is 18 MBit enough ? >>>>>>> Do you confirm this ISSI chip is the best value for what we need ? >>>>>>> Are you sure we cannot find a lower cost chip with similar performances >>>>>>> and/or a better performances chip with similar cost ? >>>>>>> Are you sure we will not need to reroute the PCB ? >>>>>>> >>>>>>> We really need to be sure before starting the PCB production. If >>>>>>> both you and Alexander confirm everything is fine, I will ask the fab to >>>>>>> start the PCB. >>>>>>> >>>>>>> Please let me know. >>>>>>> >>>>>>> Again, thanks a lot for your help. >>>>>>> >>>>>>> Best regards. >>>>>>> >>>>>>> Jean-Samuel. >>>>>>> :-) >>>>>>> >>>>>>> >>>>>>> >>>>>>> On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov < >>>>>>> andreysviyaz at gmail.com> wrote: >>>>>>> >>>>>>>> Jean-Samuel. >>>>>>>> >>>>>>>> Please inform me what actually rf chockes partnumbers are problem >>>>>>>> to order. >>>>>>>> Unfortunately MuRata produce few billion pcs and then stopped for a >>>>>>>> few years. >>>>>>>> So, possible we have to find some Chinese fab partnumbers to order. >>>>>>>> >>>>>>>> Best regards, >>>>>>>> Andrey Sviyazov. >>>>>>>> (Sent from my mobile client) >>>>>>>> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" < >>>>>>>> andreysviyaz at gmail.com> ???????: >>>>>>>> >>>>>>>> Hi Jean-Samuel. >>>>>>>>> Unfortunately I have no internet connection now. >>>>>>>>> Tomorrow I'll check flash and others. >>>>>>>>> >>>>>>>>> Best regards, >>>>>>>>> Andrey Sviyazov. >>>>>>>>> (Sent from my mobile client) >>>>>>>>> >>>>>>>>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" < >>>>>>>>> alexander.chemeris at gmail.com> ???????: >>>>>>>>> > >>>>>>>>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT >>>>>>>>> PARTNERS >>>>>>>>> > SARL wrote: >>>>>>>>> > > 1/ Would you know a distributor for the Murata chokes ? The >>>>>>>>> fab them to have >>>>>>>>> > > some issue to source these. >>>>>>>>> > >>>>>>>>> > Andrey is looking into this. >>>>>>>>> > >>>>>>>>> > > 2/ Would you suggest a distributor for the GPS chip ? >>>>>>>>> > >>>>>>>>> > Try contacting manufacturer directly: >>>>>>>>> > >>>>>>>>> http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >>>>>>>>> > >>>>>>>>> > They have a distributor in UK, but I think it might be easier to >>>>>>>>> buy >>>>>>>>> > from the manufacturer directly: >>>>>>>>> > http://www.castlemicrowave.com/castle-contact.asp >>>>>>>>> > >>>>>>>>> > This chip is popular in Russia, so it is easy to source them >>>>>>>>> here, >>>>>>>>> > shipping them to EU might be a pain in big batches, but I think >>>>>>>>> we >>>>>>>>> > could send few chips for this prototyping batch if >>>>>>>>> manufacturer's lead >>>>>>>>> > time is too long. Here it costs $14.50/chip for more then 16 >>>>>>>>> chips: >>>>>>>>> > http://www.compel.ru/infosheet/TSI/EB-570/ >>>>>>>>> > >>>>>>>>> > -- >>>>>>>>> > Regards, >>>>>>>>> > Alexander Chemeris. >>>>>>>>> > CEO, Fairwaves LLC / ??? ??????? >>>>>>>>> > http://fairwaves.ru >>>>>>>>> >>>>>>>> >>>>>>> >>>>>> >>>>> >>>> >>> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: From jsn at bjtpartners.com Tue Jul 24 12:13:14 2012 From: jsn at bjtpartners.com (Jean-Samuel Najnudel - BJT PARTNERS SARL) Date: Tue, 24 Jul 2012 14:13:14 +0200 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Andrey, PCB copper is ready yet. We will lose 560 Euros and 3 weeks delay if we change the copper. It is not impossible, we can decide to do that but I would suggest we change the PCB for the next batch. After testing the v2 board, you may found more changes we need on the copper. The board itself is not ready. We can change some passives. This will not cost anything (or almost) and extra delay will be just one or two days at most. Please let me know what you want to do about the PCB. Please let me know the exact passives modifications. I will purchase the components asap and send the modifications list to the fab. Best regards. Jean-Samuel. :-) Le 23 juil. 2012 22:47, "Andrey Sviyazov" a ?crit : > Hi Jean-Samuel. > > Please let me know fabrication progress, a specially PCB. > I ask you because of few changes required to improve LMS phase noises. > BOM required changes in passive components only. > If PCB doesn't yet ordered, then possible I'll make changes too. > > Best regards, > Andrey Sviyazov. > (Sent from my mobile client) > 04.07.2012 20:01 ???????????? "Jean-Samuel Najnudel - BJT PARTNERS SARL" < > jsn at bjtpartners.com> ???????: > >> Hi Andrey, >> >> Thank you very much for your help. >> >> I will forward this to the fab. >> Yes, you are all right, the FBMH2012HM121-T price is much better than the >> MLB-201209-0120PU. However, availability on Farnell France is not as good >> as the MLB-201209-0120PU. Price difference is quite big but we only use 5 >> beads per boards. Difference makes only about 1 euro per board. I will let >> the fab decide between these 2 references. >> >> Best regards. >> >> Jean-Samuel. >> :-) >> >> >> On Wed, Jul 4, 2012 at 4:30 PM, Andrey Sviyazov wrote: >> >>> Hi Jean-Samuel. >>> >>> Yes, you are all right and you can order TDK - MPZ1608S601A instead of >>> MLB-160808-0600PL. >>> And also possible to use 3 times cheaper FBMH2012HM121-T, 0805, 2.5A instead >>> of MLB-201209-0120PU. >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>> >>>> Hi Andrey, >>>> >>>> Thank you very much for your reply. >>>> Now, I better understand. >>>> >>>> You are all right. I do not have anything as high current as >>>> MLB-201209-0120PU at a lower price. >>>> >>>> However, I have a 0603 600 ohm 1A bead, as MLB-160808-0600PL, at a much >>>> lower price. >>>> >>>> http://ru.farnell.com/tdk/mpz1608s601a/ferrite-bead-0603-600-ohm/dp/1669747RL >>>> What do you think about this component (TDK MPZ1608S601A)? >>>> >>>> Best regards. >>>> >>>> Jean-Samuel. >>>> :-) >>>> >>>> >>>> >>>> On Wed, Jul 4, 2012 at 3:22 PM, Andrey Sviyazov >>> > wrote: >>>> >>>>> Hi Jean-Samuel. >>>>> >>>>> If Farnell better for you, then please order exactly MLB-201209-0120PU >>>>> and MLB-160808-0600PL >>>>> . >>>>> They are HI_CURRENT beads and it is really required. >>>>> >>>>> Please find attached here new SCH and BOM files with new part numbers >>>>> and links. >>>>> >>>>> Best regards, >>>>> Andrey Sviyazov. >>>>> >>>>> >>>>> >>>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>>> > >>>>> >>>>>> Hi Andrey, >>>>>> >>>>>> Thank you very much for your reply. >>>>>> >>>>>> Could you please confirm the components bellow are fine ? >>>>>> >>>>>> http://fr.farnell.com/murata/blm18tg601tn1d/ferrite-600ohm/dp/1115050RL >>>>>> >>>>>> http://fr.farnell.com/tdk/mmz2012121b/perle-de-ferrite-0805-120-ohm/dp/1669728RL >>>>>> >>>>>> Please let me know if this is fine. >>>>>> If not, which would you suggest ? >>>>>> http://ru.farnell.com/ferrite-beads >>>>>> >>>>>> >>>>>> Thanks a lot for your help. >>>>>> >>>>>> Best regards. >>>>>> >>>>>> Jean-Samuel. >>>>>> :-) >>>>>> >>>>>> >>>>>> On Wed, Jul 4, 2012 at 2:02 PM, Andrey Sviyazov < >>>>>> andreysviyaz at gmail.com> wrote: >>>>>> >>>>>>> Hi Jean-Samuel. >>>>>>> >>>>>>> For the TI160808U601 and TI201209U121 you can use any high current >>>>>>> ferrite chip bead with 600 Ohm and 120 Ohm impedance respectively. >>>>>>> For example you could order similar partnumbers from the ELFAcatalogue in the >>>>>>> 0603and >>>>>>> 0805 SMD >>>>>>> cases respectively, datasheet here pdf >>>>>>> . >>>>>>> >>>>>>> Best regards, >>>>>>> Andrey Sviyazov. >>>>>>> >>>>>>> >>>>>>> >>>>>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL < >>>>>>> jsn at bjtpartners.com> >>>>>>> >>>>>>>> Hi Andrey, >>>>>>>> >>>>>>>> Thank you very much for your reply. >>>>>>>> >>>>>>>> I try to find where to buy the TI160808U601 and TI201209-121 >>>>>>>> chokes. I do not know where I should find these. Would you know where I >>>>>>>> should order these components ? >>>>>>>> >>>>>>>> By the way, do you confirm the ISSI SRAM is pin compatible with the >>>>>>>> Cypress chip ? >>>>>>>> >>>>>>>> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >>>>>>>> >>>>>>>> Is this ISSI chip fine for our application ? Is 18 MBit enough ? >>>>>>>> Do you confirm this ISSI chip is the best value for what we need ? >>>>>>>> Are you sure we cannot find a lower cost chip with similar performances >>>>>>>> and/or a better performances chip with similar cost ? >>>>>>>> Are you sure we will not need to reroute the PCB ? >>>>>>>> >>>>>>>> We really need to be sure before starting the PCB production. If >>>>>>>> both you and Alexander confirm everything is fine, I will ask the fab to >>>>>>>> start the PCB. >>>>>>>> >>>>>>>> Please let me know. >>>>>>>> >>>>>>>> Again, thanks a lot for your help. >>>>>>>> >>>>>>>> Best regards. >>>>>>>> >>>>>>>> Jean-Samuel. >>>>>>>> :-) >>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>> On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov < >>>>>>>> andreysviyaz at gmail.com> wrote: >>>>>>>> >>>>>>>>> Jean-Samuel. >>>>>>>>> >>>>>>>>> Please inform me what actually rf chockes partnumbers are problem >>>>>>>>> to order. >>>>>>>>> Unfortunately MuRata produce few billion pcs and then stopped for >>>>>>>>> a few years. >>>>>>>>> So, possible we have to find some Chinese fab partnumbers to order. >>>>>>>>> >>>>>>>>> Best regards, >>>>>>>>> Andrey Sviyazov. >>>>>>>>> (Sent from my mobile client) >>>>>>>>> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" < >>>>>>>>> andreysviyaz at gmail.com> ???????: >>>>>>>>> >>>>>>>>> Hi Jean-Samuel. >>>>>>>>>> Unfortunately I have no internet connection now. >>>>>>>>>> Tomorrow I'll check flash and others. >>>>>>>>>> >>>>>>>>>> Best regards, >>>>>>>>>> Andrey Sviyazov. >>>>>>>>>> (Sent from my mobile client) >>>>>>>>>> >>>>>>>>>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" < >>>>>>>>>> alexander.chemeris at gmail.com> ???????: >>>>>>>>>> > >>>>>>>>>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT >>>>>>>>>> PARTNERS >>>>>>>>>> > SARL wrote: >>>>>>>>>> > > 1/ Would you know a distributor for the Murata chokes ? The >>>>>>>>>> fab them to have >>>>>>>>>> > > some issue to source these. >>>>>>>>>> > >>>>>>>>>> > Andrey is looking into this. >>>>>>>>>> > >>>>>>>>>> > > 2/ Would you suggest a distributor for the GPS chip ? >>>>>>>>>> > >>>>>>>>>> > Try contacting manufacturer directly: >>>>>>>>>> > >>>>>>>>>> http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >>>>>>>>>> > >>>>>>>>>> > They have a distributor in UK, but I think it might be easier >>>>>>>>>> to buy >>>>>>>>>> > from the manufacturer directly: >>>>>>>>>> > http://www.castlemicrowave.com/castle-contact.asp >>>>>>>>>> > >>>>>>>>>> > This chip is popular in Russia, so it is easy to source them >>>>>>>>>> here, >>>>>>>>>> > shipping them to EU might be a pain in big batches, but I think >>>>>>>>>> we >>>>>>>>>> > could send few chips for this prototyping batch if >>>>>>>>>> manufacturer's lead >>>>>>>>>> > time is too long. Here it costs $14.50/chip for more then 16 >>>>>>>>>> chips: >>>>>>>>>> > http://www.compel.ru/infosheet/TSI/EB-570/ >>>>>>>>>> > >>>>>>>>>> > -- >>>>>>>>>> > Regards, >>>>>>>>>> > Alexander Chemeris. >>>>>>>>>> > CEO, Fairwaves LLC / ??? ??????? >>>>>>>>>> > http://fairwaves.ru >>>>>>>>>> >>>>>>>>> >>>>>>>> >>>>>>> >>>>>> >>>>> >>>> >>> >> -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Tue Jul 24 12:48:13 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Tue, 24 Jul 2012 14:48:13 +0200 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Jean-Samuel, We're sitting together with Andrey Sviyazov now and he says that it's fine to continue with this PCB. You will need 40pcs of this 0 Ohm jumpers (2pcs per board): http://fr.farnell.com/bourns/cr0603-j-000elf/resistor-0603-0r-5-0-1w/dp/2008343 Andrey will update the schematics and BoM later today. On Tue, Jul 24, 2012 at 2:13 PM, Jean-Samuel Najnudel - BJT PARTNERS SARL wrote: > Hi Andrey, > > PCB copper is ready yet. We will lose 560 Euros and 3 weeks delay if we > change the copper. It is not impossible, we can decide to do that but I > would suggest we change the PCB for the next batch. After testing the v2 > board, you may found more changes we need on the copper. > > The board itself is not ready. We can change some passives. This will not > cost anything (or almost) and extra delay will be just one or two days at > most. > > Please let me know what you want to do about the PCB. > > Please let me know the exact passives modifications. I will purchase the > components asap and send the modifications list to the fab. > > Best regards. > > Jean-Samuel. > :-) > > Le 23 juil. 2012 22:47, "Andrey Sviyazov" a ?crit : > >> Hi Jean-Samuel. >> >> Please let me know fabrication progress, a specially PCB. >> I ask you because of few changes required to improve LMS phase noises. >> BOM required changes in passive components only. >> If PCB doesn't yet ordered, then possible I'll make changes too. >> >> Best regards, >> Andrey Sviyazov. >> (Sent from my mobile client) >> >> 04.07.2012 20:01 ???????????? "Jean-Samuel Najnudel - BJT PARTNERS SARL" >> ???????: >>> >>> Hi Andrey, >>> >>> Thank you very much for your help. >>> >>> I will forward this to the fab. >>> Yes, you are all right, the FBMH2012HM121-T price is much better than the >>> MLB-201209-0120PU. However, availability on Farnell France is not as good as >>> the MLB-201209-0120PU. Price difference is quite big but we only use 5 beads >>> per boards. Difference makes only about 1 euro per board. I will let the fab >>> decide between these 2 references. >>> >>> Best regards. >>> >>> Jean-Samuel. >>> :-) >>> >>> >>> On Wed, Jul 4, 2012 at 4:30 PM, Andrey Sviyazov >>> wrote: >>>> >>>> Hi Jean-Samuel. >>>> >>>> Yes, you are all right and you can order TDK - MPZ1608S601A instead of >>>> MLB-160808-0600PL. >>>> And also possible to use 3 times cheaper FBMH2012HM121-T, 0805, 2.5A >>>> instead of MLB-201209-0120PU. >>>> >>>> Best regards, >>>> Andrey Sviyazov. >>>> >>>> >>>> >>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>>>> >>>>> Hi Andrey, >>>>> >>>>> Thank you very much for your reply. >>>>> Now, I better understand. >>>>> >>>>> You are all right. I do not have anything as high current as >>>>> MLB-201209-0120PU at a lower price. >>>>> >>>>> However, I have a 0603 600 ohm 1A bead, as MLB-160808-0600PL, at a much >>>>> lower price. >>>>> >>>>> http://ru.farnell.com/tdk/mpz1608s601a/ferrite-bead-0603-600-ohm/dp/1669747RL >>>>> What do you think about this component (TDK MPZ1608S601A)? >>>>> >>>>> Best regards. >>>>> >>>>> Jean-Samuel. >>>>> :-) >>>>> >>>>> >>>>> >>>>> On Wed, Jul 4, 2012 at 3:22 PM, Andrey Sviyazov >>>>> wrote: >>>>>> >>>>>> Hi Jean-Samuel. >>>>>> >>>>>> If Farnell better for you, then please order exactly MLB-201209-0120PU >>>>>> and MLB-160808-0600PL. >>>>>> They are HI_CURRENT beads and it is really required. >>>>>> >>>>>> Please find attached here new SCH and BOM files with new part numbers >>>>>> and links. >>>>>> >>>>>> Best regards, >>>>>> Andrey Sviyazov. >>>>>> >>>>>> >>>>>> >>>>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>>>>> >>>>>>> >>>>>>> Hi Andrey, >>>>>>> >>>>>>> Thank you very much for your reply. >>>>>>> >>>>>>> Could you please confirm the components bellow are fine ? >>>>>>> >>>>>>> http://fr.farnell.com/murata/blm18tg601tn1d/ferrite-600ohm/dp/1115050RL >>>>>>> >>>>>>> http://fr.farnell.com/tdk/mmz2012121b/perle-de-ferrite-0805-120-ohm/dp/1669728RL >>>>>>> >>>>>>> Please let me know if this is fine. >>>>>>> If not, which would you suggest ? >>>>>>> http://ru.farnell.com/ferrite-beads >>>>>>> >>>>>>> >>>>>>> Thanks a lot for your help. >>>>>>> >>>>>>> Best regards. >>>>>>> >>>>>>> Jean-Samuel. >>>>>>> :-) >>>>>>> >>>>>>> >>>>>>> On Wed, Jul 4, 2012 at 2:02 PM, Andrey Sviyazov >>>>>>> wrote: >>>>>>>> >>>>>>>> Hi Jean-Samuel. >>>>>>>> >>>>>>>> For the TI160808U601 and TI201209U121 you can use any high current >>>>>>>> ferrite chip bead with 600 Ohm and 120 Ohm impedance respectively. >>>>>>>> For example you could order similar partnumbers from the ELFA >>>>>>>> catalogue in the 0603 and 0805 SMD cases respectively, datasheet here pdf. >>>>>>>> >>>>>>>> Best regards, >>>>>>>> Andrey Sviyazov. >>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>>>>>>> >>>>>>>>> >>>>>>>>> Hi Andrey, >>>>>>>>> >>>>>>>>> Thank you very much for your reply. >>>>>>>>> >>>>>>>>> I try to find where to buy the TI160808U601 and TI201209-121 >>>>>>>>> chokes. I do not know where I should find these. Would you know where I >>>>>>>>> should order these components ? >>>>>>>>> >>>>>>>>> By the way, do you confirm the ISSI SRAM is pin compatible with the >>>>>>>>> Cypress chip ? >>>>>>>>> >>>>>>>>> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >>>>>>>>> >>>>>>>>> Is this ISSI chip fine for our application ? Is 18 MBit enough ? >>>>>>>>> Do you confirm this ISSI chip is the best value for what we need ? >>>>>>>>> Are you sure we cannot find a lower cost chip with similar performances >>>>>>>>> and/or a better performances chip with similar cost ? >>>>>>>>> Are you sure we will not need to reroute the PCB ? >>>>>>>>> >>>>>>>>> We really need to be sure before starting the PCB production. If >>>>>>>>> both you and Alexander confirm everything is fine, I will ask the fab to >>>>>>>>> start the PCB. >>>>>>>>> >>>>>>>>> Please let me know. >>>>>>>>> >>>>>>>>> Again, thanks a lot for your help. >>>>>>>>> >>>>>>>>> Best regards. >>>>>>>>> >>>>>>>>> Jean-Samuel. >>>>>>>>> :-) >>>>>>>>> >>>>>>>>> >>>>>>>>> >>>>>>>>> On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov >>>>>>>>> wrote: >>>>>>>>>> >>>>>>>>>> Jean-Samuel. >>>>>>>>>> >>>>>>>>>> Please inform me what actually rf chockes partnumbers are problem >>>>>>>>>> to order. >>>>>>>>>> Unfortunately MuRata produce few billion pcs and then stopped for >>>>>>>>>> a few years. >>>>>>>>>> So, possible we have to find some Chinese fab partnumbers to >>>>>>>>>> order. >>>>>>>>>> >>>>>>>>>> Best regards, >>>>>>>>>> Andrey Sviyazov. >>>>>>>>>> (Sent from my mobile client) >>>>>>>>>> >>>>>>>>>> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" >>>>>>>>>> ???????: >>>>>>>>>> >>>>>>>>>>> Hi Jean-Samuel. >>>>>>>>>>> Unfortunately I have no internet connection now. >>>>>>>>>>> Tomorrow I'll check flash and others. >>>>>>>>>>> >>>>>>>>>>> Best regards, >>>>>>>>>>> Andrey Sviyazov. >>>>>>>>>>> (Sent from my mobile client) >>>>>>>>>>> >>>>>>>>>>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" >>>>>>>>>>> ???????: >>>>>>>>>>> > >>>>>>>>>>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT >>>>>>>>>>> > PARTNERS >>>>>>>>>>> > SARL wrote: >>>>>>>>>>> > > 1/ Would you know a distributor for the Murata chokes ? The >>>>>>>>>>> > > fab them to have >>>>>>>>>>> > > some issue to source these. >>>>>>>>>>> > >>>>>>>>>>> > Andrey is looking into this. >>>>>>>>>>> > >>>>>>>>>>> > > 2/ Would you suggest a distributor for the GPS chip ? >>>>>>>>>>> > >>>>>>>>>>> > Try contacting manufacturer directly: >>>>>>>>>>> > >>>>>>>>>>> > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >>>>>>>>>>> > >>>>>>>>>>> > They have a distributor in UK, but I think it might be easier >>>>>>>>>>> > to buy >>>>>>>>>>> > from the manufacturer directly: >>>>>>>>>>> > http://www.castlemicrowave.com/castle-contact.asp >>>>>>>>>>> > >>>>>>>>>>> > This chip is popular in Russia, so it is easy to source them >>>>>>>>>>> > here, >>>>>>>>>>> > shipping them to EU might be a pain in big batches, but I think >>>>>>>>>>> > we >>>>>>>>>>> > could send few chips for this prototyping batch if >>>>>>>>>>> > manufacturer's lead >>>>>>>>>>> > time is too long. Here it costs $14.50/chip for more then 16 >>>>>>>>>>> > chips: >>>>>>>>>>> > http://www.compel.ru/infosheet/TSI/EB-570/ >>>>>>>>>>> > >>>>>>>>>>> > -- >>>>>>>>>>> > Regards, >>>>>>>>>>> > Alexander Chemeris. >>>>>>>>>>> > CEO, Fairwaves LLC / ??? ??????? >>>>>>>>>>> > http://fairwaves.ru >>>>>>>>> >>>>>>>>> >>>>>>>> >>>>>>> >>>>>> >>>>> >>>> >>> > -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From andreysviyaz at gmail.com Tue Jul 24 21:11:04 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Wed, 25 Jul 2012 01:11:04 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Jean-Samuel. First of all you're right, we can't delay production. So, I am sure it is better if PCB production will continue as you suggest. There are only three hardware issues which have to be solved before assembling: 1) Improving LMS phase noise. It is almost done and Alexander wrote you which component need to order. 2) Digital noise which born in GPS module 230. In ver.2 we will use GPS module 570, but I am afraid that we can get the same problems. So, I need 1-2 days to workaround this issue. And also we have to understand either it important or it doesn't because this noises hided under modulation. 3) LMS engineers suggested us to use PLL loop filter 100kHz instead 50kHz. In case of 100kHz we have to decrease charge-pump current from 1.2-1.9mA down to 0.4mA, but I am afraid about integral phase noise of LO because (possible) it can affect modulation phase error (in degrees). I think, required 1-2 days (the same days) to understand this also. So, at Thirsday I will send you final BOM and assembly files. Hope it doesn't delay production, otherwise tell me and we'll hurry up. Best regards, Andrey Sviyazov. 2012/7/24 Alexander Chemeris > Hi Jean-Samuel, > > We're sitting together with Andrey Sviyazov now and he says that it's > fine to continue with this PCB. > > You will need 40pcs of this 0 Ohm jumpers (2pcs per board): > > http://fr.farnell.com/bourns/cr0603-j-000elf/resistor-0603-0r-5-0-1w/dp/2008343 > > Andrey will update the schematics and BoM later today. > > On Tue, Jul 24, 2012 at 2:13 PM, Jean-Samuel Najnudel - BJT PARTNERS > SARL wrote: > > Hi Andrey, > > > > PCB copper is ready yet. We will lose 560 Euros and 3 weeks delay if we > > change the copper. It is not impossible, we can decide to do that but I > > would suggest we change the PCB for the next batch. After testing the v2 > > board, you may found more changes we need on the copper. > > > > The board itself is not ready. We can change some passives. This will not > > cost anything (or almost) and extra delay will be just one or two days at > > most. > > > > Please let me know what you want to do about the PCB. > > > > Please let me know the exact passives modifications. I will purchase the > > components asap and send the modifications list to the fab. > > > > Best regards. > > > > Jean-Samuel. > > :-) > > > > Le 23 juil. 2012 22:47, "Andrey Sviyazov" a > ?crit : > > > >> Hi Jean-Samuel. > >> > >> Please let me know fabrication progress, a specially PCB. > >> I ask you because of few changes required to improve LMS phase noises. > >> BOM required changes in passive components only. > >> If PCB doesn't yet ordered, then possible I'll make changes too. > >> > >> Best regards, > >> Andrey Sviyazov. > >> (Sent from my mobile client) > >> > >> 04.07.2012 20:01 ???????????? "Jean-Samuel Najnudel - BJT PARTNERS SARL" > >> ???????: > >>> > >>> Hi Andrey, > >>> > >>> Thank you very much for your help. > >>> > >>> I will forward this to the fab. > >>> Yes, you are all right, the FBMH2012HM121-T price is much better than > the > >>> MLB-201209-0120PU. However, availability on Farnell France is not as > good as > >>> the MLB-201209-0120PU. Price difference is quite big but we only use 5 > beads > >>> per boards. Difference makes only about 1 euro per board. I will let > the fab > >>> decide between these 2 references. > >>> > >>> Best regards. > >>> > >>> Jean-Samuel. > >>> :-) > >>> > >>> > >>> On Wed, Jul 4, 2012 at 4:30 PM, Andrey Sviyazov < > andreysviyaz at gmail.com> > >>> wrote: > >>>> > >>>> Hi Jean-Samuel. > >>>> > >>>> Yes, you are all right and you can order TDK - MPZ1608S601A instead of > >>>> MLB-160808-0600PL. > >>>> And also possible to use 3 times cheaper FBMH2012HM121-T, 0805, 2.5A > >>>> instead of MLB-201209-0120PU. > >>>> > >>>> Best regards, > >>>> Andrey Sviyazov. > >>>> > >>>> > >>>> > >>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL < > jsn at bjtpartners.com> > >>>>> > >>>>> Hi Andrey, > >>>>> > >>>>> Thank you very much for your reply. > >>>>> Now, I better understand. > >>>>> > >>>>> You are all right. I do not have anything as high current as > >>>>> MLB-201209-0120PU at a lower price. > >>>>> > >>>>> However, I have a 0603 600 ohm 1A bead, as MLB-160808-0600PL, at a > much > >>>>> lower price. > >>>>> > >>>>> > http://ru.farnell.com/tdk/mpz1608s601a/ferrite-bead-0603-600-ohm/dp/1669747RL > >>>>> What do you think about this component (TDK MPZ1608S601A)? > >>>>> > >>>>> Best regards. > >>>>> > >>>>> Jean-Samuel. > >>>>> :-) > >>>>> > >>>>> > >>>>> > >>>>> On Wed, Jul 4, 2012 at 3:22 PM, Andrey Sviyazov > >>>>> wrote: > >>>>>> > >>>>>> Hi Jean-Samuel. > >>>>>> > >>>>>> If Farnell better for you, then please order exactly > MLB-201209-0120PU > >>>>>> and MLB-160808-0600PL. > >>>>>> They are HI_CURRENT beads and it is really required. > >>>>>> > >>>>>> Please find attached here new SCH and BOM files with new part > numbers > >>>>>> and links. > >>>>>> > >>>>>> Best regards, > >>>>>> Andrey Sviyazov. > >>>>>> > >>>>>> > >>>>>> > >>>>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL > >>>>>> > >>>>>>> > >>>>>>> Hi Andrey, > >>>>>>> > >>>>>>> Thank you very much for your reply. > >>>>>>> > >>>>>>> Could you please confirm the components bellow are fine ? > >>>>>>> > >>>>>>> > http://fr.farnell.com/murata/blm18tg601tn1d/ferrite-600ohm/dp/1115050RL > >>>>>>> > >>>>>>> > http://fr.farnell.com/tdk/mmz2012121b/perle-de-ferrite-0805-120-ohm/dp/1669728RL > >>>>>>> > >>>>>>> Please let me know if this is fine. > >>>>>>> If not, which would you suggest ? > >>>>>>> http://ru.farnell.com/ferrite-beads > >>>>>>> > >>>>>>> > >>>>>>> Thanks a lot for your help. > >>>>>>> > >>>>>>> Best regards. > >>>>>>> > >>>>>>> Jean-Samuel. > >>>>>>> :-) > >>>>>>> > >>>>>>> > >>>>>>> On Wed, Jul 4, 2012 at 2:02 PM, Andrey Sviyazov > >>>>>>> wrote: > >>>>>>>> > >>>>>>>> Hi Jean-Samuel. > >>>>>>>> > >>>>>>>> For the TI160808U601 and TI201209U121 you can use any high current > >>>>>>>> ferrite chip bead with 600 Ohm and 120 Ohm impedance respectively. > >>>>>>>> For example you could order similar partnumbers from the ELFA > >>>>>>>> catalogue in the 0603 and 0805 SMD cases respectively, datasheet > here pdf. > >>>>>>>> > >>>>>>>> Best regards, > >>>>>>>> Andrey Sviyazov. > >>>>>>>> > >>>>>>>> > >>>>>>>> > >>>>>>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL > >>>>>>>> > >>>>>>>>> > >>>>>>>>> Hi Andrey, > >>>>>>>>> > >>>>>>>>> Thank you very much for your reply. > >>>>>>>>> > >>>>>>>>> I try to find where to buy the TI160808U601 and TI201209-121 > >>>>>>>>> chokes. I do not know where I should find these. Would you know > where I > >>>>>>>>> should order these components ? > >>>>>>>>> > >>>>>>>>> By the way, do you confirm the ISSI SRAM is pin compatible with > the > >>>>>>>>> Cypress chip ? > >>>>>>>>> > >>>>>>>>> > http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 > >>>>>>>>> > >>>>>>>>> Is this ISSI chip fine for our application ? Is 18 MBit enough ? > >>>>>>>>> Do you confirm this ISSI chip is the best value for what we need > ? > >>>>>>>>> Are you sure we cannot find a lower cost chip with similar > performances > >>>>>>>>> and/or a better performances chip with similar cost ? > >>>>>>>>> Are you sure we will not need to reroute the PCB ? > >>>>>>>>> > >>>>>>>>> We really need to be sure before starting the PCB production. If > >>>>>>>>> both you and Alexander confirm everything is fine, I will ask > the fab to > >>>>>>>>> start the PCB. > >>>>>>>>> > >>>>>>>>> Please let me know. > >>>>>>>>> > >>>>>>>>> Again, thanks a lot for your help. > >>>>>>>>> > >>>>>>>>> Best regards. > >>>>>>>>> > >>>>>>>>> Jean-Samuel. > >>>>>>>>> :-) > >>>>>>>>> > >>>>>>>>> > >>>>>>>>> > >>>>>>>>> On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov > >>>>>>>>> wrote: > >>>>>>>>>> > >>>>>>>>>> Jean-Samuel. > >>>>>>>>>> > >>>>>>>>>> Please inform me what actually rf chockes partnumbers are > problem > >>>>>>>>>> to order. > >>>>>>>>>> Unfortunately MuRata produce few billion pcs and then stopped > for > >>>>>>>>>> a few years. > >>>>>>>>>> So, possible we have to find some Chinese fab partnumbers to > >>>>>>>>>> order. > >>>>>>>>>> > >>>>>>>>>> Best regards, > >>>>>>>>>> Andrey Sviyazov. > >>>>>>>>>> (Sent from my mobile client) > >>>>>>>>>> > >>>>>>>>>> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" > >>>>>>>>>> ???????: > >>>>>>>>>> > >>>>>>>>>>> Hi Jean-Samuel. > >>>>>>>>>>> Unfortunately I have no internet connection now. > >>>>>>>>>>> Tomorrow I'll check flash and others. > >>>>>>>>>>> > >>>>>>>>>>> Best regards, > >>>>>>>>>>> Andrey Sviyazov. > >>>>>>>>>>> (Sent from my mobile client) > >>>>>>>>>>> > >>>>>>>>>>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" > >>>>>>>>>>> ???????: > >>>>>>>>>>> > > >>>>>>>>>>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT > >>>>>>>>>>> > PARTNERS > >>>>>>>>>>> > SARL wrote: > >>>>>>>>>>> > > 1/ Would you know a distributor for the Murata chokes ? The > >>>>>>>>>>> > > fab them to have > >>>>>>>>>>> > > some issue to source these. > >>>>>>>>>>> > > >>>>>>>>>>> > Andrey is looking into this. > >>>>>>>>>>> > > >>>>>>>>>>> > > 2/ Would you suggest a distributor for the GPS chip ? > >>>>>>>>>>> > > >>>>>>>>>>> > Try contacting manufacturer directly: > >>>>>>>>>>> > > >>>>>>>>>>> > > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 > >>>>>>>>>>> > > >>>>>>>>>>> > They have a distributor in UK, but I think it might be easier > >>>>>>>>>>> > to buy > >>>>>>>>>>> > from the manufacturer directly: > >>>>>>>>>>> > http://www.castlemicrowave.com/castle-contact.asp > >>>>>>>>>>> > > >>>>>>>>>>> > This chip is popular in Russia, so it is easy to source them > >>>>>>>>>>> > here, > >>>>>>>>>>> > shipping them to EU might be a pain in big batches, but I > think > >>>>>>>>>>> > we > >>>>>>>>>>> > could send few chips for this prototyping batch if > >>>>>>>>>>> > manufacturer's lead > >>>>>>>>>>> > time is too long. Here it costs $14.50/chip for more then 16 > >>>>>>>>>>> > chips: > >>>>>>>>>>> > http://www.compel.ru/infosheet/TSI/EB-570/ > >>>>>>>>>>> > > >>>>>>>>>>> > -- > >>>>>>>>>>> > Regards, > >>>>>>>>>>> > Alexander Chemeris. > >>>>>>>>>>> > CEO, Fairwaves LLC / ??? ??????? > >>>>>>>>>>> > http://fairwaves.ru > >>>>>>>>> > >>>>>>>>> > >>>>>>>> > >>>>>>> > >>>>>> > >>>>> > >>>> > >>> > > > > > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andrey.sviyazov at fairwaves.ru Tue Jul 24 21:56:31 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Wed, 25 Jul 2012 01:56:31 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Thomas. Could you please make test again for LO integral phase noise and modulation accuracy with PLL loop filter 100kHz and ICP=0.4mA (or above), as Srdjan suggested us. I've assembled 100kHz loop filter with the next components: C82 = 100pF, C83=1500pF, C84=33pF, R106=2.2k, R109=3.3k. To get good noises replace choke L6 by capacitor 10nF..22nF and remove C45. I ask you because I have to send final BOM as soon as possible to avoid delay of UmTRXv2 production due to changes for improvements. Best regards, Andrey Sviyazov. P.S. Pictures attached just to be sure. 2012/7/23 Andrey Sviyazov > > > > Perhaps this is a silly question, but how do I calibrate the clock? or > > > use an external reference signal? > > > > Andrey Sviyazov - does ClockIn works as external input in UmTRXv1? > > Yes, 5V cmos level required or smaller with DC offset to get 2.5V symmetry. > Turn switches to MHz and slave positions. > > Best regards, > Andrey Sviyazov. > (Sent from my mobile client) > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: Clock AC coupling and 100 kHz.png Type: image/png Size: 110842 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: PLL 100kHz BW_bottom side.png Type: image/png Size: 118649 bytes Desc: not available URL: From ttsou at vt.edu Wed Jul 25 00:47:16 2012 From: ttsou at vt.edu (Thomas Tsou) Date: Tue, 24 Jul 2012 20:47:16 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Andrey, I will need to order parts. Can you give me a list of digikey part numbers for the required components? Thomas On Tue, Jul 24, 2012 at 5:56 PM, Andrey Sviyazov wrote: > Hi Thomas. > > Could you please make test again for LO integral phase noise and modulation > accuracy with PLL loop filter 100kHz and ICP=0.4mA (or above), as Srdjan > suggested us. > I've assembled 100kHz loop filter with the next components: > C82 = 100pF, C83=1500pF, C84=33pF, R106=2.2k, R109=3.3k. > To get good noises replace choke L6 by capacitor 10nF..22nF and remove C45. > > I ask you because I have to send final BOM as soon as possible to avoid > delay of UmTRXv2 production due to changes for improvements. > > Best regards, > Andrey Sviyazov. > P.S. Pictures attached just to be sure. > > > 2012/7/23 Andrey Sviyazov >> >> >> > > Perhaps this is a silly question, but how do I calibrate the clock? or >> > > use an external reference signal? >> > >> > Andrey Sviyazov - does ClockIn works as external input in UmTRXv1? >> >> Yes, 5V cmos level required or smaller with DC offset to get 2.5V >> symmetry. >> Turn switches to MHz and slave positions. >> >> Best regards, >> Andrey Sviyazov. >> (Sent from my mobile client) > > From alexander.chemeris at gmail.com Wed Jul 25 04:46:49 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Wed, 25 Jul 2012 08:46:49 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Andrey, Could you also describe to Thomas and Sylvain what to do with C45 and L6? I guess that's a required step before they do any other measurements. And please, add this issue to the issue tracker. On Wed, Jul 25, 2012 at 1:56 AM, Andrey Sviyazov wrote: > Hi Thomas. > > Could you please make test again for LO integral phase noise and modulation > accuracy with PLL loop filter 100kHz and ICP=0.4mA (or above), as Srdjan > suggested us. > I've assembled 100kHz loop filter with the next components: > C82 = 100pF, C83=1500pF, C84=33pF, R106=2.2k, R109=3.3k. > To get good noises replace choke L6 by capacitor 10nF..22nF and remove C45. > > I ask you because I have to send final BOM as soon as possible to avoid > delay of UmTRXv2 production due to changes for improvements. > > Best regards, > Andrey Sviyazov. > P.S. Pictures attached just to be sure. > > > 2012/7/23 Andrey Sviyazov >> >> >> > > Perhaps this is a silly question, but how do I calibrate the clock? or >> > > use an external reference signal? >> > >> > Andrey Sviyazov - does ClockIn works as external input in UmTRXv1? >> >> Yes, 5V cmos level required or smaller with DC offset to get 2.5V >> symmetry. >> Turn switches to MHz and slave positions. >> >> Best regards, >> Andrey Sviyazov. >> (Sent from my mobile client) > > -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From andrey.sviyazov at fairwaves.ru Wed Jul 25 05:01:52 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Wed, 25 Jul 2012 09:01:52 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Alexander, I already explained it in preview mail. Best regards, Andrey Sviyazov. (Sent from my mobile client) 25.07.2012 8:47 ???????????? "Alexander Chemeris" < alexander.chemeris at gmail.com> ???????: > Hi Andrey, > > Could you also describe to Thomas and Sylvain what to do with C45 and > L6? I guess that's a required step before they do any other > measurements. > > And please, add this issue to the issue tracker. > > On Wed, Jul 25, 2012 at 1:56 AM, Andrey Sviyazov > wrote: > > Hi Thomas. > > > > Could you please make test again for LO integral phase noise and > modulation > > accuracy with PLL loop filter 100kHz and ICP=0.4mA (or above), as Srdjan > > suggested us. > > I've assembled 100kHz loop filter with the next components: > > C82 = 100pF, C83=1500pF, C84=33pF, R106=2.2k, R109=3.3k. > > To get good noises replace choke L6 by capacitor 10nF..22nF and remove > C45. > > > > I ask you because I have to send final BOM as soon as possible to avoid > > delay of UmTRXv2 production due to changes for improvements. > > > > Best regards, > > Andrey Sviyazov. > > P.S. Pictures attached just to be sure. > > > > > > 2012/7/23 Andrey Sviyazov > >> > >> > >> > > Perhaps this is a silly question, but how do I calibrate the clock? > or > >> > > use an external reference signal? > >> > > >> > Andrey Sviyazov - does ClockIn works as external input in UmTRXv1? > >> > >> Yes, 5V cmos level required or smaller with DC offset to get 2.5V > >> symmetry. > >> Turn switches to MHz and slave positions. > >> > >> Best regards, > >> Andrey Sviyazov. > >> (Sent from my mobile client) > > > > > > > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Wed Jul 25 05:12:26 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Wed, 25 Jul 2012 09:12:26 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Sorry, missed that! I was reading before I really wake up. Still we need to document this at the issue tracker. On Wed, Jul 25, 2012 at 9:01 AM, Andrey Sviyazov wrote: > Alexander, I already explained it in preview mail. > > Best regards, > Andrey Sviyazov. > (Sent from my mobile client) > > 25.07.2012 8:47 ???????????? "Alexander Chemeris" > ???????: > >> Hi Andrey, >> >> Could you also describe to Thomas and Sylvain what to do with C45 and >> L6? I guess that's a required step before they do any other >> measurements. >> >> And please, add this issue to the issue tracker. >> >> On Wed, Jul 25, 2012 at 1:56 AM, Andrey Sviyazov >> wrote: >> > Hi Thomas. >> > >> > Could you please make test again for LO integral phase noise and >> > modulation >> > accuracy with PLL loop filter 100kHz and ICP=0.4mA (or above), as Srdjan >> > suggested us. >> > I've assembled 100kHz loop filter with the next components: >> > C82 = 100pF, C83=1500pF, C84=33pF, R106=2.2k, R109=3.3k. >> > To get good noises replace choke L6 by capacitor 10nF..22nF and remove >> > C45. >> > >> > I ask you because I have to send final BOM as soon as possible to avoid >> > delay of UmTRXv2 production due to changes for improvements. >> > >> > Best regards, >> > Andrey Sviyazov. >> > P.S. Pictures attached just to be sure. >> > >> > >> > 2012/7/23 Andrey Sviyazov >> >> >> >> >> >> > > Perhaps this is a silly question, but how do I calibrate the clock? >> >> > > or >> >> > > use an external reference signal? >> >> > >> >> > Andrey Sviyazov - does ClockIn works as external input in UmTRXv1? >> >> >> >> Yes, 5V cmos level required or smaller with DC offset to get 2.5V >> >> symmetry. >> >> Turn switches to MHz and slave positions. >> >> >> >> Best regards, >> >> Andrey Sviyazov. >> >> (Sent from my mobile client) >> > >> > >> >> >> >> -- >> Regards, >> Alexander Chemeris. >> CEO, Fairwaves LLC / ??? ??????? >> http://fairwaves.ru -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From andrey.sviyazov at fairwaves.ru Wed Jul 25 17:41:58 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Wed, 25 Jul 2012 21:41:58 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Thomas. Digikey part numbers links: C82 = 100pF, C83=1500pF, C84=33pF, R106=2.2k, R109=3.3k, L6=0.022uF . But you'll remove 100pF capasitor from position C45, so you could use it for C82. BTW, how long time required to delivering from the DigiKey? Best regards, Andrey Sviyazov. 2012/7/25 Thomas Tsou > Hi Andrey, > > I will need to order parts. Can you give me a list of digikey part > numbers for the required components? > > Thomas > > On Tue, Jul 24, 2012 at 5:56 PM, Andrey Sviyazov > wrote: > > Hi Thomas. > > > > Could you please make test again for LO integral phase noise and > modulation > > accuracy with PLL loop filter 100kHz and ICP=0.4mA (or above), as Srdjan > > suggested us. > > I've assembled 100kHz loop filter with the next components: > > C82 = 100pF, C83=1500pF, C84=33pF, R106=2.2k, R109=3.3k. > > To get good noises replace choke L6 by capacitor 10nF..22nF and remove > C45. > > > > I ask you because I have to send final BOM as soon as possible to avoid > > delay of UmTRXv2 production due to changes for improvements. > > > > Best regards, > > Andrey Sviyazov. > > P.S. Pictures attached just to be sure. > > > > > > 2012/7/23 Andrey Sviyazov > >> > >> > >> > > Perhaps this is a silly question, but how do I calibrate the clock? > or > >> > > use an external reference signal? > >> > > >> > Andrey Sviyazov - does ClockIn works as external input in UmTRXv1? > >> > >> Yes, 5V cmos level required or smaller with DC offset to get 2.5V > >> symmetry. > >> Turn switches to MHz and slave positions. > >> > >> Best regards, > >> Andrey Sviyazov. > >> (Sent from my mobile client) > > > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From ttsou at vt.edu Thu Jul 26 01:52:32 2012 From: ttsou at vt.edu (Thomas Tsou) Date: Wed, 25 Jul 2012 21:52:32 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: On Wed, Jul 25, 2012 at 1:41 PM, Andrey Sviyazov wrote: > Hi Thomas. > > Digikey part numbers links: > C82 = 100pF, C83=1500pF, C84=33pF, R106=2.2k, R109=3.3k, L6=0.022uF. > > But you'll remove 100pF capasitor from position C45, so you could use it for > C82. > BTW, how long time required to delivering from the DigiKey? Thank you for the links. Parts are ordered. Digikey orders usually arrives in 2 days. Thomas From alexander.chemeris at gmail.com Thu Jul 26 05:03:36 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Thu, 26 Jul 2012 09:03:36 +0400 Subject: DC Offset vs temperature Message-ID: Hi all, Thomas has discovered that DC offset calibration for LMS is drifting a lot with temperature changes and this has detrimental effect on the modulation accuracy: http://code.google.com/p/umtrx/issues/detail?id=31 One solution proposed by Sylvain is to tune modulation a bit higher using digital modulation, which should be straightforward with UHD which has digital mixer in FPGA. But I wonder what is a recommended solution for this temperature compensation for LMS in general. Srdjan, could you comment on this? -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From s.milenkovic at limemicro.com Thu Jul 26 11:31:54 2012 From: s.milenkovic at limemicro.com (Srdjan Milenkovic) Date: Thu, 26 Jul 2012 12:31:54 +0100 Subject: DC Offset vs temperature In-Reply-To: References: Message-ID: <50112AAA.1040002@limemicro.com> Hi, We need a bit more info to see what we can do to avoid at least cooling fan as it is expensive. 1. Was that proper temperature chamber measurement or just Rx on/off? 2. I think we are talking about two issues called phase error here. 2.a IQ phase error caused by LMS Tx/Rx PLLs alone 2.b Modulation phase error Item 2.a should not be affected by temperature so much In 900/1800MHz frequency region. If we want to get it even better we can always make a look up table vs temperature to correct IQ phase error from FPGA. Item 2.b is affected by both 2.a and Tx DC cal. Tx DC cal has already been addressed by Thomas. Combining Thomas's idea of DC recalibration and, if necessary, making look up table for IQ phase error correction vs temperature should put us in good position to meet the specs. Dr Srdjan Milenkovic On 26/07/2012 06:03, Alexander Chemeris wrote: > Hi all, > > Thomas has discovered that DC offset calibration for LMS is drifting a > lot with temperature changes and this has detrimental effect on the > modulation accuracy: > http://code.google.com/p/umtrx/issues/detail?id=31 > > One solution proposed by Sylvain is to tune modulation a bit higher > using digital modulation, which should be straightforward with UHD > which has digital mixer in FPGA. > > But I wonder what is a recommended solution for this temperature > compensation for LMS in general. Srdjan, could you comment on this? > -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Thu Jul 26 12:37:14 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Thu, 26 Jul 2012 16:37:14 +0400 Subject: DC Offset vs temperature In-Reply-To: <50112AAA.1040002@limemicro.com> References: <50112AAA.1040002@limemicro.com> Message-ID: On Thu, Jul 26, 2012 at 3:31 PM, Srdjan Milenkovic wrote: > Combining Thomas's idea of DC recalibration and, if necessary, making look > up table for IQ phase error correction vs temperature should put us in good > position to meet the specs. Well, AFAIK, LMS6002D doesn't have a temperature sensor built in and this means we have to install an external one, which again increase BoM cost. Is that's how this issue is solved by your other customers? I wonder is there a way to solve this without introducing a temperature compensation loop. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Thu Jul 26 15:48:22 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Thu, 26 Jul 2012 19:48:22 +0400 Subject: DC Offset vs temperature In-Reply-To: References: <50112AAA.1040002@limemicro.com> Message-ID: On Thu, Jul 26, 2012 at 4:37 PM, Alexander Chemeris wrote: > > On Thu, Jul 26, 2012 at 3:31 PM, Srdjan Milenkovic > wrote: > > Combining Thomas's idea of DC recalibration and, if necessary, making > > look > > up table for IQ phase error correction vs temperature should put us in > > good > > position to meet the specs. > > Well, AFAIK, LMS6002D doesn't have a temperature sensor built in and > this means we have to install an external one, which again increase > BoM cost. Is that's how this issue is solved by your other customers? > I wonder is there a way to solve this without introducing a > temperature compensation loop. Let me clarify - DC offset re-calibration is (more or less) fine in lab setup, but it's expensive to manufacture if we have to add temperature sensors and put every unit into a temperature camera for calibration. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From coxe at close-haul.com Fri Jul 27 12:36:35 2012 From: coxe at close-haul.com (Robin Coxe) Date: Fri, 27 Jul 2012 08:36:35 -0400 Subject: Plan for 10/100 Ethernet support for umTRX Message-ID: The Ettus UHD framework adopted for the umTRX only supports GigE (simple_gemac). A reworked, Wishbone-compliant 10/100 Ethernet MAC is included in the OpenRISC SoC project on Opencores. It has been ported to the Digilent Atlys board, which has a Spartan-6 FPGA. http://www.chokladfabriken.org/projects/orpsoc-atlys I'll begin the port of this Ethernet MAC (a cleaned-up version of the 10/100 core on OpenCores) to the UmTRX and test it on Close-Haul's SP-605 Spartan-6 eval. board. I'm not quite sure how long this task will take, but this feature falls into the "nice-to-have-but-not-urgent" category. -Robin -- Robin Coxe | Close-Haul Communications, Inc. | Boston, MA +1-617-470-8825 From 246tnt at gmail.com Fri Jul 27 13:04:49 2012 From: 246tnt at gmail.com (Sylvain Munaut) Date: Fri, 27 Jul 2012 15:04:49 +0200 Subject: Plan for 10/100 Ethernet support for umTRX In-Reply-To: References: Message-ID: Hi, > The Ettus UHD framework adopted for the umTRX only supports GigE > (simple_gemac). A reworked, Wishbone-compliant 10/100 Ethernet MAC > is included in the OpenRISC SoC project on Opencores. It has been > ported to the Digilent Atlys board, which has a Spartan-6 FPGA. > > http://www.chokladfabriken.org/projects/orpsoc-atlys > > I'll begin the port of this Ethernet MAC (a cleaned-up version of the > 10/100 core on OpenCores) to the UmTRX and test it on Close-Haul's > SP-605 Spartan-6 eval. board. I'm not quite sure how long this task > will take, but this feature falls into the > "nice-to-have-but-not-urgent" category. But would it be 10/100/1000 ? or just 10/100 ? Also, doesn't UHD make use of the 'wait' feature of Gigabit (i.e. PAUSE frames / flow control ) to avoid loosing data ? This doesn't exist on 10/100 IIRC. Cheers, Sylvain From coxe at close-haul.com Fri Jul 27 14:27:02 2012 From: coxe at close-haul.com (Robin Coxe) Date: Fri, 27 Jul 2012 10:27:02 -0400 Subject: Plan for 10/100 Ethernet support for umTRX In-Reply-To: References: Message-ID: Hi Sylvain. On Fri, Jul 27, 2012 at 9:04 AM, Sylvain Munaut <246tnt at gmail.com> wrote: > Hi, > >> The Ettus UHD framework adopted for the umTRX only supports GigE >> (simple_gemac). A reworked, Wishbone-compliant 10/100 Ethernet MAC >> is included in the OpenRISC SoC project on Opencores. It has been >> ported to the Digilent Atlys board, which has a Spartan-6 FPGA. >> >> http://www.chokladfabriken.org/projects/orpsoc-atlys >> >> I'll begin the port of this Ethernet MAC (a cleaned-up version of the >> 10/100 core on OpenCores) to the UmTRX and test it on Close-Haul's >> SP-605 Spartan-6 eval. board. I'm not quite sure how long this task >> will take, but this feature falls into the >> "nice-to-have-but-not-urgent" category. > > But would it be 10/100/1000 ? or just 10/100 ? Just 10/100. User would choose GigE or 10/100 via an IFDEF in the Verilog. I suppose it would also be possible to multiplex in the simple_gemac with this 10/100 core and set the mode from the ZPU via the Wishbone interface. There is a tri-mode Ethernet MAC that Ettus used to use on the USRP2, but I've never been able to make much sense of it. If you have suggestions for a better way to add 10/100 support, I'm definitely interested in hearing them. > Also, doesn't UHD make use of the 'wait' feature of Gigabit (i.e. > PAUSE frames / flow control ) to avoid loosing data ? This doesn't > exist on 10/100 IIRC. > I'm not all that familiar with UHD, so you probably know better than I do. Perhaps Thomas could comment? -Robin -- Robin Coxe | Close-Haul Communications, Inc. | Boston, MA +1-617-470-8825 From s.milenkovic at limemicro.com Fri Jul 27 14:28:08 2012 From: s.milenkovic at limemicro.com (Srdjan Milenkovic) Date: Fri, 27 Jul 2012 15:28:08 +0100 Subject: DC Offset vs temperature In-Reply-To: References: <50112AAA.1040002@limemicro.com> Message-ID: <5012A578.5080908@limemicro.com> Hi Alexander, As I mentioned before, IQ phase error is quite stable over temperature in 900/1800MHz region so let us put it aside. This can be tuned and fixed in production. On the other hand, DC offset and LO leakage are temperature dependent as one would expect. However, they can be calibrated in the product as well not just in the lab. You need just to trigger built in DC cal blocks and optionally use RF loop back to further improve LO leakage. If you want to avoid temperature sensor you have an option to do these calibrations regularly, every 30min-1h for example. This should track the temperature change without having the sensor on board. Our other customers are using both approaches, with and without temperature sensor, depending on application and spec. If they have on board temperature sensor they are using it for multiple purpose such as monitoring BB, PA, etc. Best regards, Srdjan Dr Srdjan Milenkovic On 26/07/2012 16:48, Alexander Chemeris wrote: > On Thu, Jul 26, 2012 at 4:37 PM, Alexander Chemeris > wrote: >> On Thu, Jul 26, 2012 at 3:31 PM, Srdjan Milenkovic >> wrote: >>> Combining Thomas's idea of DC recalibration and, if necessary, making >>> look >>> up table for IQ phase error correction vs temperature should put us in >>> good >>> position to meet the specs. >> Well, AFAIK, LMS6002D doesn't have a temperature sensor built in and >> this means we have to install an external one, which again increase >> BoM cost. Is that's how this issue is solved by your other customers? >> I wonder is there a way to solve this without introducing a >> temperature compensation loop. > Let me clarify - DC offset re-calibration is (more or less) fine in > lab setup, but it's expensive to manufacture if we have to add > temperature sensors and put every unit into a temperature camera for > calibration. > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > -------------- next part -------------- An HTML attachment was scrubbed... URL: From plddesigner at gmail.com Fri Jul 27 19:20:39 2012 From: plddesigner at gmail.com (Andrew Karpenkov) Date: Fri, 27 Jul 2012 23:20:39 +0400 Subject: Plan for 10/100 Ethernet support for umTRX In-Reply-To: References: Message-ID: Hi All! May be it's easy just modify Ettus code for support Tri-Mode Ethernet. I think that it is not so difficult. In that way we can chose Ethernet PHY work mode from host. Also 'wait' feature (PAUSE frames / flow control) available not only for Gigabit Ethernet. Some 10/100 Ethernet Controllers support it (for example, LAN9218). Regards, Andrew Karpenkov 2012/7/27 Robin Coxe > Hi Sylvain. > > On Fri, Jul 27, 2012 at 9:04 AM, Sylvain Munaut <246tnt at gmail.com> wrote: > > Hi, > > > >> The Ettus UHD framework adopted for the umTRX only supports GigE > >> (simple_gemac). A reworked, Wishbone-compliant 10/100 Ethernet MAC > >> is included in the OpenRISC SoC project on Opencores. It has been > >> ported to the Digilent Atlys board, which has a Spartan-6 FPGA. > >> > >> http://www.chokladfabriken.org/projects/orpsoc-atlys > >> > >> I'll begin the port of this Ethernet MAC (a cleaned-up version of the > >> 10/100 core on OpenCores) to the UmTRX and test it on Close-Haul's > >> SP-605 Spartan-6 eval. board. I'm not quite sure how long this task > >> will take, but this feature falls into the > >> "nice-to-have-but-not-urgent" category. > > > > But would it be 10/100/1000 ? or just 10/100 ? > > Just 10/100. User would choose GigE or 10/100 via an IFDEF in the > Verilog. I suppose it would also be possible to multiplex in the > simple_gemac with this 10/100 core and set the mode from the ZPU via > the Wishbone interface. There is a tri-mode Ethernet MAC that Ettus > used to use on the USRP2, but I've never been able to make much sense > of it. If you have suggestions for a better way to add 10/100 > support, I'm definitely interested in hearing them. > > > Also, doesn't UHD make use of the 'wait' feature of Gigabit (i.e. > > PAUSE frames / flow control ) to avoid loosing data ? This doesn't > > exist on 10/100 IIRC. > > > > I'm not all that familiar with UHD, so you probably know better than I > do. Perhaps Thomas could comment? > > -Robin > > -- > Robin Coxe | Close-Haul Communications, Inc. | Boston, MA > +1-617-470-8825 > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From alexander.chemeris at gmail.com Sat Jul 28 02:15:57 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Sat, 28 Jul 2012 06:15:57 +0400 Subject: DC Offset vs temperature In-Reply-To: <5012A578.5080908@limemicro.com> References: <50112AAA.1040002@limemicro.com> <5012A578.5080908@limemicro.com> Message-ID: Hi Srdjan, Thank you for the comment. Unfortunately, we can't perform regular re-calibration, because a GSM base station can't stop transmitting. This means we need a full blow temperature sensor and this is a bad news, as we have to create UmTRXv3 to add it. This is something you should definitely consider for your next-gen chip - an embedded temperature sensor. Do you know how sensitive those parameters are to a temperature? I.e. should we calibrate adjust them every centigrade or every five centigrade? On Fri, Jul 27, 2012 at 6:28 PM, Srdjan Milenkovic wrote: > Hi Alexander, > > As I mentioned before, IQ phase error is quite stable over temperature in > 900/1800MHz region so let us put it aside. This can be tuned and fixed in > production. > > On the other hand, DC offset and LO leakage are temperature dependent as one > would expect. However, they can be calibrated in the product as well not > just in the lab. You need just to trigger built in DC cal blocks and > optionally use RF loop back to further improve LO leakage. If you want to > avoid temperature sensor you have an option to do these calibrations > regularly, every 30min-1h for example. This should track the temperature > change without having the sensor on board. > > Our other customers are using both approaches, with and without temperature > sensor, depending on application and spec. If they have on board temperature > sensor they are using it for multiple purpose such as monitoring BB, PA, > etc. > > Best regards, Srdjan > > > > On 26/07/2012 16:48, Alexander Chemeris wrote: > > On Thu, Jul 26, 2012 at 4:37 PM, Alexander Chemeris > wrote: > > On Thu, Jul 26, 2012 at 3:31 PM, Srdjan Milenkovic > wrote: > > Combining Thomas's idea of DC recalibration and, if necessary, making > look > up table for IQ phase error correction vs temperature should put us in > good > position to meet the specs. > > Well, AFAIK, LMS6002D doesn't have a temperature sensor built in and > this means we have to install an external one, which again increase > BoM cost. Is that's how this issue is solved by your other customers? > I wonder is there a way to solve this without introducing a > temperature compensation loop. > > Let me clarify - DC offset re-calibration is (more or less) fine in > lab setup, but it's expensive to manufacture if we have to add > temperature sensors and put every unit into a temperature camera for > calibration. > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > > -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From s.milenkovic at limemicro.com Sat Jul 28 10:33:28 2012 From: s.milenkovic at limemicro.com (Srdjan Milenkovic) Date: Sat, 28 Jul 2012 11:33:28 +0100 Subject: DC Offset vs temperature In-Reply-To: References: <50112AAA.1040002@limemicro.com> <5012A578.5080908@limemicro.com> Message-ID: <5013BFF8.8070006@limemicro.com> Hi Alexander, I understand. It is the same with WCDMA and other FDD modulation standards, BTS can not stop transmitting/receiving. However, we can not expect temperature to change from -40 to +85 deg C without doing anything about it. LMS is quite robust regarding temperature change. For example, PLL will stay locked within +/-20 deg C from the tuning point. The graph below shows DC/LO leakage calibration stability vs temperature. Applications based on OFDM (LTE, WiMAX for example) do not need to wary about DC/LO leakage recalibration as DC OFDM carrier is not used. Other modulation schemes will have to take care of this. If we define the spec of -60dBc LO leakage, the graph below shows that LMS IC is OK within +/-10 deg C offset from the calibration point. BTW, you do not need UmTRXv3 at the moment. You can build a small board with temperature sensor alone and interface it back to BB/FPGA. Best regards, Srdjan Dr Srdjan Milenkovic On 28/07/2012 03:15, Alexander Chemeris wrote: > Hi Srdjan, > > Thank you for the comment. > > Unfortunately, we can't perform regular re-calibration, because a GSM > base station can't stop transmitting. This means we need a full blow > temperature sensor and this is a bad news, as we have to create > UmTRXv3 to add it. This is something you should definitely consider > for your next-gen chip - an embedded temperature sensor. > > Do you know how sensitive those parameters are to a temperature? I.e. > should we calibrate adjust them every centigrade or every five > centigrade? > > On Fri, Jul 27, 2012 at 6:28 PM, Srdjan Milenkovic > wrote: >> Hi Alexander, >> >> As I mentioned before, IQ phase error is quite stable over temperature in >> 900/1800MHz region so let us put it aside. This can be tuned and fixed in >> production. >> >> On the other hand, DC offset and LO leakage are temperature dependent as one >> would expect. However, they can be calibrated in the product as well not >> just in the lab. You need just to trigger built in DC cal blocks and >> optionally use RF loop back to further improve LO leakage. If you want to >> avoid temperature sensor you have an option to do these calibrations >> regularly, every 30min-1h for example. This should track the temperature >> change without having the sensor on board. >> >> Our other customers are using both approaches, with and without temperature >> sensor, depending on application and spec. If they have on board temperature >> sensor they are using it for multiple purpose such as monitoring BB, PA, >> etc. >> >> Best regards, Srdjan >> >> >> >> On 26/07/2012 16:48, Alexander Chemeris wrote: >> >> On Thu, Jul 26, 2012 at 4:37 PM, Alexander Chemeris >> wrote: >> >> On Thu, Jul 26, 2012 at 3:31 PM, Srdjan Milenkovic >> wrote: >> >> Combining Thomas's idea of DC recalibration and, if necessary, making >> look >> up table for IQ phase error correction vs temperature should put us in >> good >> position to meet the specs. >> >> Well, AFAIK, LMS6002D doesn't have a temperature sensor built in and >> this means we have to install an external one, which again increase >> BoM cost. Is that's how this issue is solved by your other customers? >> I wonder is there a way to solve this without introducing a >> temperature compensation loop. >> >> Let me clarify - DC offset re-calibration is (more or less) fine in >> lab setup, but it's expensive to manufacture if we have to add >> temperature sensors and put every unit into a temperature camera for >> calibration. >> >> -- >> Regards, >> Alexander Chemeris. >> CEO, Fairwaves LLC / ??? ??????? >> http://fairwaves.ru >> >> > > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: afgfgeah.png Type: image/png Size: 22003 bytes Desc: not available URL: From andreysviyaz at gmail.com Sat Jul 28 15:17:32 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Sat, 28 Jul 2012 19:17:32 +0400 Subject: DC Offset vs temperature In-Reply-To: <5013BFF8.8070006@limemicro.com> References: <50112AAA.1040002@limemicro.com> <5012A578.5080908@limemicro.com> <5013BFF8.8070006@limemicro.com> Message-ID: Hi Srdjan. Can we measure of all important for us instabilities of calibrations vs temperature and then write it to EEPROM for mass production? I mean, do you have information about repeatability of curves (laws) of deg C instabilities for chips with same and different date codes of manufacture? Also, how near should be temperature sensor to the LSM chip? I mean, can be used averaged relative temperature of the housing heatsink, with known gradient, of course? Please recommend us measure method, even if we need personal temperature sensor for each onboard LMS's. Best regards, Andrey Sviyazov. 2012/7/28 Srdjan Milenkovic > Hi Alexander, > > I understand. It is the same with WCDMA and other FDD modulation > standards, BTS can not stop transmitting/receiving. However, we can not > expect temperature to change from -40 to +85 deg C without doing anything > about it. > > LMS is quite robust regarding temperature change. For example, PLL will > stay locked within +/-20 deg C from the tuning point. > > The graph below shows DC/LO leakage calibration stability vs temperature. > Applications based on OFDM (LTE, WiMAX for example) do not need to wary > about DC/LO leakage recalibration as DC OFDM carrier is not used. Other > modulation schemes will have to take care of this. If we define the spec of > -60dBc LO leakage, the graph below shows that LMS IC is OK within +/-10 deg > C offset from the calibration point. > > BTW, you do not need UmTRXv3 at the moment. You can build a small board > with temperature sensor alone and interface it back to BB/FPGA. > > Best regards, Srdjan > > > > > > ** ** > > **** > On 28/07/2012 03:15, Alexander Chemeris wrote: > > Hi Srdjan, > > Thank you for the comment. > > Unfortunately, we can't perform regular re-calibration, because a GSM > base station can't stop transmitting. This means we need a full blow > temperature sensor and this is a bad news, as we have to create > UmTRXv3 to add it. This is something you should definitely consider > for your next-gen chip - an embedded temperature sensor. > > Do you know how sensitive those parameters are to a temperature? I.e. > should we calibrate adjust them every centigrade or every five > centigrade? > > On Fri, Jul 27, 2012 at 6:28 PM, Srdjan Milenkovic wrote: > > Hi Alexander, > > As I mentioned before, IQ phase error is quite stable over temperature in > 900/1800MHz region so let us put it aside. This can be tuned and fixed in > production. > > On the other hand, DC offset and LO leakage are temperature dependent as one > would expect. However, they can be calibrated in the product as well not > just in the lab. You need just to trigger built in DC cal blocks and > optionally use RF loop back to further improve LO leakage. If you want to > avoid temperature sensor you have an option to do these calibrations > regularly, every 30min-1h for example. This should track the temperature > change without having the sensor on board. > > Our other customers are using both approaches, with and without temperature > sensor, depending on application and spec. If they have on board temperature > sensor they are using it for multiple purpose such as monitoring BB, PA, > etc. > > Best regards, Srdjan > > > > On 26/07/2012 16:48, Alexander Chemeris wrote: > > On Thu, Jul 26, 2012 at 4:37 PM, Alexander Chemeris wrote: > > On Thu, Jul 26, 2012 at 3:31 PM, Srdjan Milenkovic wrote: > > Combining Thomas's idea of DC recalibration and, if necessary, making > look > up table for IQ phase error correction vs temperature should put us in > good > position to meet the specs. > > Well, AFAIK, LMS6002D doesn't have a temperature sensor built in and > this means we have to install an external one, which again increase > BoM cost. Is that's how this issue is solved by your other customers? > I wonder is there a way to solve this without introducing a > temperature compensation loop. > > Let me clarify - DC offset re-calibration is (more or less) fine in > lab setup, but it's expensive to manufacture if we have to add > temperature sensors and put every unit into a temperature camera for > calibration. > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ???????http://fairwaves.ru > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From coxe at close-haul.com Sat Jul 28 15:44:18 2012 From: coxe at close-haul.com (Robin Coxe) Date: Sat, 28 Jul 2012 11:44:18 -0400 Subject: DC Offset vs temperature In-Reply-To: References: <50112AAA.1040002@limemicro.com> <5012A578.5080908@limemicro.com> <5013BFF8.8070006@limemicro.com> Message-ID: It might make sense to do some thermal cycle tests with a few temperature sensor breakout boards like this one: https://www.sparkfun.com/products/9418 On Sat, Jul 28, 2012 at 11:17 AM, Andrey Sviyazov wrote: > Hi Srdjan. > > Can we measure of all important for us instabilities of calibrations vs > temperature and then write it to EEPROM for mass production? > I mean, do you have information about repeatability of curves (laws) of > deg C instabilities for chips with same and different date codes of > manufacture? > > Also, how near should be temperature sensor to the LSM chip? > I mean, can be used averaged relative temperature of the housing heatsink, > with known gradient, of course? > Please recommend us measure method, even if we need personal temperature > sensor for each onboard LMS's. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/28 Srdjan Milenkovic > >> Hi Alexander, >> >> I understand. It is the same with WCDMA and other FDD modulation >> standards, BTS can not stop transmitting/receiving. However, we can not >> expect temperature to change from -40 to +85 deg C without doing anything >> about it. >> >> LMS is quite robust regarding temperature change. For example, PLL will >> stay locked within +/-20 deg C from the tuning point. >> >> The graph below shows DC/LO leakage calibration stability vs temperature. >> Applications based on OFDM (LTE, WiMAX for example) do not need to wary >> about DC/LO leakage recalibration as DC OFDM carrier is not used. Other >> modulation schemes will have to take care of this. If we define the spec of >> -60dBc LO leakage, the graph below shows that LMS IC is OK within +/-10 deg >> C offset from the calibration point. >> >> BTW, you do not need UmTRXv3 at the moment. You can build a small board >> with temperature sensor alone and interface it back to BB/FPGA. >> >> Best regards, Srdjan >> >> >> >> >> >> ** ** >> >> **** >> On 28/07/2012 03:15, Alexander Chemeris wrote: >> >> Hi Srdjan, >> >> Thank you for the comment. >> >> Unfortunately, we can't perform regular re-calibration, because a GSM >> base station can't stop transmitting. This means we need a full blow >> temperature sensor and this is a bad news, as we have to create >> UmTRXv3 to add it. This is something you should definitely consider >> for your next-gen chip - an embedded temperature sensor. >> >> Do you know how sensitive those parameters are to a temperature? I.e. >> should we calibrate adjust them every centigrade or every five >> centigrade? >> >> On Fri, Jul 27, 2012 at 6:28 PM, Srdjan Milenkovic wrote: >> >> Hi Alexander, >> >> As I mentioned before, IQ phase error is quite stable over temperature in >> 900/1800MHz region so let us put it aside. This can be tuned and fixed in >> production. >> >> On the other hand, DC offset and LO leakage are temperature dependent as one >> would expect. However, they can be calibrated in the product as well not >> just in the lab. You need just to trigger built in DC cal blocks and >> optionally use RF loop back to further improve LO leakage. If you want to >> avoid temperature sensor you have an option to do these calibrations >> regularly, every 30min-1h for example. This should track the temperature >> change without having the sensor on board. >> >> Our other customers are using both approaches, with and without temperature >> sensor, depending on application and spec. If they have on board temperature >> sensor they are using it for multiple purpose such as monitoring BB, PA, >> etc. >> >> Best regards, Srdjan >> >> >> >> On 26/07/2012 16:48, Alexander Chemeris wrote: >> >> On Thu, Jul 26, 2012 at 4:37 PM, Alexander Chemeris wrote: >> >> On Thu, Jul 26, 2012 at 3:31 PM, Srdjan Milenkovic wrote: >> >> Combining Thomas's idea of DC recalibration and, if necessary, making >> look >> up table for IQ phase error correction vs temperature should put us in >> good >> position to meet the specs. >> >> Well, AFAIK, LMS6002D doesn't have a temperature sensor built in and >> this means we have to install an external one, which again increase >> BoM cost. Is that's how this issue is solved by your other customers? >> I wonder is there a way to solve this without introducing a >> temperature compensation loop. >> >> Let me clarify - DC offset re-calibration is (more or less) fine in >> lab setup, but it's expensive to manufacture if we have to add >> temperature sensors and put every unit into a temperature camera for >> calibration. >> >> -- >> Regards, >> Alexander Chemeris. >> CEO, Fairwaves LLC / ??? ???????http://fairwaves.ru >> >> >> > -- Robin Coxe | Close-Haul Communications, Inc. | Boston, MA +1-617-470-8825 -------------- next part -------------- An HTML attachment was scrubbed... URL: From andreysviyaz at gmail.com Sat Jul 28 16:15:27 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Sat, 28 Jul 2012 20:15:27 +0400 Subject: DC Offset vs temperature In-Reply-To: References: <50112AAA.1040002@limemicro.com> <5012A578.5080908@limemicro.com> <5013BFF8.8070006@limemicro.com> Message-ID: Hi Robin. Yes, I know this TI sensor and I've suggested to Alexander to include similar in the UmTRXv2 board instead of fan controller. Unfortunately, it was when we didn't known about calibration problems vs temperature. So, now we should implement temperature compensation control in HOST and FPGA, but till for external sensors like you suggest. Of course, sensors would be onboard in UmTRXv3 as Alexander mentiones. Best regards, Andrey Sviyazov. 2012/7/28 Robin Coxe > It might make sense to do some thermal cycle tests with a few temperature > sensor breakout boards like this one: > https://www.sparkfun.com/products/9418 > > > On Sat, Jul 28, 2012 at 11:17 AM, Andrey Sviyazov wrote: > >> Hi Srdjan. >> >> Can we measure of all important for us instabilities of calibrations vs >> temperature and then write it to EEPROM for mass production? >> I mean, do you have information about repeatability of curves (laws) of >> deg C instabilities for chips with same and different date codes of >> manufacture? >> >> Also, how near should be temperature sensor to the LSM chip? >> I mean, can be used averaged relative temperature of the housing >> heatsink, with known gradient, of course? >> Please recommend us measure method, even if we need personal temperature >> sensor for each onboard LMS's. >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/28 Srdjan Milenkovic >> >>> Hi Alexander, >>> >>> I understand. It is the same with WCDMA and other FDD modulation >>> standards, BTS can not stop transmitting/receiving. However, we can not >>> expect temperature to change from -40 to +85 deg C without doing anything >>> about it. >>> >>> LMS is quite robust regarding temperature change. For example, PLL will >>> stay locked within +/-20 deg C from the tuning point. >>> >>> The graph below shows DC/LO leakage calibration stability vs >>> temperature. Applications based on OFDM (LTE, WiMAX for example) do not >>> need to wary about DC/LO leakage recalibration as DC OFDM carrier is not >>> used. Other modulation schemes will have to take care of this. If we define >>> the spec of -60dBc LO leakage, the graph below shows that LMS IC is OK >>> within +/-10 deg C offset from the calibration point. >>> >>> BTW, you do not need UmTRXv3 at the moment. You can build a small board >>> with temperature sensor alone and interface it back to BB/FPGA. >>> >>> Best regards, Srdjan >>> >>> >>> >>> >>> >>> ** ** >>> >>> **** >>> On 28/07/2012 03:15, Alexander Chemeris wrote: >>> >>> Hi Srdjan, >>> >>> Thank you for the comment. >>> >>> Unfortunately, we can't perform regular re-calibration, because a GSM >>> base station can't stop transmitting. This means we need a full blow >>> temperature sensor and this is a bad news, as we have to create >>> UmTRXv3 to add it. This is something you should definitely consider >>> for your next-gen chip - an embedded temperature sensor. >>> >>> Do you know how sensitive those parameters are to a temperature? I.e. >>> should we calibrate adjust them every centigrade or every five >>> centigrade? >>> >>> On Fri, Jul 27, 2012 at 6:28 PM, Srdjan Milenkovic wrote: >>> >>> Hi Alexander, >>> >>> As I mentioned before, IQ phase error is quite stable over temperature in >>> 900/1800MHz region so let us put it aside. This can be tuned and fixed in >>> production. >>> >>> On the other hand, DC offset and LO leakage are temperature dependent as one >>> would expect. However, they can be calibrated in the product as well not >>> just in the lab. You need just to trigger built in DC cal blocks and >>> optionally use RF loop back to further improve LO leakage. If you want to >>> avoid temperature sensor you have an option to do these calibrations >>> regularly, every 30min-1h for example. This should track the temperature >>> change without having the sensor on board. >>> >>> Our other customers are using both approaches, with and without temperature >>> sensor, depending on application and spec. If they have on board temperature >>> sensor they are using it for multiple purpose such as monitoring BB, PA, >>> etc. >>> >>> Best regards, Srdjan >>> >>> >>> >>> On 26/07/2012 16:48, Alexander Chemeris wrote: >>> >>> On Thu, Jul 26, 2012 at 4:37 PM, Alexander Chemeris wrote: >>> >>> On Thu, Jul 26, 2012 at 3:31 PM, Srdjan Milenkovic wrote: >>> >>> Combining Thomas's idea of DC recalibration and, if necessary, making >>> look >>> up table for IQ phase error correction vs temperature should put us in >>> good >>> position to meet the specs. >>> >>> Well, AFAIK, LMS6002D doesn't have a temperature sensor built in and >>> this means we have to install an external one, which again increase >>> BoM cost. Is that's how this issue is solved by your other customers? >>> I wonder is there a way to solve this without introducing a >>> temperature compensation loop. >>> >>> Let me clarify - DC offset re-calibration is (more or less) fine in >>> lab setup, but it's expensive to manufacture if we have to add >>> temperature sensors and put every unit into a temperature camera for >>> calibration. >>> >>> -- >>> Regards, >>> Alexander Chemeris. >>> CEO, Fairwaves LLC / ??? ???????http://fairwaves.ru >>> >>> >>> >> > > > -- > Robin Coxe | Close-Haul Communications, Inc. | Boston, MA > +1-617-470-8825 > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andreysviyaz at gmail.com Sat Jul 28 16:48:04 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Sat, 28 Jul 2012 20:48:04 +0400 Subject: DC Offset vs temperature In-Reply-To: References: <50112AAA.1040002@limemicro.com> <5012A578.5080908@limemicro.com> <5013BFF8.8070006@limemicro.com> Message-ID: BTW, due to ultra low active quiescent current of TMP102 we can reading and powering several sensors via FPGA io pins of debug connector. Best regards, Andrey Sviyazov. 2012/7/28 Andrey Sviyazov > Hi Robin. > > Yes, I know this TI sensor and I've suggested to Alexander to include > similar in the UmTRXv2 board instead of fan controller. > Unfortunately, it was when we didn't known about calibration problems vs > temperature. > So, now we should implement temperature compensation control in HOST and > FPGA, but till for external sensors like you suggest. > Of course, sensors would be onboard in UmTRXv3 as Alexander mentiones. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/28 Robin Coxe > >> It might make sense to do some thermal cycle tests with a few temperature >> sensor breakout boards like this one: >> https://www.sparkfun.com/products/9418 >> >> >> On Sat, Jul 28, 2012 at 11:17 AM, Andrey Sviyazov > > wrote: >> >>> Hi Srdjan. >>> >>> Can we measure of all important for us instabilities of calibrations vs >>> temperature and then write it to EEPROM for mass production? >>> I mean, do you have information about repeatability of curves (laws) of >>> deg C instabilities for chips with same and different date codes of >>> manufacture? >>> >>> Also, how near should be temperature sensor to the LSM chip? >>> I mean, can be used averaged relative temperature of the housing >>> heatsink, with known gradient, of course? >>> Please recommend us measure method, even if we need personal temperature >>> sensor for each onboard LMS's. >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/28 Srdjan Milenkovic >>> >>>> Hi Alexander, >>>> >>>> I understand. It is the same with WCDMA and other FDD modulation >>>> standards, BTS can not stop transmitting/receiving. However, we can not >>>> expect temperature to change from -40 to +85 deg C without doing anything >>>> about it. >>>> >>>> LMS is quite robust regarding temperature change. For example, PLL will >>>> stay locked within +/-20 deg C from the tuning point. >>>> >>>> The graph below shows DC/LO leakage calibration stability vs >>>> temperature. Applications based on OFDM (LTE, WiMAX for example) do not >>>> need to wary about DC/LO leakage recalibration as DC OFDM carrier is not >>>> used. Other modulation schemes will have to take care of this. If we define >>>> the spec of -60dBc LO leakage, the graph below shows that LMS IC is OK >>>> within +/-10 deg C offset from the calibration point. >>>> >>>> BTW, you do not need UmTRXv3 at the moment. You can build a small board >>>> with temperature sensor alone and interface it back to BB/FPGA. >>>> >>>> Best regards, Srdjan >>>> >>>> >>>> >>>> >>>> >>>> ** ** >>>> >>>> **** >>>> On 28/07/2012 03:15, Alexander Chemeris wrote: >>>> >>>> Hi Srdjan, >>>> >>>> Thank you for the comment. >>>> >>>> Unfortunately, we can't perform regular re-calibration, because a GSM >>>> base station can't stop transmitting. This means we need a full blow >>>> temperature sensor and this is a bad news, as we have to create >>>> UmTRXv3 to add it. This is something you should definitely consider >>>> for your next-gen chip - an embedded temperature sensor. >>>> >>>> Do you know how sensitive those parameters are to a temperature? I.e. >>>> should we calibrate adjust them every centigrade or every five >>>> centigrade? >>>> >>>> On Fri, Jul 27, 2012 at 6:28 PM, Srdjan Milenkovic wrote: >>>> >>>> Hi Alexander, >>>> >>>> As I mentioned before, IQ phase error is quite stable over temperature in >>>> 900/1800MHz region so let us put it aside. This can be tuned and fixed in >>>> production. >>>> >>>> On the other hand, DC offset and LO leakage are temperature dependent as one >>>> would expect. However, they can be calibrated in the product as well not >>>> just in the lab. You need just to trigger built in DC cal blocks and >>>> optionally use RF loop back to further improve LO leakage. If you want to >>>> avoid temperature sensor you have an option to do these calibrations >>>> regularly, every 30min-1h for example. This should track the temperature >>>> change without having the sensor on board. >>>> >>>> Our other customers are using both approaches, with and without temperature >>>> sensor, depending on application and spec. If they have on board temperature >>>> sensor they are using it for multiple purpose such as monitoring BB, PA, >>>> etc. >>>> >>>> Best regards, Srdjan >>>> >>>> >>>> >>>> On 26/07/2012 16:48, Alexander Chemeris wrote: >>>> >>>> On Thu, Jul 26, 2012 at 4:37 PM, Alexander Chemeris wrote: >>>> >>>> On Thu, Jul 26, 2012 at 3:31 PM, Srdjan Milenkovic wrote: >>>> >>>> Combining Thomas's idea of DC recalibration and, if necessary, making >>>> look >>>> up table for IQ phase error correction vs temperature should put us in >>>> good >>>> position to meet the specs. >>>> >>>> Well, AFAIK, LMS6002D doesn't have a temperature sensor built in and >>>> this means we have to install an external one, which again increase >>>> BoM cost. Is that's how this issue is solved by your other customers? >>>> I wonder is there a way to solve this without introducing a >>>> temperature compensation loop. >>>> >>>> Let me clarify - DC offset re-calibration is (more or less) fine in >>>> lab setup, but it's expensive to manufacture if we have to add >>>> temperature sensors and put every unit into a temperature camera for >>>> calibration. >>>> >>>> -- >>>> Regards, >>>> Alexander Chemeris. >>>> CEO, Fairwaves LLC / ??? ???????http://fairwaves.ru >>>> >>>> >>>> >>> >> >> >> -- >> Robin Coxe | Close-Haul Communications, Inc. | Boston, MA >> +1-617-470-8825 >> > > -------------- next part -------------- An HTML attachment was scrubbed... URL: From ttsou at vt.edu Mon Jul 30 02:37:54 2012 From: ttsou at vt.edu (Thomas Tsou) Date: Sun, 29 Jul 2012 22:37:54 -0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Andrey, Parts arrived yesterday and I made modifications for the 100 kHz loop filter and tested today. The entire 900 band is below 1.5 / 5 with a good margin. http://filebox.vt.edu/users/ttsou/http/umtrx_945mhz_4.bmp The lower part of the 1800 is also below the target value. I was not successful at 1885 MHz, though further calibration is possible (manual calibration at each frequency takes a very long time). I will perform additional tests tomorrow. http://filebox.vt.edu/users/ttsou/http/umtrx_1825mhz_4.bmp http://filebox.vt.edu/users/ttsou/http/umtrx_1825mhz_noise.PNG Thomas On Wed, Jul 25, 2012 at 9:52 PM, Thomas Tsou wrote: > On Wed, Jul 25, 2012 at 1:41 PM, Andrey Sviyazov > wrote: >> Hi Thomas. >> >> Digikey part numbers links: >> C82 = 100pF, C83=1500pF, C84=33pF, R106=2.2k, R109=3.3k, L6=0.022uF. >> >> But you'll remove 100pF capasitor from position C45, so you could use it for >> C82. >> BTW, how long time required to delivering from the DigiKey? > > Thank you for the links. Parts are ordered. Digikey orders usually > arrives in 2 days. > > Thomas From andrey.sviyazov at fairwaves.ru Mon Jul 30 08:07:58 2012 From: andrey.sviyazov at fairwaves.ru (Andrey Sviyazov) Date: Mon, 30 Jul 2012 12:07:58 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi Thomas. Thank you very much for good news. Sylvain and everybody who discussed, thanks a lot. Seems, now I could finalize new revison of the BOM. Best regards, Andrey Sviyazov. 2012/7/30 Thomas Tsou > Hi Andrey, > > Parts arrived yesterday and I made modifications for the 100 kHz loop > filter and tested today. The entire 900 band is below 1.5 / 5 with a > good margin. > > http://filebox.vt.edu/users/ttsou/http/umtrx_945mhz_4.bmp > > The lower part of the 1800 is also below the target value. I was not > successful at 1885 MHz, though further calibration is possible (manual > calibration at each frequency takes a very long time). I will perform > additional tests tomorrow. > > http://filebox.vt.edu/users/ttsou/http/umtrx_1825mhz_4.bmp > http://filebox.vt.edu/users/ttsou/http/umtrx_1825mhz_noise.PNG > > Thomas > > On Wed, Jul 25, 2012 at 9:52 PM, Thomas Tsou wrote: > > On Wed, Jul 25, 2012 at 1:41 PM, Andrey Sviyazov > > wrote: > >> Hi Thomas. > >> > >> Digikey part numbers links: > >> C82 = 100pF, C83=1500pF, C84=33pF, R106=2.2k, R109=3.3k, L6=0.022uF. > >> > >> But you'll remove 100pF capasitor from position C45, so you could use > it for > >> C82. > >> BTW, how long time required to delivering from the DigiKey? > > > > Thank you for the links. Parts are ordered. Digikey orders usually > > arrives in 2 days. > > > > Thomas > -------------- next part -------------- An HTML attachment was scrubbed... URL: From andreysviyaz at gmail.com Mon Jul 30 12:20:06 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Mon, 30 Jul 2012 16:20:06 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Hi Jean-Samuel. Here are attached last versions of interactive PDF for assembly and schema, and BOM (rename zi_ to zip first). List of components which are changed: L6-1, L6-2 = R0603 0 Ohm instead of choke C45-1, C45-2 = Do Not Install C82-1, C82-2, C98-1, C98-2 = 100pF instead of 470pF C83-1, C83-2, C99-1, C99-2 = 1500pF instead of 8.2nF C84-1, C84-2, C97-1, C97-2 = 33pF instead of 150pF R106-1, R106-2, R121-1, R121-2 = 2k2 instead of 820 Ohm R109-1, R109-2, R119-1, R119-2 = 3k3 instead of 1.2 kOhm Best regards, Andrey Sviyazov. 2012/7/25 Andrey Sviyazov > Hi Jean-Samuel. > > First of all you're right, we can't delay production. > So, I am sure it is better if PCB production will continue as you suggest. > > There are only three hardware issues which have to be solved before > assembling: > 1) Improving LMS phase noise. > It is almost done and Alexander wrote you which component need to order. > > 2) Digital noise which born in GPS module 230. > In ver.2 we will use GPS module 570, but I am afraid that we can get the > same problems. > So, I need 1-2 days to workaround this issue. > And also we have to understand either it important or it doesn't because > this noises hided under modulation. > > 3) LMS engineers suggested us to use PLL loop filter 100kHz instead 50kHz. > In case of 100kHz we have to decrease charge-pump current from 1.2-1.9mA > down to 0.4mA, but I am afraid about integral phase noise of LO because > (possible) it can affect modulation phase error (in degrees). > I think, required 1-2 days (the same days) to understand this also. > > So, at Thirsday I will send you final BOM and assembly files. > Hope it doesn't delay production, otherwise tell me and we'll hurry up. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/24 Alexander Chemeris > >> Hi Jean-Samuel, >> >> We're sitting together with Andrey Sviyazov now and he says that it's >> fine to continue with this PCB. >> >> You will need 40pcs of this 0 Ohm jumpers (2pcs per board): >> >> http://fr.farnell.com/bourns/cr0603-j-000elf/resistor-0603-0r-5-0-1w/dp/2008343 >> >> Andrey will update the schematics and BoM later today. >> >> On Tue, Jul 24, 2012 at 2:13 PM, Jean-Samuel Najnudel - BJT PARTNERS >> SARL wrote: >> > Hi Andrey, >> > >> > PCB copper is ready yet. We will lose 560 Euros and 3 weeks delay if we >> > change the copper. It is not impossible, we can decide to do that but I >> > would suggest we change the PCB for the next batch. After testing the v2 >> > board, you may found more changes we need on the copper. >> > >> > The board itself is not ready. We can change some passives. This will >> not >> > cost anything (or almost) and extra delay will be just one or two days >> at >> > most. >> > >> > Please let me know what you want to do about the PCB. >> > >> > Please let me know the exact passives modifications. I will purchase the >> > components asap and send the modifications list to the fab. >> > >> > Best regards. >> > >> > Jean-Samuel. >> > :-) >> > >> > Le 23 juil. 2012 22:47, "Andrey Sviyazov" a >> ?crit : >> > >> >> Hi Jean-Samuel. >> >> >> >> Please let me know fabrication progress, a specially PCB. >> >> I ask you because of few changes required to improve LMS phase noises. >> >> BOM required changes in passive components only. >> >> If PCB doesn't yet ordered, then possible I'll make changes too. >> >> >> >> Best regards, >> >> Andrey Sviyazov. >> >> (Sent from my mobile client) >> >> >> >> 04.07.2012 20:01 ???????????? "Jean-Samuel Najnudel - BJT PARTNERS >> SARL" >> >> ???????: >> >>> >> >>> Hi Andrey, >> >>> >> >>> Thank you very much for your help. >> >>> >> >>> I will forward this to the fab. >> >>> Yes, you are all right, the FBMH2012HM121-T price is much better than >> the >> >>> MLB-201209-0120PU. However, availability on Farnell France is not as >> good as >> >>> the MLB-201209-0120PU. Price difference is quite big but we only use >> 5 beads >> >>> per boards. Difference makes only about 1 euro per board. I will let >> the fab >> >>> decide between these 2 references. >> >>> >> >>> Best regards. >> >>> >> >>> Jean-Samuel. >> >>> :-) >> >>> >> >>> >> >>> On Wed, Jul 4, 2012 at 4:30 PM, Andrey Sviyazov < >> andreysviyaz at gmail.com> >> >>> wrote: >> >>>> >> >>>> Hi Jean-Samuel. >> >>>> >> >>>> Yes, you are all right and you can order TDK - MPZ1608S601A instead >> of >> >>>> MLB-160808-0600PL. >> >>>> And also possible to use 3 times cheaper FBMH2012HM121-T, 0805, 2.5A >> >>>> instead of MLB-201209-0120PU. >> >>>> >> >>>> Best regards, >> >>>> Andrey Sviyazov. >> >>>> >> >>>> >> >>>> >> >>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL < >> jsn at bjtpartners.com> >> >>>>> >> >>>>> Hi Andrey, >> >>>>> >> >>>>> Thank you very much for your reply. >> >>>>> Now, I better understand. >> >>>>> >> >>>>> You are all right. I do not have anything as high current as >> >>>>> MLB-201209-0120PU at a lower price. >> >>>>> >> >>>>> However, I have a 0603 600 ohm 1A bead, as MLB-160808-0600PL, at a >> much >> >>>>> lower price. >> >>>>> >> >>>>> >> http://ru.farnell.com/tdk/mpz1608s601a/ferrite-bead-0603-600-ohm/dp/1669747RL >> >>>>> What do you think about this component (TDK MPZ1608S601A)? >> >>>>> >> >>>>> Best regards. >> >>>>> >> >>>>> Jean-Samuel. >> >>>>> :-) >> >>>>> >> >>>>> >> >>>>> >> >>>>> On Wed, Jul 4, 2012 at 3:22 PM, Andrey Sviyazov >> >>>>> wrote: >> >>>>>> >> >>>>>> Hi Jean-Samuel. >> >>>>>> >> >>>>>> If Farnell better for you, then please order exactly >> MLB-201209-0120PU >> >>>>>> and MLB-160808-0600PL. >> >>>>>> They are HI_CURRENT beads and it is really required. >> >>>>>> >> >>>>>> Please find attached here new SCH and BOM files with new part >> numbers >> >>>>>> and links. >> >>>>>> >> >>>>>> Best regards, >> >>>>>> Andrey Sviyazov. >> >>>>>> >> >>>>>> >> >>>>>> >> >>>>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >> >>>>>> >> >>>>>>> >> >>>>>>> Hi Andrey, >> >>>>>>> >> >>>>>>> Thank you very much for your reply. >> >>>>>>> >> >>>>>>> Could you please confirm the components bellow are fine ? >> >>>>>>> >> >>>>>>> >> http://fr.farnell.com/murata/blm18tg601tn1d/ferrite-600ohm/dp/1115050RL >> >>>>>>> >> >>>>>>> >> http://fr.farnell.com/tdk/mmz2012121b/perle-de-ferrite-0805-120-ohm/dp/1669728RL >> >>>>>>> >> >>>>>>> Please let me know if this is fine. >> >>>>>>> If not, which would you suggest ? >> >>>>>>> http://ru.farnell.com/ferrite-beads >> >>>>>>> >> >>>>>>> >> >>>>>>> Thanks a lot for your help. >> >>>>>>> >> >>>>>>> Best regards. >> >>>>>>> >> >>>>>>> Jean-Samuel. >> >>>>>>> :-) >> >>>>>>> >> >>>>>>> >> >>>>>>> On Wed, Jul 4, 2012 at 2:02 PM, Andrey Sviyazov >> >>>>>>> wrote: >> >>>>>>>> >> >>>>>>>> Hi Jean-Samuel. >> >>>>>>>> >> >>>>>>>> For the TI160808U601 and TI201209U121 you can use any high >> current >> >>>>>>>> ferrite chip bead with 600 Ohm and 120 Ohm impedance >> respectively. >> >>>>>>>> For example you could order similar partnumbers from the ELFA >> >>>>>>>> catalogue in the 0603 and 0805 SMD cases respectively, datasheet >> here pdf. >> >>>>>>>> >> >>>>>>>> Best regards, >> >>>>>>>> Andrey Sviyazov. >> >>>>>>>> >> >>>>>>>> >> >>>>>>>> >> >>>>>>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >> >>>>>>>> >> >>>>>>>>> >> >>>>>>>>> Hi Andrey, >> >>>>>>>>> >> >>>>>>>>> Thank you very much for your reply. >> >>>>>>>>> >> >>>>>>>>> I try to find where to buy the TI160808U601 and TI201209-121 >> >>>>>>>>> chokes. I do not know where I should find these. Would you know >> where I >> >>>>>>>>> should order these components ? >> >>>>>>>>> >> >>>>>>>>> By the way, do you confirm the ISSI SRAM is pin compatible with >> the >> >>>>>>>>> Cypress chip ? >> >>>>>>>>> >> >>>>>>>>> >> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >> >>>>>>>>> >> >>>>>>>>> Is this ISSI chip fine for our application ? Is 18 MBit enough ? >> >>>>>>>>> Do you confirm this ISSI chip is the best value for what we >> need ? >> >>>>>>>>> Are you sure we cannot find a lower cost chip with similar >> performances >> >>>>>>>>> and/or a better performances chip with similar cost ? >> >>>>>>>>> Are you sure we will not need to reroute the PCB ? >> >>>>>>>>> >> >>>>>>>>> We really need to be sure before starting the PCB production. If >> >>>>>>>>> both you and Alexander confirm everything is fine, I will ask >> the fab to >> >>>>>>>>> start the PCB. >> >>>>>>>>> >> >>>>>>>>> Please let me know. >> >>>>>>>>> >> >>>>>>>>> Again, thanks a lot for your help. >> >>>>>>>>> >> >>>>>>>>> Best regards. >> >>>>>>>>> >> >>>>>>>>> Jean-Samuel. >> >>>>>>>>> :-) >> >>>>>>>>> >> >>>>>>>>> >> >>>>>>>>> >> >>>>>>>>> On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov >> >>>>>>>>> wrote: >> >>>>>>>>>> >> >>>>>>>>>> Jean-Samuel. >> >>>>>>>>>> >> >>>>>>>>>> Please inform me what actually rf chockes partnumbers are >> problem >> >>>>>>>>>> to order. >> >>>>>>>>>> Unfortunately MuRata produce few billion pcs and then stopped >> for >> >>>>>>>>>> a few years. >> >>>>>>>>>> So, possible we have to find some Chinese fab partnumbers to >> >>>>>>>>>> order. >> >>>>>>>>>> >> >>>>>>>>>> Best regards, >> >>>>>>>>>> Andrey Sviyazov. >> >>>>>>>>>> (Sent from my mobile client) >> >>>>>>>>>> >> >>>>>>>>>> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" >> >>>>>>>>>> ???????: >> >>>>>>>>>> >> >>>>>>>>>>> Hi Jean-Samuel. >> >>>>>>>>>>> Unfortunately I have no internet connection now. >> >>>>>>>>>>> Tomorrow I'll check flash and others. >> >>>>>>>>>>> >> >>>>>>>>>>> Best regards, >> >>>>>>>>>>> Andrey Sviyazov. >> >>>>>>>>>>> (Sent from my mobile client) >> >>>>>>>>>>> >> >>>>>>>>>>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" >> >>>>>>>>>>> ???????: >> >>>>>>>>>>> > >> >>>>>>>>>>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT >> >>>>>>>>>>> > PARTNERS >> >>>>>>>>>>> > SARL wrote: >> >>>>>>>>>>> > > 1/ Would you know a distributor for the Murata chokes ? >> The >> >>>>>>>>>>> > > fab them to have >> >>>>>>>>>>> > > some issue to source these. >> >>>>>>>>>>> > >> >>>>>>>>>>> > Andrey is looking into this. >> >>>>>>>>>>> > >> >>>>>>>>>>> > > 2/ Would you suggest a distributor for the GPS chip ? >> >>>>>>>>>>> > >> >>>>>>>>>>> > Try contacting manufacturer directly: >> >>>>>>>>>>> > >> >>>>>>>>>>> > >> http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >> >>>>>>>>>>> > >> >>>>>>>>>>> > They have a distributor in UK, but I think it might be >> easier >> >>>>>>>>>>> > to buy >> >>>>>>>>>>> > from the manufacturer directly: >> >>>>>>>>>>> > http://www.castlemicrowave.com/castle-contact.asp >> >>>>>>>>>>> > >> >>>>>>>>>>> > This chip is popular in Russia, so it is easy to source them >> >>>>>>>>>>> > here, >> >>>>>>>>>>> > shipping them to EU might be a pain in big batches, but I >> think >> >>>>>>>>>>> > we >> >>>>>>>>>>> > could send few chips for this prototyping batch if >> >>>>>>>>>>> > manufacturer's lead >> >>>>>>>>>>> > time is too long. Here it costs $14.50/chip for more then 16 >> >>>>>>>>>>> > chips: >> >>>>>>>>>>> > http://www.compel.ru/infosheet/TSI/EB-570/ >> >>>>>>>>>>> > >> >>>>>>>>>>> > -- >> >>>>>>>>>>> > Regards, >> >>>>>>>>>>> > Alexander Chemeris. >> >>>>>>>>>>> > CEO, Fairwaves LLC / ??? ??????? >> >>>>>>>>>>> > http://fairwaves.ru >> >>>>>>>>> >> >>>>>>>>> >> >>>>>>>> >> >>>>>>> >> >>>>>> >> >>>>> >> >>>> >> >>> >> > >> >> >> >> -- >> Regards, >> Alexander Chemeris. >> CEO, Fairwaves LLC / ??? ??????? >> http://fairwaves.ru >> > > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: UmTRXv2_300712.zi_ Type: application/octet-stream Size: 2091450 bytes Desc: not available URL: From andreysviyaz at gmail.com Mon Jul 30 12:22:41 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Mon, 30 Jul 2012 16:22:41 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Here project, sch and pcb files. Best regards, Andrey Sviyazov. 2012/7/30 Andrey Sviyazov > Hi Jean-Samuel. > > Here are attached last versions of interactive PDF for assembly > and schema, and BOM (rename zi_ to zip first). > List of components which are changed: > L6-1, L6-2 = R0603 0 Ohm instead of choke > C45-1, C45-2 = Do Not Install > C82-1, C82-2, C98-1, C98-2 = 100pF instead of 470pF > C83-1, C83-2, C99-1, C99-2 = 1500pF instead of 8.2nF > C84-1, C84-2, C97-1, C97-2 = 33pF instead of 150pF > R106-1, R106-2, R121-1, R121-2 = 2k2 instead of 820 Ohm > R109-1, R109-2, R119-1, R119-2 = 3k3 instead of 1.2 kOhm > > Best regards, > Andrey Sviyazov. > > > > 2012/7/25 Andrey Sviyazov > >> Hi Jean-Samuel. >> >> First of all you're right, we can't delay production. >> So, I am sure it is better if PCB production will continue as you suggest. >> >> There are only three hardware issues which have to be solved before >> assembling: >> 1) Improving LMS phase noise. >> It is almost done and Alexander wrote you which component need to order. >> >> 2) Digital noise which born in GPS module 230. >> In ver.2 we will use GPS module 570, but I am afraid that we can get the >> same problems. >> So, I need 1-2 days to workaround this issue. >> And also we have to understand either it important or it doesn't because >> this noises hided under modulation. >> >> 3) LMS engineers suggested us to use PLL loop filter 100kHz instead 50kHz. >> In case of 100kHz we have to decrease charge-pump current from 1.2-1.9mA >> down to 0.4mA, but I am afraid about integral phase noise of LO because >> (possible) it can affect modulation phase error (in degrees). >> I think, required 1-2 days (the same days) to understand this also. >> >> So, at Thirsday I will send you final BOM and assembly files. >> Hope it doesn't delay production, otherwise tell me and we'll hurry up. >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/24 Alexander Chemeris >> >>> Hi Jean-Samuel, >>> >>> We're sitting together with Andrey Sviyazov now and he says that it's >>> fine to continue with this PCB. >>> >>> You will need 40pcs of this 0 Ohm jumpers (2pcs per board): >>> >>> http://fr.farnell.com/bourns/cr0603-j-000elf/resistor-0603-0r-5-0-1w/dp/2008343 >>> >>> Andrey will update the schematics and BoM later today. >>> >>> On Tue, Jul 24, 2012 at 2:13 PM, Jean-Samuel Najnudel - BJT PARTNERS >>> SARL wrote: >>> > Hi Andrey, >>> > >>> > PCB copper is ready yet. We will lose 560 Euros and 3 weeks delay if we >>> > change the copper. It is not impossible, we can decide to do that but I >>> > would suggest we change the PCB for the next batch. After testing the >>> v2 >>> > board, you may found more changes we need on the copper. >>> > >>> > The board itself is not ready. We can change some passives. This will >>> not >>> > cost anything (or almost) and extra delay will be just one or two days >>> at >>> > most. >>> > >>> > Please let me know what you want to do about the PCB. >>> > >>> > Please let me know the exact passives modifications. I will purchase >>> the >>> > components asap and send the modifications list to the fab. >>> > >>> > Best regards. >>> > >>> > Jean-Samuel. >>> > :-) >>> > >>> > Le 23 juil. 2012 22:47, "Andrey Sviyazov" a >>> ?crit : >>> > >>> >> Hi Jean-Samuel. >>> >> >>> >> Please let me know fabrication progress, a specially PCB. >>> >> I ask you because of few changes required to improve LMS phase noises. >>> >> BOM required changes in passive components only. >>> >> If PCB doesn't yet ordered, then possible I'll make changes too. >>> >> >>> >> Best regards, >>> >> Andrey Sviyazov. >>> >> (Sent from my mobile client) >>> >> >>> >> 04.07.2012 20:01 ???????????? "Jean-Samuel Najnudel - BJT PARTNERS >>> SARL" >>> >> ???????: >>> >>> >>> >>> Hi Andrey, >>> >>> >>> >>> Thank you very much for your help. >>> >>> >>> >>> I will forward this to the fab. >>> >>> Yes, you are all right, the FBMH2012HM121-T price is much better >>> than the >>> >>> MLB-201209-0120PU. However, availability on Farnell France is not as >>> good as >>> >>> the MLB-201209-0120PU. Price difference is quite big but we only use >>> 5 beads >>> >>> per boards. Difference makes only about 1 euro per board. I will let >>> the fab >>> >>> decide between these 2 references. >>> >>> >>> >>> Best regards. >>> >>> >>> >>> Jean-Samuel. >>> >>> :-) >>> >>> >>> >>> >>> >>> On Wed, Jul 4, 2012 at 4:30 PM, Andrey Sviyazov < >>> andreysviyaz at gmail.com> >>> >>> wrote: >>> >>>> >>> >>>> Hi Jean-Samuel. >>> >>>> >>> >>>> Yes, you are all right and you can order TDK - MPZ1608S601A instead >>> of >>> >>>> MLB-160808-0600PL. >>> >>>> And also possible to use 3 times cheaper FBMH2012HM121-T, 0805, 2.5A >>> >>>> instead of MLB-201209-0120PU. >>> >>>> >>> >>>> Best regards, >>> >>>> Andrey Sviyazov. >>> >>>> >>> >>>> >>> >>>> >>> >>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL < >>> jsn at bjtpartners.com> >>> >>>>> >>> >>>>> Hi Andrey, >>> >>>>> >>> >>>>> Thank you very much for your reply. >>> >>>>> Now, I better understand. >>> >>>>> >>> >>>>> You are all right. I do not have anything as high current as >>> >>>>> MLB-201209-0120PU at a lower price. >>> >>>>> >>> >>>>> However, I have a 0603 600 ohm 1A bead, as MLB-160808-0600PL, at a >>> much >>> >>>>> lower price. >>> >>>>> >>> >>>>> >>> http://ru.farnell.com/tdk/mpz1608s601a/ferrite-bead-0603-600-ohm/dp/1669747RL >>> >>>>> What do you think about this component (TDK MPZ1608S601A)? >>> >>>>> >>> >>>>> Best regards. >>> >>>>> >>> >>>>> Jean-Samuel. >>> >>>>> :-) >>> >>>>> >>> >>>>> >>> >>>>> >>> >>>>> On Wed, Jul 4, 2012 at 3:22 PM, Andrey Sviyazov >>> >>>>> wrote: >>> >>>>>> >>> >>>>>> Hi Jean-Samuel. >>> >>>>>> >>> >>>>>> If Farnell better for you, then please order exactly >>> MLB-201209-0120PU >>> >>>>>> and MLB-160808-0600PL. >>> >>>>>> They are HI_CURRENT beads and it is really required. >>> >>>>>> >>> >>>>>> Please find attached here new SCH and BOM files with new part >>> numbers >>> >>>>>> and links. >>> >>>>>> >>> >>>>>> Best regards, >>> >>>>>> Andrey Sviyazov. >>> >>>>>> >>> >>>>>> >>> >>>>>> >>> >>>>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>> >>>>>> >>> >>>>>>> >>> >>>>>>> Hi Andrey, >>> >>>>>>> >>> >>>>>>> Thank you very much for your reply. >>> >>>>>>> >>> >>>>>>> Could you please confirm the components bellow are fine ? >>> >>>>>>> >>> >>>>>>> >>> http://fr.farnell.com/murata/blm18tg601tn1d/ferrite-600ohm/dp/1115050RL >>> >>>>>>> >>> >>>>>>> >>> http://fr.farnell.com/tdk/mmz2012121b/perle-de-ferrite-0805-120-ohm/dp/1669728RL >>> >>>>>>> >>> >>>>>>> Please let me know if this is fine. >>> >>>>>>> If not, which would you suggest ? >>> >>>>>>> http://ru.farnell.com/ferrite-beads >>> >>>>>>> >>> >>>>>>> >>> >>>>>>> Thanks a lot for your help. >>> >>>>>>> >>> >>>>>>> Best regards. >>> >>>>>>> >>> >>>>>>> Jean-Samuel. >>> >>>>>>> :-) >>> >>>>>>> >>> >>>>>>> >>> >>>>>>> On Wed, Jul 4, 2012 at 2:02 PM, Andrey Sviyazov >>> >>>>>>> wrote: >>> >>>>>>>> >>> >>>>>>>> Hi Jean-Samuel. >>> >>>>>>>> >>> >>>>>>>> For the TI160808U601 and TI201209U121 you can use any high >>> current >>> >>>>>>>> ferrite chip bead with 600 Ohm and 120 Ohm impedance >>> respectively. >>> >>>>>>>> For example you could order similar partnumbers from the ELFA >>> >>>>>>>> catalogue in the 0603 and 0805 SMD cases respectively, >>> datasheet here pdf. >>> >>>>>>>> >>> >>>>>>>> Best regards, >>> >>>>>>>> Andrey Sviyazov. >>> >>>>>>>> >>> >>>>>>>> >>> >>>>>>>> >>> >>>>>>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>> >>>>>>>> >>> >>>>>>>>> >>> >>>>>>>>> Hi Andrey, >>> >>>>>>>>> >>> >>>>>>>>> Thank you very much for your reply. >>> >>>>>>>>> >>> >>>>>>>>> I try to find where to buy the TI160808U601 and TI201209-121 >>> >>>>>>>>> chokes. I do not know where I should find these. Would you >>> know where I >>> >>>>>>>>> should order these components ? >>> >>>>>>>>> >>> >>>>>>>>> By the way, do you confirm the ISSI SRAM is pin compatible >>> with the >>> >>>>>>>>> Cypress chip ? >>> >>>>>>>>> >>> >>>>>>>>> >>> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >>> >>>>>>>>> >>> >>>>>>>>> Is this ISSI chip fine for our application ? Is 18 MBit enough >>> ? >>> >>>>>>>>> Do you confirm this ISSI chip is the best value for what we >>> need ? >>> >>>>>>>>> Are you sure we cannot find a lower cost chip with similar >>> performances >>> >>>>>>>>> and/or a better performances chip with similar cost ? >>> >>>>>>>>> Are you sure we will not need to reroute the PCB ? >>> >>>>>>>>> >>> >>>>>>>>> We really need to be sure before starting the PCB production. >>> If >>> >>>>>>>>> both you and Alexander confirm everything is fine, I will ask >>> the fab to >>> >>>>>>>>> start the PCB. >>> >>>>>>>>> >>> >>>>>>>>> Please let me know. >>> >>>>>>>>> >>> >>>>>>>>> Again, thanks a lot for your help. >>> >>>>>>>>> >>> >>>>>>>>> Best regards. >>> >>>>>>>>> >>> >>>>>>>>> Jean-Samuel. >>> >>>>>>>>> :-) >>> >>>>>>>>> >>> >>>>>>>>> >>> >>>>>>>>> >>> >>>>>>>>> On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov >>> >>>>>>>>> wrote: >>> >>>>>>>>>> >>> >>>>>>>>>> Jean-Samuel. >>> >>>>>>>>>> >>> >>>>>>>>>> Please inform me what actually rf chockes partnumbers are >>> problem >>> >>>>>>>>>> to order. >>> >>>>>>>>>> Unfortunately MuRata produce few billion pcs and then stopped >>> for >>> >>>>>>>>>> a few years. >>> >>>>>>>>>> So, possible we have to find some Chinese fab partnumbers to >>> >>>>>>>>>> order. >>> >>>>>>>>>> >>> >>>>>>>>>> Best regards, >>> >>>>>>>>>> Andrey Sviyazov. >>> >>>>>>>>>> (Sent from my mobile client) >>> >>>>>>>>>> >>> >>>>>>>>>> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" >>> >>>>>>>>>> ???????: >>> >>>>>>>>>> >>> >>>>>>>>>>> Hi Jean-Samuel. >>> >>>>>>>>>>> Unfortunately I have no internet connection now. >>> >>>>>>>>>>> Tomorrow I'll check flash and others. >>> >>>>>>>>>>> >>> >>>>>>>>>>> Best regards, >>> >>>>>>>>>>> Andrey Sviyazov. >>> >>>>>>>>>>> (Sent from my mobile client) >>> >>>>>>>>>>> >>> >>>>>>>>>>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" >>> >>>>>>>>>>> ???????: >>> >>>>>>>>>>> > >>> >>>>>>>>>>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - BJT >>> >>>>>>>>>>> > PARTNERS >>> >>>>>>>>>>> > SARL wrote: >>> >>>>>>>>>>> > > 1/ Would you know a distributor for the Murata chokes ? >>> The >>> >>>>>>>>>>> > > fab them to have >>> >>>>>>>>>>> > > some issue to source these. >>> >>>>>>>>>>> > >>> >>>>>>>>>>> > Andrey is looking into this. >>> >>>>>>>>>>> > >>> >>>>>>>>>>> > > 2/ Would you suggest a distributor for the GPS chip ? >>> >>>>>>>>>>> > >>> >>>>>>>>>>> > Try contacting manufacturer directly: >>> >>>>>>>>>>> > >>> >>>>>>>>>>> > >>> http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >>> >>>>>>>>>>> > >>> >>>>>>>>>>> > They have a distributor in UK, but I think it might be >>> easier >>> >>>>>>>>>>> > to buy >>> >>>>>>>>>>> > from the manufacturer directly: >>> >>>>>>>>>>> > http://www.castlemicrowave.com/castle-contact.asp >>> >>>>>>>>>>> > >>> >>>>>>>>>>> > This chip is popular in Russia, so it is easy to source >>> them >>> >>>>>>>>>>> > here, >>> >>>>>>>>>>> > shipping them to EU might be a pain in big batches, but I >>> think >>> >>>>>>>>>>> > we >>> >>>>>>>>>>> > could send few chips for this prototyping batch if >>> >>>>>>>>>>> > manufacturer's lead >>> >>>>>>>>>>> > time is too long. Here it costs $14.50/chip for more then >>> 16 >>> >>>>>>>>>>> > chips: >>> >>>>>>>>>>> > http://www.compel.ru/infosheet/TSI/EB-570/ >>> >>>>>>>>>>> > >>> >>>>>>>>>>> > -- >>> >>>>>>>>>>> > Regards, >>> >>>>>>>>>>> > Alexander Chemeris. >>> >>>>>>>>>>> > CEO, Fairwaves LLC / ??? ??????? >>> >>>>>>>>>>> > http://fairwaves.ru >>> >>>>>>>>> >>> >>>>>>>>> >>> >>>>>>>> >>> >>>>>>> >>> >>>>>> >>> >>>>> >>> >>>> >>> >>> >>> > >>> >>> >>> >>> -- >>> Regards, >>> Alexander Chemeris. >>> CEO, Fairwaves LLC / ??? ??????? >>> http://fairwaves.ru >>> >> >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: UmTRXv2_prj_sch (30.07.2012 16-18-30).zi_ Type: application/octet-stream Size: 767402 bytes Desc: not available URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: UmTRXv2_pcb (30.07.2012 16-19-07).zi_ Type: application/octet-stream Size: 5006460 bytes Desc: not available URL: From alexander.chemeris at gmail.com Mon Jul 30 12:31:17 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Mon, 30 Jul 2012 16:31:17 +0400 Subject: UmTRXv2 final project In-Reply-To: References: Message-ID: Andrey, thanks. Please send me UmTRXv2_sch_all.pdf as well On Mon, Jul 30, 2012 at 4:22 PM, Andrey Sviyazov wrote: > Here project, sch and pcb files. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/30 Andrey Sviyazov >> >> Hi Jean-Samuel. >> >> Here are attached last versions of interactive PDF for assembly and >> schema, and BOM (rename zi_ to zip first). >> List of components which are changed: >> L6-1, L6-2 = R0603 0 Ohm instead of choke >> C45-1, C45-2 = Do Not Install >> C82-1, C82-2, C98-1, C98-2 = 100pF instead of 470pF >> C83-1, C83-2, C99-1, C99-2 = 1500pF instead of 8.2nF >> C84-1, C84-2, C97-1, C97-2 = 33pF instead of 150pF >> R106-1, R106-2, R121-1, R121-2 = 2k2 instead of 820 Ohm >> R109-1, R109-2, R119-1, R119-2 = 3k3 instead of 1.2 kOhm >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/25 Andrey Sviyazov >>> >>> Hi Jean-Samuel. >>> >>> First of all you're right, we can't delay production. >>> So, I am sure it is better if PCB production will continue as you >>> suggest. >>> >>> There are only three hardware issues which have to be solved before >>> assembling: >>> 1) Improving LMS phase noise. >>> It is almost done and Alexander wrote you which component need to order. >>> >>> 2) Digital noise which born in GPS module 230. >>> In ver.2 we will use GPS module 570, but I am afraid that we can get the >>> same problems. >>> So, I need 1-2 days to workaround this issue. >>> And also we have to understand either it important or it doesn't because >>> this noises hided under modulation. >>> >>> 3) LMS engineers suggested us to use PLL loop filter 100kHz instead >>> 50kHz. >>> In case of 100kHz we have to decrease charge-pump current from 1.2-1.9mA >>> down to 0.4mA, but I am afraid about integral phase noise of LO because >>> (possible) it can affect modulation phase error (in degrees). >>> I think, required 1-2 days (the same days) to understand this also. >>> >>> So, at Thirsday I will send you final BOM and assembly files. >>> Hope it doesn't delay production, otherwise tell me and we'll hurry up. >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/24 Alexander Chemeris >>>> >>>> Hi Jean-Samuel, >>>> >>>> We're sitting together with Andrey Sviyazov now and he says that it's >>>> fine to continue with this PCB. >>>> >>>> You will need 40pcs of this 0 Ohm jumpers (2pcs per board): >>>> >>>> http://fr.farnell.com/bourns/cr0603-j-000elf/resistor-0603-0r-5-0-1w/dp/2008343 >>>> >>>> Andrey will update the schematics and BoM later today. >>>> >>>> On Tue, Jul 24, 2012 at 2:13 PM, Jean-Samuel Najnudel - BJT PARTNERS >>>> SARL wrote: >>>> > Hi Andrey, >>>> > >>>> > PCB copper is ready yet. We will lose 560 Euros and 3 weeks delay if >>>> > we >>>> > change the copper. It is not impossible, we can decide to do that but >>>> > I >>>> > would suggest we change the PCB for the next batch. After testing the >>>> > v2 >>>> > board, you may found more changes we need on the copper. >>>> > >>>> > The board itself is not ready. We can change some passives. This will >>>> > not >>>> > cost anything (or almost) and extra delay will be just one or two days >>>> > at >>>> > most. >>>> > >>>> > Please let me know what you want to do about the PCB. >>>> > >>>> > Please let me know the exact passives modifications. I will purchase >>>> > the >>>> > components asap and send the modifications list to the fab. >>>> > >>>> > Best regards. >>>> > >>>> > Jean-Samuel. >>>> > :-) >>>> > >>>> > Le 23 juil. 2012 22:47, "Andrey Sviyazov" a >>>> > ?crit : >>>> > >>>> >> Hi Jean-Samuel. >>>> >> >>>> >> Please let me know fabrication progress, a specially PCB. >>>> >> I ask you because of few changes required to improve LMS phase >>>> >> noises. >>>> >> BOM required changes in passive components only. >>>> >> If PCB doesn't yet ordered, then possible I'll make changes too. >>>> >> >>>> >> Best regards, >>>> >> Andrey Sviyazov. >>>> >> (Sent from my mobile client) >>>> >> >>>> >> 04.07.2012 20:01 ???????????? "Jean-Samuel Najnudel - BJT PARTNERS >>>> >> SARL" >>>> >> ???????: >>>> >>> >>>> >>> Hi Andrey, >>>> >>> >>>> >>> Thank you very much for your help. >>>> >>> >>>> >>> I will forward this to the fab. >>>> >>> Yes, you are all right, the FBMH2012HM121-T price is much better >>>> >>> than the >>>> >>> MLB-201209-0120PU. However, availability on Farnell France is not as >>>> >>> good as >>>> >>> the MLB-201209-0120PU. Price difference is quite big but we only use >>>> >>> 5 beads >>>> >>> per boards. Difference makes only about 1 euro per board. I will let >>>> >>> the fab >>>> >>> decide between these 2 references. >>>> >>> >>>> >>> Best regards. >>>> >>> >>>> >>> Jean-Samuel. >>>> >>> :-) >>>> >>> >>>> >>> >>>> >>> On Wed, Jul 4, 2012 at 4:30 PM, Andrey Sviyazov >>>> >>> >>>> >>> wrote: >>>> >>>> >>>> >>>> Hi Jean-Samuel. >>>> >>>> >>>> >>>> Yes, you are all right and you can order TDK - MPZ1608S601A instead >>>> >>>> of >>>> >>>> MLB-160808-0600PL. >>>> >>>> And also possible to use 3 times cheaper FBMH2012HM121-T, 0805, >>>> >>>> 2.5A >>>> >>>> instead of MLB-201209-0120PU. >>>> >>>> >>>> >>>> Best regards, >>>> >>>> Andrey Sviyazov. >>>> >>>> >>>> >>>> >>>> >>>> >>>> >>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>>> >>>> >>>> >>>>> >>>> >>>>> Hi Andrey, >>>> >>>>> >>>> >>>>> Thank you very much for your reply. >>>> >>>>> Now, I better understand. >>>> >>>>> >>>> >>>>> You are all right. I do not have anything as high current as >>>> >>>>> MLB-201209-0120PU at a lower price. >>>> >>>>> >>>> >>>>> However, I have a 0603 600 ohm 1A bead, as MLB-160808-0600PL, at a >>>> >>>>> much >>>> >>>>> lower price. >>>> >>>>> >>>> >>>>> >>>> >>>>> http://ru.farnell.com/tdk/mpz1608s601a/ferrite-bead-0603-600-ohm/dp/1669747RL >>>> >>>>> What do you think about this component (TDK MPZ1608S601A)? >>>> >>>>> >>>> >>>>> Best regards. >>>> >>>>> >>>> >>>>> Jean-Samuel. >>>> >>>>> :-) >>>> >>>>> >>>> >>>>> >>>> >>>>> >>>> >>>>> On Wed, Jul 4, 2012 at 3:22 PM, Andrey Sviyazov >>>> >>>>> wrote: >>>> >>>>>> >>>> >>>>>> Hi Jean-Samuel. >>>> >>>>>> >>>> >>>>>> If Farnell better for you, then please order exactly >>>> >>>>>> MLB-201209-0120PU >>>> >>>>>> and MLB-160808-0600PL. >>>> >>>>>> They are HI_CURRENT beads and it is really required. >>>> >>>>>> >>>> >>>>>> Please find attached here new SCH and BOM files with new part >>>> >>>>>> numbers >>>> >>>>>> and links. >>>> >>>>>> >>>> >>>>>> Best regards, >>>> >>>>>> Andrey Sviyazov. >>>> >>>>>> >>>> >>>>>> >>>> >>>>>> >>>> >>>>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>>> >>>>>> >>>> >>>>>>> >>>> >>>>>>> Hi Andrey, >>>> >>>>>>> >>>> >>>>>>> Thank you very much for your reply. >>>> >>>>>>> >>>> >>>>>>> Could you please confirm the components bellow are fine ? >>>> >>>>>>> >>>> >>>>>>> >>>> >>>>>>> http://fr.farnell.com/murata/blm18tg601tn1d/ferrite-600ohm/dp/1115050RL >>>> >>>>>>> >>>> >>>>>>> >>>> >>>>>>> http://fr.farnell.com/tdk/mmz2012121b/perle-de-ferrite-0805-120-ohm/dp/1669728RL >>>> >>>>>>> >>>> >>>>>>> Please let me know if this is fine. >>>> >>>>>>> If not, which would you suggest ? >>>> >>>>>>> http://ru.farnell.com/ferrite-beads >>>> >>>>>>> >>>> >>>>>>> >>>> >>>>>>> Thanks a lot for your help. >>>> >>>>>>> >>>> >>>>>>> Best regards. >>>> >>>>>>> >>>> >>>>>>> Jean-Samuel. >>>> >>>>>>> :-) >>>> >>>>>>> >>>> >>>>>>> >>>> >>>>>>> On Wed, Jul 4, 2012 at 2:02 PM, Andrey Sviyazov >>>> >>>>>>> wrote: >>>> >>>>>>>> >>>> >>>>>>>> Hi Jean-Samuel. >>>> >>>>>>>> >>>> >>>>>>>> For the TI160808U601 and TI201209U121 you can use any high >>>> >>>>>>>> current >>>> >>>>>>>> ferrite chip bead with 600 Ohm and 120 Ohm impedance >>>> >>>>>>>> respectively. >>>> >>>>>>>> For example you could order similar partnumbers from the ELFA >>>> >>>>>>>> catalogue in the 0603 and 0805 SMD cases respectively, >>>> >>>>>>>> datasheet here pdf. >>>> >>>>>>>> >>>> >>>>>>>> Best regards, >>>> >>>>>>>> Andrey Sviyazov. >>>> >>>>>>>> >>>> >>>>>>>> >>>> >>>>>>>> >>>> >>>>>>>> 2012/7/4 Jean-Samuel Najnudel - BJT PARTNERS SARL >>>> >>>>>>>> >>>> >>>>>>>>> >>>> >>>>>>>>> Hi Andrey, >>>> >>>>>>>>> >>>> >>>>>>>>> Thank you very much for your reply. >>>> >>>>>>>>> >>>> >>>>>>>>> I try to find where to buy the TI160808U601 and TI201209-121 >>>> >>>>>>>>> chokes. I do not know where I should find these. Would you >>>> >>>>>>>>> know where I >>>> >>>>>>>>> should order these components ? >>>> >>>>>>>>> >>>> >>>>>>>>> By the way, do you confirm the ISSI SRAM is pin compatible >>>> >>>>>>>>> with the >>>> >>>>>>>>> Cypress chip ? >>>> >>>>>>>>> >>>> >>>>>>>>> >>>> >>>>>>>>> http://www.digikey.com/product-detail/en/IS61NLP51236-200TQLI/706-1103-ND/1557418 >>>> >>>>>>>>> >>>> >>>>>>>>> Is this ISSI chip fine for our application ? Is 18 MBit enough >>>> >>>>>>>>> ? >>>> >>>>>>>>> Do you confirm this ISSI chip is the best value for what we >>>> >>>>>>>>> need ? >>>> >>>>>>>>> Are you sure we cannot find a lower cost chip with similar >>>> >>>>>>>>> performances >>>> >>>>>>>>> and/or a better performances chip with similar cost ? >>>> >>>>>>>>> Are you sure we will not need to reroute the PCB ? >>>> >>>>>>>>> >>>> >>>>>>>>> We really need to be sure before starting the PCB production. >>>> >>>>>>>>> If >>>> >>>>>>>>> both you and Alexander confirm everything is fine, I will ask >>>> >>>>>>>>> the fab to >>>> >>>>>>>>> start the PCB. >>>> >>>>>>>>> >>>> >>>>>>>>> Please let me know. >>>> >>>>>>>>> >>>> >>>>>>>>> Again, thanks a lot for your help. >>>> >>>>>>>>> >>>> >>>>>>>>> Best regards. >>>> >>>>>>>>> >>>> >>>>>>>>> Jean-Samuel. >>>> >>>>>>>>> :-) >>>> >>>>>>>>> >>>> >>>>>>>>> >>>> >>>>>>>>> >>>> >>>>>>>>> On Tue, Jul 3, 2012 at 11:40 PM, Andrey Sviyazov >>>> >>>>>>>>> wrote: >>>> >>>>>>>>>> >>>> >>>>>>>>>> Jean-Samuel. >>>> >>>>>>>>>> >>>> >>>>>>>>>> Please inform me what actually rf chockes partnumbers are >>>> >>>>>>>>>> problem >>>> >>>>>>>>>> to order. >>>> >>>>>>>>>> Unfortunately MuRata produce few billion pcs and then stopped >>>> >>>>>>>>>> for >>>> >>>>>>>>>> a few years. >>>> >>>>>>>>>> So, possible we have to find some Chinese fab partnumbers to >>>> >>>>>>>>>> order. >>>> >>>>>>>>>> >>>> >>>>>>>>>> Best regards, >>>> >>>>>>>>>> Andrey Sviyazov. >>>> >>>>>>>>>> (Sent from my mobile client) >>>> >>>>>>>>>> >>>> >>>>>>>>>> 04.07.2012 1:22 ???????????? "Andrey Sviyazov" >>>> >>>>>>>>>> ???????: >>>> >>>>>>>>>> >>>> >>>>>>>>>>> Hi Jean-Samuel. >>>> >>>>>>>>>>> Unfortunately I have no internet connection now. >>>> >>>>>>>>>>> Tomorrow I'll check flash and others. >>>> >>>>>>>>>>> >>>> >>>>>>>>>>> Best regards, >>>> >>>>>>>>>>> Andrey Sviyazov. >>>> >>>>>>>>>>> (Sent from my mobile client) >>>> >>>>>>>>>>> >>>> >>>>>>>>>>> 04.07.2012 1:10 ???????????? "Alexander Chemeris" >>>> >>>>>>>>>>> ???????: >>>> >>>>>>>>>>> > >>>> >>>>>>>>>>> > On Mon, Jul 2, 2012 at 10:16 PM, Jean-Samuel Najnudel - >>>> >>>>>>>>>>> > BJT >>>> >>>>>>>>>>> > PARTNERS >>>> >>>>>>>>>>> > SARL wrote: >>>> >>>>>>>>>>> > > 1/ Would you know a distributor for the Murata chokes ? >>>> >>>>>>>>>>> > > The >>>> >>>>>>>>>>> > > fab them to have >>>> >>>>>>>>>>> > > some issue to source these. >>>> >>>>>>>>>>> > >>>> >>>>>>>>>>> > Andrey is looking into this. >>>> >>>>>>>>>>> > >>>> >>>>>>>>>>> > > 2/ Would you suggest a distributor for the GPS chip ? >>>> >>>>>>>>>>> > >>>> >>>>>>>>>>> > Try contacting manufacturer directly: >>>> >>>>>>>>>>> > >>>> >>>>>>>>>>> > >>>> >>>>>>>>>>> > http://www.transystem.com.tw/product.php?b=g&m=pe&cid=4&sid=&id=66 >>>> >>>>>>>>>>> > >>>> >>>>>>>>>>> > They have a distributor in UK, but I think it might be >>>> >>>>>>>>>>> > easier >>>> >>>>>>>>>>> > to buy >>>> >>>>>>>>>>> > from the manufacturer directly: >>>> >>>>>>>>>>> > http://www.castlemicrowave.com/castle-contact.asp >>>> >>>>>>>>>>> > >>>> >>>>>>>>>>> > This chip is popular in Russia, so it is easy to source >>>> >>>>>>>>>>> > them >>>> >>>>>>>>>>> > here, >>>> >>>>>>>>>>> > shipping them to EU might be a pain in big batches, but I >>>> >>>>>>>>>>> > think >>>> >>>>>>>>>>> > we >>>> >>>>>>>>>>> > could send few chips for this prototyping batch if >>>> >>>>>>>>>>> > manufacturer's lead >>>> >>>>>>>>>>> > time is too long. Here it costs $14.50/chip for more then >>>> >>>>>>>>>>> > 16 >>>> >>>>>>>>>>> > chips: >>>> >>>>>>>>>>> > http://www.compel.ru/infosheet/TSI/EB-570/ >>>> >>>>>>>>>>> > >>>> >>>>>>>>>>> > -- >>>> >>>>>>>>>>> > Regards, >>>> >>>>>>>>>>> > Alexander Chemeris. >>>> >>>>>>>>>>> > CEO, Fairwaves LLC / ??? ??????? >>>> >>>>>>>>>>> > http://fairwaves.ru >>>> >>>>>>>>> >>>> >>>>>>>>> >>>> >>>>>>>> >>>> >>>>>>> >>>> >>>>>> >>>> >>>>> >>>> >>>> >>>> >>> >>>> > >>>> >>>> >>>> >>>> -- >>>> Regards, >>>> Alexander Chemeris. >>>> CEO, Fairwaves LLC / ??? ??????? >>>> http://fairwaves.ru >>> >>> >> > -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Mon Jul 30 13:54:48 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Mon, 30 Jul 2012 17:54:48 +0400 Subject: LMS TxLO noise In-Reply-To: References: Message-ID: Hi all, Schematics are updated: https://github.com/chemeris/umtrx-schematics/commit/e4f71edbe96d4673ce87e6db982c0346a9b6e412 Huge thanks to everyone for digging into the issue! On Mon, Jul 30, 2012 at 12:07 PM, Andrey Sviyazov wrote: > Hi Thomas. > > Thank you very much for good news. > Sylvain and everybody who discussed, thanks a lot. > Seems, now I could finalize new revison of the BOM. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/30 Thomas Tsou >> >> Hi Andrey, >> >> Parts arrived yesterday and I made modifications for the 100 kHz loop >> filter and tested today. The entire 900 band is below 1.5 / 5 with a >> good margin. >> >> http://filebox.vt.edu/users/ttsou/http/umtrx_945mhz_4.bmp >> >> The lower part of the 1800 is also below the target value. I was not >> successful at 1885 MHz, though further calibration is possible (manual >> calibration at each frequency takes a very long time). I will perform >> additional tests tomorrow. >> >> http://filebox.vt.edu/users/ttsou/http/umtrx_1825mhz_4.bmp >> http://filebox.vt.edu/users/ttsou/http/umtrx_1825mhz_noise.PNG >> >> Thomas >> >> On Wed, Jul 25, 2012 at 9:52 PM, Thomas Tsou wrote: >> > On Wed, Jul 25, 2012 at 1:41 PM, Andrey Sviyazov >> > wrote: >> >> Hi Thomas. >> >> >> >> Digikey part numbers links: >> >> C82 = 100pF, C83=1500pF, C84=33pF, R106=2.2k, R109=3.3k, L6=0.022uF. >> >> >> >> But you'll remove 100pF capasitor from position C45, so you could use >> >> it for >> >> C82. >> >> BTW, how long time required to delivering from the DigiKey? >> > >> > Thank you for the links. Parts are ordered. Digikey orders usually >> > arrives in 2 days. >> > >> > Thomas > > -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Mon Jul 30 20:40:14 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Tue, 31 Jul 2012 00:40:14 +0400 Subject: UmTRX in action picture Message-ID: We need a picture of UmTRX in action for the Open Hardware Summit web-site. Andrey Sviyazov - could you bring your UmTRX (the one with an enclosure) to the hackerspace to make a picture of it with antennas? -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From alexander.chemeris at gmail.com Tue Jul 31 15:12:34 2012 From: alexander.chemeris at gmail.com (Alexander Chemeris) Date: Tue, 31 Jul 2012 19:12:34 +0400 Subject: Pletronics OHM4 Message-ID: Hi, I've received 10pcs of OHM4048052GG010020-26.0M today. Andrey Sviyazov - could you measure their performance and test UmTRX with them? -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ??? ??????? http://fairwaves.ru From andreysviyaz at gmail.com Tue Jul 31 16:35:05 2012 From: andreysviyaz at gmail.com (Andrey Sviyazov) Date: Tue, 31 Jul 2012 20:35:05 +0400 Subject: Pletronics OHM4 In-Reply-To: References: Message-ID: That's good news! Yes, of course, I have to test it and then share some results. Best regards, Andrey Sviyazov. 2012/7/31 Alexander Chemeris > Hi, > > I've received 10pcs of OHM4048052GG010020-26.0M today. Andrey Sviyazov > - could you measure their performance and test UmTRX with them? > > -- > Regards, > Alexander Chemeris. > CEO, Fairwaves LLC / ??? ??????? > http://fairwaves.ru > > -------------- next part -------------- An HTML attachment was scrubbed... URL: