Hi,<br><br><div class="gmail_quote">On Tue, Jul 10, 2012 at 12:26 PM, Harald Welte <span dir="ltr"><<a href="mailto:laforge@gnumonks.org" target="_blank">laforge@gnumonks.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hi Christian,<br>
<div><br>
On Tue, Jul 10, 2012 at 07:04:35PM +0200, Christian Daniel -- maintech GmbH wrote:<br>
> We violate the 100mA limit by a small amount. FPGA and E4K can be<br>
> switched off and the ADC doesn't consume much when no clock is<br>
> applied. I don't see a problem here - at least after we fixed the<br>
> power sequence to stop it from using the full 400mA directly on power<br>
> up. Also a diode for external power supply is on the board. But yes -<br>
> it will not be USB certified. But so far this is not a real-world problem.<br>
<br>
</div>Actually, now that you're doing a re-design for the SSC -> EBI change,<br>
it might be an idea to make the oscillator power supply switchable and<br>
controlled by a GPIO from the SAM3U or FPGA. At that point, there's no<br>
problem booting at < 100mA.<br><br></blockquote><div><br></div><div>The Si570 has an OE pin, but even in tri-state mode it still consumes ~60mA. So, I second Harald: it makes sense to have an option to make the oscillator power supply switchable and to keep the overall consumption (including the RF IC, ADC, FPGA, TCXO and MCU) below 100mA until higher currents are negotiated. Connect the switch input to a SAM3U I/O rather than one of the FPGA.</div>
<div><br></div><div>By the way, the FPGA seems to have only one clock input, 'CLKPO'. Is this the case?</div><div><br></div><div><span style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">> 2. The Lattice LatticeXP2 FPGA is available in the same package but</span><br style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">
<div style="color:rgb(80,0,80);font-size:13px;font-family:arial,sans-serif">> in larger size at almost identical price. Why did you pick the<br>> smallest available FPGA, the LFXP-5E ($16) instead of the LFXP-8E<br>
> ($20)?<br><br></div><span style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">Because it was on stock and is big enough for the task at hand.</span><div><br></div>
<div>It can never be too big for a prototype. :) The two models ought to be pin-compatible, so the upgrade might be worth it if the LFXP-8E is available.</div><div>
<br style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif"><br style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif"><span style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">> 5. My understanding is that you configure the FPGA using the JTAG</span><br style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">
<div style="color:rgb(80,0,80);font-size:13px;font-family:arial,sans-serif">> lines in bit-bang mode through SAM3U GPIOs. Why don't you use the<br>> sysConfig port of the Lattice FPGA? It's faster, easier to<br>
> implement with the SAM3U SPI peripheral (and it's also a feature I<br>> haven't seen with other FPGAs). See Lattice TN1141<br></div><span style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">> <</span><a href="http://www.latticesemi.com/documents/TN1141.pdf" style="color:rgb(17,85,204);font-size:13px;font-family:arial,sans-serif" target="_blank">http://www.latticesemi.com/documents/TN1141.pdf</a><span style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">>.</span><br style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">
<br style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif"><span style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">Good point. Well - the current method works well and is fast (about 30</span><br style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">
<span style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">seconds to flash via USB). No need to change it again... My guess is,</span><br style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">
<span style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">that it won't get much faster since the bottleneck is USB and flash</span><br style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">
<span style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">write time. Perhaps we'll have to change it when we switch to EBI to</span><br style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">
<span style="color:rgb(34,34,34);font-size:13px;font-family:arial,sans-serif">free some SAM3U pins.</span></div><div><br></div><div>The other advantage of using the sysConfig Port is that you can save the JTAG lines for a pin header. If the pin header is compatible with the Lattice programmer, you might be able to use the Lattice's ChipScope equivalent for debugging the FPGA.</div>
<div><br></div><div>Cheers,</div><div><br></div><div>Sandor</div><div><br></div></div></div>