RFC: osmo-clk-gen v2

[Harald Welte]

Hi!

due to work overloead I've asked Martin to take over doing the various
design changes of osmo-clock-gen towards v2.  As the work progresses, we
have some questions about your preference.

The major changes performed so far in the design:

1) switch from SAMD11 to SAMD21 processor (more flash/ram)
   https://osmocom.org/issues/3856

We also used the opportunity of having more UARTs available to use a
different UART on the UEXT than on the 2.5mm console port.

There are no questions here.


2) allow different output voltages for two of the four banks of the Silabs chip
   https://osmocom.org/issues/3905

* have jumpers in-line of two of the four output banks of the PLL chipc
* jumper closed: reference is drawn from one (shared) "other voltage" LDO onboard
* jumper open: reference voltage can be provided/injected by user from external reference

What's still open to discuss is whether or not the LDO will be fixed
(you have to change resistors to change the voltage) or adjustable.  In
the latter case, we'd apply the DAC output of the SAMD21 as an input to
the tracking input of the LDO.  However, this would mean that we'd no
longer have the DAC output for driving a VCTCXO.

Which brings us to

3) should we keep the VCTCXO?

I really only placed it in v1 as PCB space was available.  Note that
while v1 can drive the VCTCXO Control voltrage from the microcontroller,
there is no circuitry on board to acually measure/compare/count the
output frequency and hence it's not possible to really have a control
*loop* as the feedback is missing.  That makes it rather useless.

So for the v2, we can either

a) remove the VCTCXO altogether and use the DAC output for
   software-modifiable output voltage levels of [some of] the clocks, or

b) try to come up with a way to actually count the clock cycles and
   compare it against some reference.  I'm not sure the SAMD21 could do
   a very good job of that, as I'm assuming that all inputs are sampled
   to some internal clock and hence experience jitter.

I personally would go for 'a', as to me this board/module was always only
about the PLL, and not about providing a stable reference itself.  I'd
much rather have a separate board/module with a GPS-DO, which then
provides a 10MHz reference into any number of osmo-clk-gen boards to
derive any number of other clocks.  Sort of like the good old unix
philosophy of doing only one thing in one program and chaining them
together.

Any thoughts?

There's also still to be done:

4) Use SAMD XOSC / PLL / GCLK to allow lower reference frequencies
   https://osmocom.org/issues/3857
   Where we'd actually use one of the SAMD GCLK outputs as one of the
   intputs to the Si5351C, and expose a GCLK input of the SAMD on an
   external header.  This way, much lower frequencies can be used to
   driver the Si5351C.  Or one could even go for deriving them from the
   SAMD RTC XTAL.

Regards,
	Harald

-- 
- Harald Welte <laforge at gnumonks.org>           http://laforge.gnumonks.org/
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