From daniel74f at gmail.com Fri May 3 13:38:00 2019 From: daniel74f at gmail.com (Daniel Correa) Date: Fri, 3 May 2019 10:38:00 -0300 Subject: fl2k output voltage level changes every few seconds Message-ID: Hi. When running the command line fl2k_fm -c 5000 /dev/zero to generate a continuous wave, the output voltage of the fl2k dongle regularly switches between two different amplitude levels (peak to peak voltage) every 2 or 3 seconds, by about %30 to %70 depending on the load. There's no visible gradual transition, it just switches instantly. The output peak-to-peak voltage is about 350 milivolts with no load. I've calculated the output impedance to be about 750 ohm at that frequency for the larger output level. I'm using the HDMI version of the dongle with the wire soldered after a capacitor (or resistor maybe) which was already there, to the red VGA pixel output of the chip. Could the issue be because some signal conditioning circuitry is missing that is present in the actual VGA version of the dongle, or that the pin is actually pulled to ground in this dongle as it is unused, and the chip doesn't like it and for some reason it then decides to regularly switch voltages? Any other ideas? From makrisj at gmail.com Wed May 8 12:12:09 2019 From: makrisj at gmail.com (Ioannis Makris) Date: Wed, 8 May 2019 15:12:09 +0300 Subject: fl2k output voltage level changes every few seconds Message-ID: While this is truly unexpected behaviour, please understand that the device was designed for a termination load of 75+j0 ohms (that's what all video/VGA analog signals require to be present at the load side) so any other load impedance value is untested at factory. I have independently tested that shorting the output to the ground causes an instant halt to the output of the plain VGA dongle, so there might be some protection circuit. Also, the VGA circuit has 150 ohms termination loads. -------------- next part -------------- An HTML attachment was scrubbed... URL: From laforge at gnumonks.org Sun May 19 19:29:44 2019 From: laforge at gnumonks.org (Harald Welte) Date: Sun, 19 May 2019 21:29:44 +0200 Subject: RFC: osmo-clk-gen v2 Message-ID: <20190519192944.GB8961@nataraja> Hi! due to work overloead I've asked Martin to take over doing the various design changes of osmo-clock-gen towards v2. As the work progresses, we have some questions about your preference. The major changes performed so far in the design: 1) switch from SAMD11 to SAMD21 processor (more flash/ram) https://osmocom.org/issues/3856 We also used the opportunity of having more UARTs available to use a different UART on the UEXT than on the 2.5mm console port. There are no questions here. 2) allow different output voltages for two of the four banks of the Silabs chip https://osmocom.org/issues/3905 * have jumpers in-line of two of the four output banks of the PLL chipc * jumper closed: reference is drawn from one (shared) "other voltage" LDO onboard * jumper open: reference voltage can be provided/injected by user from external reference What's still open to discuss is whether or not the LDO will be fixed (you have to change resistors to change the voltage) or adjustable. In the latter case, we'd apply the DAC output of the SAMD21 as an input to the tracking input of the LDO. However, this would mean that we'd no longer have the DAC output for driving a VCTCXO. Which brings us to 3) should we keep the VCTCXO? I really only placed it in v1 as PCB space was available. Note that while v1 can drive the VCTCXO Control voltrage from the microcontroller, there is no circuitry on board to acually measure/compare/count the output frequency and hence it's not possible to really have a control *loop* as the feedback is missing. That makes it rather useless. So for the v2, we can either a) remove the VCTCXO altogether and use the DAC output for software-modifiable output voltage levels of [some of] the clocks, or b) try to come up with a way to actually count the clock cycles and compare it against some reference. I'm not sure the SAMD21 could do a very good job of that, as I'm assuming that all inputs are sampled to some internal clock and hence experience jitter. I personally would go for 'a', as to me this board/module was always only about the PLL, and not about providing a stable reference itself. I'd much rather have a separate board/module with a GPS-DO, which then provides a 10MHz reference into any number of osmo-clk-gen boards to derive any number of other clocks. Sort of like the good old unix philosophy of doing only one thing in one program and chaining them together. Any thoughts? There's also still to be done: 4) Use SAMD XOSC / PLL / GCLK to allow lower reference frequencies https://osmocom.org/issues/3857 Where we'd actually use one of the SAMD GCLK outputs as one of the intputs to the Si5351C, and expose a GCLK input of the SAMD on an external header. This way, much lower frequencies can be used to driver the Si5351C. Or one could even go for deriving them from the SAMD RTC XTAL. Regards, Harald -- - Harald Welte http://laforge.gnumonks.org/ ============================================================================ "Privacy in residential applications is a desirable marketing option." (ETSI EN 300 175-7 Ch. A6) From 246tnt at gmail.com Mon May 20 15:13:42 2019 From: 246tnt at gmail.com (Sylvain Munaut) Date: Mon, 20 May 2019 17:13:42 +0200 Subject: RFC: osmo-clk-gen v2 In-Reply-To: <20190519192944.GB8961@nataraja> References: <20190519192944.GB8961@nataraja> Message-ID: > 2) allow different output voltages for two of the four banks of the Silabs chip > https://osmocom.org/issues/3905 I'd use the DAC for software voltage tuning. Use 0R to select which bank uses which (default rail or programmable one, with just default to have 1/2 bank being the programmable vio). > 3) should we keep the VCTCXO? No. As you explained I think it's better to split functions and not overload this board. > 4) Use SAMD XOSC / PLL / GCLK to allow lower reference frequencies > https://osmocom.org/issues/3857 > Where we'd actually use one of the SAMD GCLK outputs as one of the > intputs to the Si5351C, and expose a GCLK input of the SAMD on an > external header. This way, much lower frequencies can be used to > driver the Si5351C. Or one could even go for deriving them from the > SAMD RTC XTAL. Does that mean the SAMD core would be running from the reference clock ? (and so wouldn't run if there is no reference connected) Cheers, Sylvain From laforge at gnumonks.org Tue May 21 09:37:07 2019 From: laforge at gnumonks.org (Harald Welte) Date: Tue, 21 May 2019 11:37:07 +0200 Subject: RFC: osmo-clk-gen v2 In-Reply-To: References: <20190519192944.GB8961@nataraja> Message-ID: <20190521093706.GK30189@nataraja> Hi Sylvain, On Mon, May 20, 2019 at 05:13:42PM +0200, Sylvain Munaut wrote: > > 2) allow different output voltages for two of the four banks of the Silabs chip > > https://osmocom.org/issues/3905 > > I'd use the DAC for software voltage tuning. > Use 0R to select which bank uses which (default rail or programmable > one, with just default to have 1/2 bank being the programmable vio). Our solution so far was to have two banks fixed and two banks either fixed or variable by means of (mechanical, tht) jumpers. I'm not sure we can fit our of them, or if we can fit 0R SMD resistors at lest. @Martin? > > 3) should we keep the VCTCXO? > > No. As you explained I think it's better to split functions and not > overload this board. happy to see we're in agreement here. > > 4) Use SAMD XOSC / PLL / GCLK to allow lower reference frequencies > > https://osmocom.org/issues/3857 > > Where we'd actually use one of the SAMD GCLK outputs as one of the > > intputs to the Si5351C, and expose a GCLK input of the SAMD on an > > external header. This way, much lower frequencies can be used to > > driver the Si5351C. Or one could even go for deriving them from the > > SAMD RTC XTAL. > > Does that mean the SAMD core would be running from the reference clock > ? (and so wouldn't run if there is no reference connected) The SAMD can run from its internal oscillator, even while communicating over USB where it derives/recovers the USB clock from the SOF. So while one could run it from an external reference, it is not mandatory/required. -- - Harald Welte http://laforge.gnumonks.org/ ============================================================================ "Privacy in residential applications is a desirable marketing option." (ETSI EN 300 175-7 Ch. A6) From mueller at kit.edu Tue May 21 11:48:49 2019 From: mueller at kit.edu (=?utf-8?B?TcO8bGxlciwgTWFyY3VzIChDRUwp?=) Date: Tue, 21 May 2019 11:48:49 +0000 Subject: RFC: osmo-clk-gen v2 In-Reply-To: <20190521093706.GK30189@nataraja> References: <20190519192944.GB8961@nataraja> <20190521093706.GK30189@nataraja> Message-ID: <5442e3ceb6bc2bc48991bdedd2430afccf5ad1aa.camel@kit.edu> Hi Sylvain & Harald, On Tue, 2019-05-21 at 11:37 +0200, Harald Welte wrote: > Hi Sylvain, > > On Mon, May 20, 2019 at 05:13:42PM +0200, Sylvain Munaut wrote: > > > 2) allow different output voltages for two of the four banks of the Silabs chip > > > https://osmocom.org/issues/3905 > > > > I'd use the DAC for software voltage tuning. > > Use 0R to select which bank uses which (default rail or programmable > > one, with just default to have 1/2 bank being the programmable vio). > > Our solution so far was to have two banks fixed and two banks either > fixed or variable by means of (mechanical, tht) jumpers. I'm not sure > we can fit our of them, or if we can fit 0R SMD resistors at lest. @Martin? Knowing that 2.54 mm jumpers can be huge ? can't one just add a resistor in series with the DAC output and connect both that and the external Vref input to the tracking input of the regulator? (I didn't even know there was tracking regulators, that's awesome! I'd just have gone for an SC-70 opamp voltage follower; considering the 5.6 mA max bank I_DDOx current, that would suffice, I think?) That way, with no external voltage fed in to these jumpers, the DAC is "alone" and assuming no significant current into the tracking input, the resistor doesn't skew the voltage. With an external source connected, one could just set the DAC output to be a high-Z input. The resistor then just fulfills the role of avoiding high currents going between DAC and external voltage source if one forgets to float the output first or the external voltage is significantly higher than the MCU's VCC. (the question would be "how does the MCU know there's an external voltage reference connected", but if the tracking input's impedance is high enough, one could use a very weak resistor, so that a "competing" DAC wouldn't even affect the external reference, and it wouldn't have to know.) > > > 3) should we keep the VCTCXO? > > > > No. As you explained I think it's better to split functions and not > > overload this board. > > happy to see we're in agreement here. > > > > 4) Use SAMD XOSC / PLL / GCLK to allow lower reference frequencies > > > https://osmocom.org/issues/3857 > > > Where we'd actually use one of the SAMD GCLK outputs as one of the > > > intputs to the Si5351C, and expose a GCLK input of the SAMD on an > > > external header. This way, much lower frequencies can be used to > > > driver the Si5351C. Or one could even go for deriving them from the > > > SAMD RTC XTAL. > > > > Does that mean the SAMD core would be running from the reference clock > > ? (and so wouldn't run if there is no reference connected) > > The SAMD can run from its internal oscillator, even while communicating over > USB where it derives/recovers the USB clock from the SOF. So while one could > run it from an external reference, it is not mandatory/required. I think the XOSC input pads of the SAM D11/21 can also function as normal GPIOs, so one could comfortably use these to detect the presence of a roughly suitable clock signal, and only then configure one of the internal clock buses (don't know ? maybe even one used by nothing else) to source the clock from that, and enable the output of that internal clock to the respective GCLK to the GCLK_IO pin. Regards, Marcus -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/x-pkcs7-signature Size: 6582 bytes Desc: not available URL: From barbo at umn.edu Wed May 22 20:25:29 2019 From: barbo at umn.edu (Steven Barbo) Date: Wed, 22 May 2019 15:25:29 -0500 Subject: gr-osmosdr yml file for gnuradio/grc/blocks Message-ID: Hello. Managed to compile gr-osmosdr from git with gnuradio 3.8tech-preview-365-gd66bc948 (Python 3.7.3) Having some issue converting osmosdr-source and sink block files from xml verion to yml. Anyone done such they'd be willing to share? Thank you. -- If something is requisite, how can it possibly be, prerequisite? vanitas vanitatum omnia vanitas later, steve http://umn.edu/~barbo -------------- next part -------------- An HTML attachment was scrubbed... URL: From mschramm at sysmocom.de Thu May 23 17:27:44 2019 From: mschramm at sysmocom.de (Martin Schramm) Date: Thu, 23 May 2019 19:27:44 +0200 Subject: RFC: osmo-clk-gen v2 In-Reply-To: <5442e3ceb6bc2bc48991bdedd2430afccf5ad1aa.camel@kit.edu> References: <20190519192944.GB8961@nataraja> <20190521093706.GK30189@nataraja> <5442e3ceb6bc2bc48991bdedd2430afccf5ad1aa.camel@kit.edu> Message-ID: <6e6102fa-550f-b578-d593-625d12b2b922@sysmocom.de> Hi, >>> I'd use the DAC for software voltage tuning. >>> Use 0R to select which bank uses which (default rail or programmable >>> one, with just default to have 1/2 bank being the programmable vio). >> >> Our solution so far was to have two banks fixed and two banks either >> fixed or variable by means of (mechanical, tht) jumpers. I'm not sure >> we can fit our of them, or if we can fit 0R SMD resistors at lest. @Martin? Now it contains a 4x3 jumper block to switch the io supply of four banks (each forming two outputs) each between VDD fixed (3V3) and the adjustable supply. > considering the 5.6 mA max > bank I_DDOx current, that would suffice, I think?) 5.6mA is max I_DDOx, - but _per output_. So any adjustable source must supply over 40mA to the PLL out drivers. For the tracking LOD, I first selected the TLE4250. But lowest output voltage of this part is 2.5V, and as we want to have e.g. 1V8 as well, another part has to be found. I again took a buffer (voltage follower) formed of a generic R2R-IO, unity gain-stable CMOS opamp (MIC7300, TLV9001...). Those supply (or sink) 40 mA and more. But the max. output current depends on the output voltage, so, if we want to continue with that approach, I'd likely add a BJT current helper stage behind the opamp (BJT collector on 5V). We have almost no dynamic demands on that opamp, so disregarding any phase errors we introduce by driving large capacitive and resistive loads, it would work w/o a BJT, but let's see... laforge just mentioned he wants to have added a very weak pull-down between VOUT (DAC) and op amp input, to ground spikes during power-on and fw started/GPIOs initialized. The PULLEN bits are 0 after reset, so no PU should be set... external voltage reference and its input: > Knowing that 2.54 mm jumpers can be huge ? can't one just add a > resistor in series with the DAC output and connect both that and the > external Vref input to the tracking input of the regulator? [...] The DACVREFA (=ADCVREFA) pin has a limitation of AV_ref<= V_DDANA - 0.6V . As I'd want to have V_DDANA connected w/ a ferrite to V_DD (3V3), we can only use the internal reference 2, which is V_DDANA (SAMD21 ds: 37.11.5) So I don't see an external ref voltage input on that PCB... maybe your use case would explain your needs here! ;) VCTCXO: >>> 3) should we keep the VCTCXO? >>> >> No. As you explained I think it's better to split functions and not >> overload this board. >> >> happy to see we're in agreement here. ;) OK, thanks, part skipped and occupied area freed. I'll keep you updated about the ongoing progress. Martin -- From mueller at kit.edu Thu May 23 22:06:35 2019 From: mueller at kit.edu (=?utf-8?B?TcO8bGxlciwgTWFyY3VzIChDRUwp?=) Date: Thu, 23 May 2019 22:06:35 +0000 Subject: RFC: osmo-clk-gen v2 In-Reply-To: <6e6102fa-550f-b578-d593-625d12b2b922@sysmocom.de> References: <20190519192944.GB8961@nataraja> <20190521093706.GK30189@nataraja> <5442e3ceb6bc2bc48991bdedd2430afccf5ad1aa.camel@kit.edu> <6e6102fa-550f-b578-d593-625d12b2b922@sysmocom.de> Message-ID: On Thu, 2019-05-23 at 19:27 +0200, Martin Schramm wrote: > For the tracking LOD, I first selected the TLE4250. But lowest output > voltage of this part is 2.5V, and as we want to have e.g. 1V8 as well, > another part has to be found. yeah, that was my impression too once I searched ti.com for tracking LDOs: the ones available are either exceedingly large or don't go far enough down the voltage range. Hm, what about a buffered voltage follower (i.e. NPN BJT's base on the output of the opamp negative feedback and output on the emitter, VCC on the collector)? Should give plenty of current, with limited CE voltage drop but the ability to basically go to the negative rail with output voltage. > I again took a buffer (voltage follower) formed of a generic R2R-IO, > unity gain-stable CMOS opamp (MIC7300, TLV9001...). Those supply (or > sink) 40 mA and more. But the max. output current depends on the output > voltage, so, if we want to continue with that approach, I'd likely add a > BJT current helper stage behind the opamp (BJT collector on 5V). We have > almost no dynamic demands on that opamp, so disregarding any phase > errors we introduce by driving large capacitive and resistive loads, it > would work w/o a BJT, but let's see... ah nevermind, I think we're thinking of the same. > The DACVREFA (=ADCVREFA) pin has a limitation of AV_ref<= V_DDANA - 0.6V > . As I'd want to have V_DDANA connected w/ a ferrite to V_DD (3V3), we > can only use the internal reference 2, which is V_DDANA (SAMD21 ds: > 37.11.5) aaaah... > So I don't see an external ref voltage input on that PCB... maybe your > use case would explain your needs here! ;) Don't have a use case of my own here, sorry :) Maybe then using a GPIO pin PWM + FET + 2.54 mm jumper to VCC that doubles as external input would be easiest? Best regards, Marcus -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/x-pkcs7-signature Size: 6582 bytes Desc: not available URL: From daniel74f at gmail.com Fri May 24 09:15:44 2019 From: daniel74f at gmail.com (Daniel Correa) Date: Fri, 24 May 2019 06:15:44 -0300 Subject: fl2k output voltage level changes every few seconds In-Reply-To: References: Message-ID: >Also, the VGA circuit has 150 ohms termination loads. Do you mean that each of the resistors seen in the output in https://osmocom.org/attachments/download/3049/fl2k_pcb_top.jpg is 150 ohm, or both combined in parallel are 150 ohm? From 246tnt at gmail.com Fri May 24 10:39:33 2019 From: 246tnt at gmail.com (Sylvain Munaut) Date: Fri, 24 May 2019 12:39:33 +0200 Subject: RFC: osmo-clk-gen v2 In-Reply-To: <6e6102fa-550f-b578-d593-625d12b2b922@sysmocom.de> References: <20190519192944.GB8961@nataraja> <20190521093706.GK30189@nataraja> <5442e3ceb6bc2bc48991bdedd2430afccf5ad1aa.camel@kit.edu> <6e6102fa-550f-b578-d593-625d12b2b922@sysmocom.de> Message-ID: Hi > I again took a buffer (voltage follower) formed of a generic R2R-IO, > unity gain-stable CMOS opamp (MIC7300, TLV9001...). Those supply (or > sink) 40 mA and more. But the max. output current depends on the output > voltage, so, if we want to continue with that approach, I'd likely add a > BJT current helper stage behind the opamp (BJT collector on 5V). We have > almost no dynamic demands on that opamp, so disregarding any phase > errors we introduce by driving large capacitive and resistive loads, it > would work w/o a BJT, but let's see... Heh, I just prototyped something last weekend for another project with controlled VIO using a mcp6001 and a N-mos pass transistor. ( It sure doesn't have the lower drop-out configuration but I think it's more stable that way ). > So I don't see an external ref voltage input on that PCB... maybe your > use case would explain your needs here! ;) I don't see the need for a external vref input. VDDANA is fine. Cheers, Sylvain From makrisj at gmail.com Sat May 25 13:17:17 2019 From: makrisj at gmail.com (Ioannis Makris) Date: Sat, 25 May 2019 16:17:17 +0300 Subject: fl2k output voltage level changes every few seconds In-Reply-To: References: Message-ID: And another thing - the configuration demonstrated on the image you provided is an actual ? (pi) type low pass filter composed by R-L-R elements. There, the individual resistor is 150 ohm, in DC they are parallel, in RF they make a low pass filter along with the coil in btw. Some implementations do not use any coil but a 0-ohm shunt resistor instead. That means the resistors are parallel and they yield 75 ohms. Cheers On Sat, 25 May 2019 at 16:10, Ioannis Makris wrote: > I mean that each RGB analog output of the FL2k on the PCB has permanent > fixed terminations of 150 ohm. Still, I need to apologise for having to add > a correction: > > Some of the dongles having only analog output are being terminated @ 75 > ohms at the factory. > > Ref.1: http://www.marsport.org.uk/smd/mainframe.htm > Ref.2: See attached image > > This is normal. Those outputs are most probably open emitter outputs; > hence they need a termination in order to actually produce any current. > Leaving them floating in DC would most probably lead to unexpected and > unaccounted for results. > One could experiment by adding different values for termination or even a > 330 ohms trimmer in rheostat configuration,while maintaining at least an 75 > ohms resistor in series so as to give a range of 75-405 ohms of > termination. > What is to be monitored is the actual spectral behavior of the DAC rather > its maximum output, as there are unwanted spectral elements that could > register as power output on the wanted frequency in conventional needle > meters, when it actually that is far from truth. > Affecting terminations yields intermodulation in amplifiers and unwanted > spectral elements may occur due to several effects I can think of. > Always monitor spectral output if you want to transmit with this thing. > What I've seen is that if you just add 20dB of gain on its output without > applying heavy filtering beforehand you could easily end up to jail for > interfering aviation frequencies used at airports nearby. > -------------- next part -------------- An HTML attachment was scrubbed... URL: From daniel74f at gmail.com Mon May 27 14:52:15 2019 From: daniel74f at gmail.com (Daniel Correa) Date: Mon, 27 May 2019 11:52:15 -0300 Subject: fl2k output voltage level changes every few seconds In-Reply-To: References: Message-ID: Thanks for the info. Anyway, I figured out what the problem was, I hadn't disconnected a second chip which apparently turns the VGA signals coming from the FL2000 into HDMI. Removing a capacitor on the red pixel line between the two chips solved the issue. From pczzs at yahoo.com Fri May 31 16:59:31 2019 From: pczzs at yahoo.com (P C) Date: Fri, 31 May 2019 11:59:31 -0500 Subject: RTL_SDR "output_block_size (default 16*16384)" Message-ID: <2ff66056-843d-b403-6233-e375ee0228dd@yahoo.com> In RTL_SDR, option -b What does: "output_block_size (default 16*16384)" mean? I have been searching and I just can't find that explained anywhere. Thanks, Pete From vvvelichkov at gmail.com Fri May 31 20:14:03 2019 From: vvvelichkov at gmail.com (Vasil Velichkov) Date: Fri, 31 May 2019 23:14:03 +0300 Subject: RTL_SDR "output_block_size (default 16*16384)" In-Reply-To: <2ff66056-843d-b403-6233-e375ee0228dd@yahoo.com> References: <2ff66056-843d-b403-6233-e375ee0228dd@yahoo.com> Message-ID: <8eda73b0-9d71-c0d3-8402-804776140f97@gmail.com> Hi Pete, On 31/05/2019 19.59, P C wrote: > > In RTL_SDR, option -b > > What does: > "output_block_size (default 16*16384)" mean? > > I have been searching and I just can't find that explained anywhere. It's the size of the buffer that's used while capturing in synchronous mode. http://git.osmocom.org/rtl-sdr/tree/src/rtl_sdr.c#n143 http://git.osmocom.org/rtl-sdr/tree/src/rtl_sdr.c#n174 http://git.osmocom.org/rtl-sdr/tree/src/rtl_sdr.c#n236 Regards, Vasil