How RTL-SDR samples signals

Michael Karcher osmosdr at
Tue Aug 20 07:32:27 UTC 2013

Am Dienstag, den 20.08.2013, 14:24 +1000 schrieb David Basden:

As far as I understand it, sampling really happens at 28.8MHz with
probably 8 bits per channel. These ADCs are integrated in the RTL2832U
chip. After sampling, the samples are filtered using a symmetric FIR
filter (I reported how that filter is programmed around a year ago on
this list), then resampled to four times the user ADC. At that stage, a
second FIR anti-alias filter which seems ot be fixed (or running on
default coefficients all the time) kicks in before down-sampling to the
requested sample rate.

The 7-bit ADC quoted by jdow is also present on the chip, but it is a
low-bandwidth ADC. Some tuner chips, like the FC0012 (one of my dongles
has that chip) have a wide-bandwidth rectifier indicating the total RF
level at the input, but only an analog output but no digital provision
to read that level. The 7-bit ADC is used to measure the RF level to set
the RF gain for the tuner.

The 3.2MSps limit is definitely caused by the USB interface in the RTL
chips, actually, in my experience, already 2.88MHz is sometimes dropping
samples. It seems (from comments in the vendor-provided DVB-T driver)
like there might be a way to run that chip in USB isochronous mode
instead of bulk mode, but I have no idea whether that would require
strap modification, or just fiddling with some registers in the USB
interface section.

> On Mon, Aug 19, 2013 at 08:47:20PM -0700, jdow wrote:
> > That doesn't necessarily square with "7-bit ADC for RF signals level
> > measurement". It's unclear to me where it would get the signal with
> > enough levels that a 7-bit ADC would get used. You'd have to decimate
> > down to 225 Msps or so in order to get 7 bits of data.
> > 
> > {^_^}   Joanne/W6MKU

  Michael Karcher

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