E4000 undocumented registers?
a.nielsen at shikadi.net
Sun Nov 11 01:52:52 UTC 2012
I've been looking at the E4000 tuner code and I have a couple of questions
that aren't answered in the datasheet. I'm hoping someone here might have
In the Elonics-supplied code when setting the frequency (around line 1339),
they always write a 1 into register 0x07 (Synth1), which is the "PLL locked"
register. Does this affect anything? The datasheet says it's read only and
librtlsdr only ever reads this value, it never writes to it.
Then, beginning at 82.9MHz and continuing at every multiple of 28.8MHz above
this, the first 7MHz is tuned differently, but the rest of the 21.8MHz in that
"channel" is set normally. This stops between 233.9MHz and 485.6MHz, then
resumes again at 8MHz increments instead of 7MHz up until 868MHz.
When tuned differently, register 0x05 (Input clock) gets set to 3, which isn't
listed in the datasheet (and also says 'do not write to this register').
Mostly (but not always) when this happens (i.e. first 7-8MHz of the channel),
register 0x07 bits 3-4 are also set to various arbitrary values. The
datasheet says 0 means "16-32MHz input clock freq range" but this code writes
1 and 2 into this field as well. It seems to write approximately these values:
1 up to 89.9MHz
0 up to 118.7MHz
1 up to 205.1MHz
2 up to 233.9MHz
0 up to 551.2MHz
1 up to 752.8MHz
2 up to 868MHz
0 after 868MHz
After the first 7-8MHz the rest of the 28.8MHz channel has the default 0 value
Does anyone know what these values control?
As a side note, register 0x08 (Synth2) appears to do something even though
it's listed as reserved. By setting particular bits I can get the rtl_test
program to not lock on to any frequency, but oddly enough rtl_fm still works
fine. I'm not sure what to make of this yet. I don't suppose this register
is documented anywhere else? I'm just wondering whether the datasheets
supplied by Elonics are different to the one that is now public.
: One of many copies is at
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