<p>laforge <strong>submitted</strong> this change.</p><p><a href="https://gerrit.osmocom.org/c/osmo-ccid-firmware/+/25612">View Change</a></p><div style="white-space:pre-wrap">Approvals:
Jenkins Builder: Verified
laforge: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sychronize atmel start config with the headers<br><br>Change-Id: Ib21847f6726920e3f97600a347f2a16f957a5e8e<br>---<br>M sysmoOCTSIM/atmel_start_config.atstart<br>M sysmoOCTSIM/config/hpl_oscctrl_config.h<br>M sysmoOCTSIM/config/hpl_rtc_config.h<br>M sysmoOCTSIM/config/peripheral_clk_config.h<br>M sysmoOCTSIM/hpl/core/hpl_init.c<br>5 files changed, 105 insertions(+), 56 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>index 73ad9bd..92ef0bb 100644</span><br><span>--- a/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>+++ b/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>@@ -2,12 +2,17 @@</span><br><span> name: sysmoOCTSIM</span><br><span> versions:</span><br><span> api: '1.0'</span><br><span style="color: hsl(0, 100%, 40%);">- backend: 1.5.122</span><br><span style="color: hsl(0, 100%, 40%);">- commit: 820baecf7dd115d94b0d42ee3b0b9d6ba2da7113</span><br><span style="color: hsl(0, 100%, 40%);">- content: 1.0.1507</span><br><span style="color: hsl(0, 100%, 40%);">- content_pack_name: acme-packs-all</span><br><span style="color: hsl(120, 100%, 40%);">+ backend: 1.8.580</span><br><span style="color: hsl(120, 100%, 40%);">+ commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c</span><br><span style="color: hsl(120, 100%, 40%);">+ content: unknown</span><br><span style="color: hsl(120, 100%, 40%);">+ content_pack_name: unknown</span><br><span> format: '2'</span><br><span style="color: hsl(0, 100%, 40%);">- frontend: 1.5.1877</span><br><span style="color: hsl(120, 100%, 40%);">+ frontend: 1.8.580</span><br><span style="color: hsl(120, 100%, 40%);">+ packs_version_avr8: 1.0.1463</span><br><span style="color: hsl(120, 100%, 40%);">+ packs_version_qtouch: unknown</span><br><span style="color: hsl(120, 100%, 40%);">+ packs_version_sam: 1.0.1726</span><br><span style="color: hsl(120, 100%, 40%);">+ version_backend: 1.8.580</span><br><span style="color: hsl(120, 100%, 40%);">+ version_frontend: ''</span><br><span> board:</span><br><span> identifier: CustomBoard</span><br><span> device: SAME54N19A-AF</span><br><span>@@ -658,18 +663,46 @@</span><br><span> functionality: System</span><br><span> api: HAL:HPL:GCLK</span><br><span> configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ $input: 100000000</span><br><span style="color: hsl(120, 100%, 40%);">+ $input_id: Digital Phase Locked Loop (DPLL1)</span><br><span style="color: hsl(120, 100%, 40%);">+ RESERVED_InputFreq: 100000000</span><br><span style="color: hsl(120, 100%, 40%);">+ RESERVED_InputFreq_id: Digital Phase Locked Loop (DPLL1)</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Generic clock generator 0: 120000000</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Generic clock generator 1: 48000000</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Generic clock generator 10: 12000000</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Generic clock generator 11: 2000000</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Generic clock generator 2: 12500000</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Generic clock generator 3: 32768</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Generic clock generator 4: 50000000</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Generic clock generator 5: 20000000</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Generic clock generator 6: 7058823.529411765</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Generic clock generator 7: 12000000</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Generic clock generator 8: 12000000</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Generic clock generator 9: 12000000</span><br><span> enable_gclk_gen_0: true</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_0__externalclock: 1000000</span><br><span> enable_gclk_gen_1: true</span><br><span> enable_gclk_gen_10: false</span><br><span style="color: hsl(0, 100%, 40%);">- enable_gclk_gen_11: true</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_10__externalclock: 1000000</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_11: false</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_11__externalclock: 1000000</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_1__externalclock: 1000000</span><br><span> enable_gclk_gen_2: true</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_2__externalclock: 1000000</span><br><span> enable_gclk_gen_3: true</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_3__externalclock: 1000000</span><br><span> enable_gclk_gen_4: true</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_4__externalclock: 1000000</span><br><span> enable_gclk_gen_5: true</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_5__externalclock: 1000000</span><br><span> enable_gclk_gen_6: true</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_6__externalclock: 1000000</span><br><span> enable_gclk_gen_7: false</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_7__externalclock: 1000000</span><br><span> enable_gclk_gen_8: false</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_8__externalclock: 1000000</span><br><span> enable_gclk_gen_9: false</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_9__externalclock: 1000000</span><br><span> gclk_arch_gen_0_enable: true</span><br><span> gclk_arch_gen_0_idc: false</span><br><span> gclk_arch_gen_0_oe: false</span><br><span>@@ -680,7 +713,7 @@</span><br><span> gclk_arch_gen_10_oe: false</span><br><span> gclk_arch_gen_10_oov: false</span><br><span> gclk_arch_gen_10_runstdby: false</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_arch_gen_11_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_arch_gen_11_enable: false</span><br><span> gclk_arch_gen_11_idc: false</span><br><span> gclk_arch_gen_11_oe: false</span><br><span> gclk_arch_gen_11_oov: false</span><br><span>@@ -776,6 +809,11 @@</span><br><span> functionality: System</span><br><span> api: HAL:HPL:MCLK</span><br><span> configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ $input: 120000000</span><br><span style="color: hsl(120, 100%, 40%);">+ $input_id: Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+ RESERVED_InputFreq: 120000000</span><br><span style="color: hsl(120, 100%, 40%);">+ RESERVED_InputFreq_id: Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_CPU: 120000000</span><br><span> cpu_clock_source: Generic clock generator 0</span><br><span> cpu_div: '1'</span><br><span> enable_cpu_clock: true</span><br><span>@@ -799,6 +837,11 @@</span><br><span> functionality: System</span><br><span> api: HAL:HPL:OSC32KCTRL</span><br><span> configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ $input: 32768</span><br><span style="color: hsl(120, 100%, 40%);">+ $input_id: 32kHz External Crystal Oscillator (XOSC32K)</span><br><span style="color: hsl(120, 100%, 40%);">+ RESERVED_InputFreq: 32768</span><br><span style="color: hsl(120, 100%, 40%);">+ RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K)</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_RTC source: 32768</span><br><span> enable_osculp32k: true</span><br><span> enable_rtc_source: false</span><br><span> enable_xosc32k: true</span><br><span>@@ -809,11 +852,11 @@</span><br><span> xosc32k_arch_cfden: false</span><br><span> xosc32k_arch_cfdeo: false</span><br><span> xosc32k_arch_cgm: Standard mode</span><br><span style="color: hsl(0, 100%, 40%);">- xosc32k_arch_en1k: false</span><br><span style="color: hsl(120, 100%, 40%);">+ xosc32k_arch_en1k: true</span><br><span> xosc32k_arch_en32k: true</span><br><span> xosc32k_arch_enable: true</span><br><span style="color: hsl(0, 100%, 40%);">- xosc32k_arch_ondemand: true</span><br><span style="color: hsl(0, 100%, 40%);">- xosc32k_arch_runstdby: false</span><br><span style="color: hsl(120, 100%, 40%);">+ xosc32k_arch_ondemand: false</span><br><span style="color: hsl(120, 100%, 40%);">+ xosc32k_arch_runstdby: true</span><br><span> xosc32k_arch_startup: 62592us</span><br><span> xosc32k_arch_swben: false</span><br><span> xosc32k_arch_xtalen: true</span><br><span>@@ -827,19 +870,28 @@</span><br><span> functionality: System</span><br><span> api: HAL:HPL:OSCCTRL</span><br><span> configuration:</span><br><span style="color: hsl(0, 100%, 40%);">- dfll_arch_bplckc: false</span><br><span style="color: hsl(120, 100%, 40%);">+ $input: 32768</span><br><span style="color: hsl(120, 100%, 40%);">+ $input_id: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ RESERVED_InputFreq: 32768</span><br><span style="color: hsl(120, 100%, 40%);">+ RESERVED_InputFreq_id: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Digital Phase Locked Loop (DPLL0): 120000000</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_Digital Phase Locked Loop (DPLL1): 100000000</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000</span><br><span style="color: hsl(120, 100%, 40%);">+ dfll_arch_bplckc: true</span><br><span> dfll_arch_calibration: false</span><br><span> dfll_arch_ccdis: true</span><br><span> dfll_arch_coarse: 31</span><br><span> dfll_arch_cstep: 1</span><br><span> dfll_arch_enable: true</span><br><span> dfll_arch_fine: 128</span><br><span style="color: hsl(0, 100%, 40%);">- dfll_arch_fstep: 1</span><br><span style="color: hsl(120, 100%, 40%);">+ dfll_arch_fstep: 10</span><br><span> dfll_arch_llaw: false</span><br><span> dfll_arch_ondemand: false</span><br><span> dfll_arch_qldis: false</span><br><span> dfll_arch_runstdby: false</span><br><span style="color: hsl(0, 100%, 40%);">- dfll_arch_stable: false</span><br><span style="color: hsl(120, 100%, 40%);">+ dfll_arch_stable: true</span><br><span> dfll_arch_usbcrm: true</span><br><span> dfll_arch_waitlock: false</span><br><span> dfll_mode: Closed Loop Mode</span><br><span>@@ -863,7 +915,7 @@</span><br><span> fdpll0_clock_div: 2</span><br><span> fdpll0_ldr: 59</span><br><span> fdpll0_ldrfrac: 0</span><br><span style="color: hsl(0, 100%, 40%);">- fdpll0_ref_clock: Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+ fdpll0_ref_clock: External Crystal Oscillator 8-48MHz (XOSC1)</span><br><span> fdpll1_arch_dcoen: false</span><br><span> fdpll1_arch_enable: true</span><br><span> fdpll1_arch_filter: 0</span><br><span>@@ -877,7 +929,7 @@</span><br><span> fdpll1_clock_div: 2</span><br><span> fdpll1_ldr: 49</span><br><span> fdpll1_ldrfrac: 0</span><br><span style="color: hsl(0, 100%, 40%);">- fdpll1_ref_clock: Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+ fdpll1_ref_clock: External Crystal Oscillator 8-48MHz (XOSC1)</span><br><span> xosc0_arch_cfden: false</span><br><span> xosc0_arch_enable: false</span><br><span> xosc0_arch_enalc: false</span><br><span>@@ -969,7 +1021,7 @@</span><br><span> api: HAL:Driver:Calendar</span><br><span> configuration:</span><br><span> rtc_arch_init_reset: true</span><br><span style="color: hsl(0, 100%, 40%);">- rtc_arch_prescaler: Peripheral clock divided by 1</span><br><span style="color: hsl(120, 100%, 40%);">+ rtc_arch_prescaler: Peripheral clock divided by 1024</span><br><span> rtc_cmpeo0: false</span><br><span> rtc_cmpeo1: false</span><br><span> rtc_event_control: false</span><br><span>@@ -1037,11 +1089,11 @@</span><br><span> usart_gtime: 2-bit times</span><br><span> usart_inack: NACK is transmitted when a parity error is received.</span><br><span> usart_inverse_enabled: false</span><br><span style="color: hsl(0, 100%, 40%);">- usart_iso7816_type: T=0</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_iso7816_type: T=1</span><br><span> usart_maxiter: 7</span><br><span> usart_parity: Even parity</span><br><span> usart_rx_enable: true</span><br><span style="color: hsl(0, 100%, 40%);">- usart_stop_bit: One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_stop_bit: Two stop bits</span><br><span> usart_tx_enable: true</span><br><span> optional_signals: []</span><br><span> variant:</span><br><span>@@ -1084,11 +1136,11 @@</span><br><span> usart_gtime: 2-bit times</span><br><span> usart_inack: NACK is transmitted when a parity error is received.</span><br><span> usart_inverse_enabled: false</span><br><span style="color: hsl(0, 100%, 40%);">- usart_iso7816_type: T=0</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_iso7816_type: T=1</span><br><span> usart_maxiter: 7</span><br><span> usart_parity: Even parity</span><br><span> usart_rx_enable: true</span><br><span style="color: hsl(0, 100%, 40%);">- usart_stop_bit: One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_stop_bit: Two stop bits</span><br><span> usart_tx_enable: true</span><br><span> optional_signals: []</span><br><span> variant:</span><br><span>@@ -1131,11 +1183,11 @@</span><br><span> usart_gtime: 2-bit times</span><br><span> usart_inack: NACK is transmitted when a parity error is received.</span><br><span> usart_inverse_enabled: false</span><br><span style="color: hsl(0, 100%, 40%);">- usart_iso7816_type: T=0</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_iso7816_type: T=1</span><br><span> usart_maxiter: 7</span><br><span> usart_parity: Even parity</span><br><span> usart_rx_enable: true</span><br><span style="color: hsl(0, 100%, 40%);">- usart_stop_bit: One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_stop_bit: Two stop bits</span><br><span> usart_tx_enable: true</span><br><span> optional_signals: []</span><br><span> variant:</span><br><span>@@ -1178,11 +1230,11 @@</span><br><span> usart_gtime: 2-bit times</span><br><span> usart_inack: NACK is transmitted when a parity error is received.</span><br><span> usart_inverse_enabled: false</span><br><span style="color: hsl(0, 100%, 40%);">- usart_iso7816_type: T=0</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_iso7816_type: T=1</span><br><span> usart_maxiter: 7</span><br><span> usart_parity: Even parity</span><br><span> usart_rx_enable: true</span><br><span style="color: hsl(0, 100%, 40%);">- usart_stop_bit: One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_stop_bit: Two stop bits</span><br><span> usart_tx_enable: true</span><br><span> optional_signals: []</span><br><span> variant:</span><br><span>@@ -1225,11 +1277,11 @@</span><br><span> usart_gtime: 2-bit times</span><br><span> usart_inack: NACK is transmitted when a parity error is received.</span><br><span> usart_inverse_enabled: false</span><br><span style="color: hsl(0, 100%, 40%);">- usart_iso7816_type: T=0</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_iso7816_type: T=1</span><br><span> usart_maxiter: 7</span><br><span> usart_parity: Even parity</span><br><span> usart_rx_enable: true</span><br><span style="color: hsl(0, 100%, 40%);">- usart_stop_bit: One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_stop_bit: Two stop bits</span><br><span> usart_tx_enable: true</span><br><span> optional_signals: []</span><br><span> variant:</span><br><span>@@ -1272,11 +1324,11 @@</span><br><span> usart_gtime: 2-bit times</span><br><span> usart_inack: NACK is transmitted when a parity error is received.</span><br><span> usart_inverse_enabled: false</span><br><span style="color: hsl(0, 100%, 40%);">- usart_iso7816_type: T=0</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_iso7816_type: T=1</span><br><span> usart_maxiter: 7</span><br><span> usart_parity: Even parity</span><br><span> usart_rx_enable: true</span><br><span style="color: hsl(0, 100%, 40%);">- usart_stop_bit: One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_stop_bit: Two stop bits</span><br><span> usart_tx_enable: true</span><br><span> optional_signals: []</span><br><span> variant:</span><br><span>@@ -1319,11 +1371,11 @@</span><br><span> usart_gtime: 2-bit times</span><br><span> usart_inack: NACK is transmitted when a parity error is received.</span><br><span> usart_inverse_enabled: false</span><br><span style="color: hsl(0, 100%, 40%);">- usart_iso7816_type: T=0</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_iso7816_type: T=1</span><br><span> usart_maxiter: 7</span><br><span> usart_parity: Even parity</span><br><span> usart_rx_enable: true</span><br><span style="color: hsl(0, 100%, 40%);">- usart_stop_bit: One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_stop_bit: Two stop bits</span><br><span> usart_tx_enable: true</span><br><span> optional_signals: []</span><br><span> variant:</span><br><span>@@ -1416,9 +1468,9 @@</span><br><span> usb_ep5_I_CACHE: No cache</span><br><span> usb_ep6_I_CACHE: No cache</span><br><span> usb_ep7_I_CACHE: No cache</span><br><span style="color: hsl(0, 100%, 40%);">- usbd_arch_max_ep_n: 2 (EP 0x82 or 0x02)</span><br><span style="color: hsl(120, 100%, 40%);">+ usbd_arch_max_ep_n: 4 (EP 0x84 or 0x04)</span><br><span> usbd_arch_speed: Full speed</span><br><span style="color: hsl(0, 100%, 40%);">- usbd_num_ep_sp: 4 (EP0 + 3 endpoints)</span><br><span style="color: hsl(120, 100%, 40%);">+ usbd_num_ep_sp: 7 (EP0 + 6 endpoints)</span><br><span> optional_signals: []</span><br><span> variant:</span><br><span> specification: default</span><br><span>@@ -1664,3 +1716,4 @@</span><br><span> user_label: SDA2</span><br><span> configuration: null</span><br><span> toolchain_options: []</span><br><span style="color: hsl(120, 100%, 40%);">+static_files: []</span><br><span>diff --git a/sysmoOCTSIM/config/hpl_oscctrl_config.h b/sysmoOCTSIM/config/hpl_oscctrl_config.h</span><br><span>index a7bc9b9..d27c869 100644</span><br><span>--- a/sysmoOCTSIM/config/hpl_oscctrl_config.h</span><br><span>+++ b/sysmoOCTSIM/config/hpl_oscctrl_config.h</span><br><span>@@ -404,7 +404,6 @@</span><br><span> // <i> Select the clock source.</span><br><span> // <id> fdpll0_ref_clock</span><br><span> #ifndef CONF_FDPLL0_GCLK</span><br><span style="color: hsl(0, 100%, 40%);">-// directly use XOSC1 as clock input (no need to use an additional GCLK)</span><br><span> #define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC1</span><br><span> #endif</span><br><span> </span><br><span>@@ -431,23 +430,24 @@</span><br><span> #endif</span><br><span> </span><br><span> // <o> Loop Divider Ratio Fractional Part <0x0-0x1F></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register</span><br><span> // <id> fdpll0_ldrfrac</span><br><span> #ifndef CONF_FDPLL0_LDRFRAC</span><br><span> #define CONF_FDPLL0_LDRFRAC 0x0</span><br><span> #endif</span><br><span> </span><br><span> // <o> Loop Divider Ratio Integer Part <0x0-0x1FFF></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register</span><br><span> // <id> fdpll0_ldr</span><br><span> #ifndef CONF_FDPLL0_LDR</span><br><span style="color: hsl(0, 100%, 40%);">-// 2 MHz input clock * ( <59> + 1 = 60 ) = 120 MHz output clock</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL0_LDR 59</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL0_LDR 0x3b</span><br><span> #endif</span><br><span> </span><br><span> // <o> Clock Divider <0x0-0x7FF></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> This Clock divider is only for XOSC clock input to DPLL</span><br><span> // <id> fdpll0_clock_div</span><br><span> #ifndef CONF_FDPLL0_DIV</span><br><span style="color: hsl(0, 100%, 40%);">-// XOSC1 = 12 MHz, divide by 2 * ( <2> + 1 ) = 6 to have a 2 MHz clock input (maximum is 3.4 MHz)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL0_DIV 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL0_DIV 0x2</span><br><span> #endif</span><br><span> </span><br><span> // <q> DCO Filter Enable</span><br><span>@@ -488,7 +488,6 @@</span><br><span> // <0x3=>XOSC1 clock reference</span><br><span> // <id> fdpll0_arch_refclk</span><br><span> #ifndef CONF_FDPLL0_REFCLK</span><br><span style="color: hsl(0, 100%, 40%);">-// XOSC1 is used as input signal, thus also use it as reference</span><br><span> #define CONF_FDPLL0_REFCLK 0x3</span><br><span> #endif</span><br><span> </span><br><span>@@ -533,7 +532,6 @@</span><br><span> // <i> Select the clock source.</span><br><span> // <id> fdpll1_ref_clock</span><br><span> #ifndef CONF_FDPLL1_GCLK</span><br><span style="color: hsl(0, 100%, 40%);">-// directly use XOSC1 as clock input (no need to use an additional GCLK)</span><br><span> #define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC1</span><br><span> #endif</span><br><span> </span><br><span>@@ -560,23 +558,24 @@</span><br><span> #endif</span><br><span> </span><br><span> // <o> Loop Divider Ratio Fractional Part <0x0-0x1F></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register</span><br><span> // <id> fdpll1_ldrfrac</span><br><span> #ifndef CONF_FDPLL1_LDRFRAC</span><br><span> #define CONF_FDPLL1_LDRFRAC 0x0</span><br><span> #endif</span><br><span> </span><br><span> // <o> Loop Divider Ratio Integer Part <0x0-0x1FFF></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register</span><br><span> // <id> fdpll1_ldr</span><br><span> #ifndef CONF_FDPLL1_LDR</span><br><span style="color: hsl(0, 100%, 40%);">-// 2 MHz input clock * ( <49> + 1 = 50 ) = 100 MHz output clock</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL1_LDR 49</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL1_LDR 0x31</span><br><span> #endif</span><br><span> </span><br><span> // <o> Clock Divider <0x0-0x7FF></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> This Clock divider is only for XOSC clock input to DPLL</span><br><span> // <id> fdpll1_clock_div</span><br><span> #ifndef CONF_FDPLL1_DIV</span><br><span style="color: hsl(0, 100%, 40%);">-// XOSC1 = 12 MHz, divide by 2 * ( <2> + 1 ) = 6 to have a 2 MHz clock input (maximum is 3.4 MHz)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL1_DIV 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL1_DIV 0x2</span><br><span> #endif</span><br><span> </span><br><span> // <q> DCO Filter Enable</span><br><span>@@ -617,7 +616,6 @@</span><br><span> // <0x3=>XOSC1 clock reference</span><br><span> // <id> fdpll1_arch_refclk</span><br><span> #ifndef CONF_FDPLL1_REFCLK</span><br><span style="color: hsl(0, 100%, 40%);">-// XOSC1 is used as input signal, thus also use it as reference</span><br><span> #define CONF_FDPLL1_REFCLK 0x3</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/sysmoOCTSIM/config/hpl_rtc_config.h b/sysmoOCTSIM/config/hpl_rtc_config.h</span><br><span>index 3961d40..0e795ba 100644</span><br><span>--- a/sysmoOCTSIM/config/hpl_rtc_config.h</span><br><span>+++ b/sysmoOCTSIM/config/hpl_rtc_config.h</span><br><span>@@ -35,7 +35,7 @@</span><br><span> // <id> rtc_arch_prescaler</span><br><span> #ifndef CONF_RTC_PRESCALER</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_RTC_PRESCALER 0xB</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_RTC_PRESCALER 0xb</span><br><span> </span><br><span> #endif</span><br><span> </span><br><span>diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>index 6d8ba10..205e33e 100644</span><br><span>--- a/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>+++ b/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>@@ -97,7 +97,7 @@</span><br><span> * \brief SERCOM0's Core Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 500000</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 12500000</span><br><span> #endif</span><br><span> </span><br><span> /**</span><br><span>@@ -177,7 +177,7 @@</span><br><span> * \brief SERCOM1's Core Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 500000</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 12500000</span><br><span> #endif</span><br><span> </span><br><span> /**</span><br><span>@@ -257,7 +257,7 @@</span><br><span> * \brief SERCOM2's Core Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 500000</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 12500000</span><br><span> #endif</span><br><span> </span><br><span> /**</span><br><span>@@ -337,7 +337,7 @@</span><br><span> * \brief SERCOM3's Core Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 500000</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 12500000</span><br><span> #endif</span><br><span> </span><br><span> /**</span><br><span>@@ -417,7 +417,7 @@</span><br><span> * \brief SERCOM4's Core Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 500000</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 12500000</span><br><span> #endif</span><br><span> </span><br><span> /**</span><br><span>@@ -497,7 +497,7 @@</span><br><span> * \brief SERCOM5's Core Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 500000</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 12500000</span><br><span> #endif</span><br><span> </span><br><span> /**</span><br><span>@@ -577,7 +577,7 @@</span><br><span> * \brief SERCOM6's Core Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_SERCOM6_CORE_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 500000</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 12500000</span><br><span> #endif</span><br><span> </span><br><span> /**</span><br><span>diff --git a/sysmoOCTSIM/hpl/core/hpl_init.c b/sysmoOCTSIM/hpl/core/hpl_init.c</span><br><span>index bb8425c..be0db93 100644</span><br><span>--- a/sysmoOCTSIM/hpl/core/hpl_init.c</span><br><span>+++ b/sysmoOCTSIM/hpl/core/hpl_init.c</span><br><span>@@ -42,12 +42,10 @@</span><br><span> #include <hal_cache.h></span><br><span> </span><br><span> /* Referenced GCLKs (out of 0~11), should be initialized firstly</span><br><span style="color: hsl(0, 100%, 40%);">- * - GCLK 11 for FDPLL1</span><br><span style="color: hsl(0, 100%, 40%);">- * - GCLK 11 for FDPLL0</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define _GCLK_INIT_1ST 0x00000800</span><br><span style="color: hsl(120, 100%, 40%);">+#define _GCLK_INIT_1ST 0x00000000</span><br><span> /* Not referenced GCLKs, initialized last */</span><br><span style="color: hsl(0, 100%, 40%);">-#define _GCLK_INIT_LAST 0x000007FF</span><br><span style="color: hsl(120, 100%, 40%);">+#define _GCLK_INIT_LAST 0x00000FFF</span><br><span> </span><br><span> /**</span><br><span> * \brief Initialize the hardware abstraction layer</span><br><span></span><br></pre><p>To view, visit <a href="https://gerrit.osmocom.org/c/osmo-ccid-firmware/+/25612">change 25612</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://gerrit.osmocom.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://gerrit.osmocom.org/c/osmo-ccid-firmware/+/25612"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: osmo-ccid-firmware </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ib21847f6726920e3f97600a347f2a16f957a5e8e </div>
<div style="display:none"> Gerrit-Change-Number: 25612 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Hoernchen <ewild@sysmocom.de> </div>
<div style="display:none"> Gerrit-Reviewer: Jenkins Builder </div>
<div style="display:none"> Gerrit-Reviewer: laforge <laforge@osmocom.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>