<p>laforge <strong>submitted</strong> this change.</p><p><a href="https://gerrit.osmocom.org/c/osmo-ccid-firmware/+/25613">View Change</a></p><div style="white-space:pre-wrap">Approvals:
Jenkins Builder: Verified
laforge: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">internal ul32k instead of external 32k osc<br><br>This should be fine, the slow clock for the uarts is not used for the<br>modes we're interested in, and the usb clock is derived from the usb sof<br>anyway, so it's not used as a reference there either.<br><br>This will most likely drift, but so did the external one, and a<br>free-running rtc without any external input was going to drift anyway,<br>considering the octsim is supposed to just run without being powered<br>down for a very long time.<br><br>Change-Id: I257b8854e1860ed698c4007efeb5d16e842b519a<br>---<br>M sysmoOCTSIM/atmel_start_config.atstart<br>M sysmoOCTSIM/config/hpl_gclk_config.h<br>M sysmoOCTSIM/config/hpl_osc32kctrl_config.h<br>M sysmoOCTSIM/config/peripheral_clk_config.h<br>4 files changed, 18 insertions(+), 18 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>index 92ef0bb..74d73e0 100644</span><br><span>--- a/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>+++ b/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>@@ -663,10 +663,10 @@</span><br><span> functionality: System</span><br><span> api: HAL:HPL:GCLK</span><br><span> configuration:</span><br><span style="color: hsl(0, 100%, 40%);">- $input: 100000000</span><br><span style="color: hsl(0, 100%, 40%);">- $input_id: Digital Phase Locked Loop (DPLL1)</span><br><span style="color: hsl(0, 100%, 40%);">- RESERVED_InputFreq: 100000000</span><br><span style="color: hsl(0, 100%, 40%);">- RESERVED_InputFreq_id: Digital Phase Locked Loop (DPLL1)</span><br><span style="color: hsl(120, 100%, 40%);">+ $input: 32768</span><br><span style="color: hsl(120, 100%, 40%);">+ $input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)</span><br><span style="color: hsl(120, 100%, 40%);">+ RESERVED_InputFreq: 32768</span><br><span style="color: hsl(120, 100%, 40%);">+ RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)</span><br><span> _$freq_output_Generic clock generator 0: 120000000</span><br><span> _$freq_output_Generic clock generator 1: 48000000</span><br><span> _$freq_output_Generic clock generator 10: 12000000</span><br><span>@@ -780,7 +780,7 @@</span><br><span> gclk_gen_2_oscillator: Digital Phase Locked Loop (DPLL1)</span><br><span> gclk_gen_3_div: 1</span><br><span> gclk_gen_3_div_sel: false</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K)</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_gen_3_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)</span><br><span> gclk_gen_4_div: 2</span><br><span> gclk_gen_4_div_sel: false</span><br><span> gclk_gen_4_oscillator: Digital Phase Locked Loop (DPLL1)</span><br><span>@@ -838,23 +838,23 @@</span><br><span> api: HAL:HPL:OSC32KCTRL</span><br><span> configuration:</span><br><span> $input: 32768</span><br><span style="color: hsl(0, 100%, 40%);">- $input_id: 32kHz External Crystal Oscillator (XOSC32K)</span><br><span style="color: hsl(120, 100%, 40%);">+ $input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)</span><br><span> RESERVED_InputFreq: 32768</span><br><span style="color: hsl(0, 100%, 40%);">- RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K)</span><br><span style="color: hsl(0, 100%, 40%);">- _$freq_output_RTC source: 32768</span><br><span style="color: hsl(120, 100%, 40%);">+ RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)</span><br><span style="color: hsl(120, 100%, 40%);">+ _$freq_output_RTC source: 1024</span><br><span> enable_osculp32k: true</span><br><span> enable_rtc_source: false</span><br><span style="color: hsl(0, 100%, 40%);">- enable_xosc32k: true</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_xosc32k: false</span><br><span> osculp32k_calib: 0</span><br><span> osculp32k_calib_enable: false</span><br><span style="color: hsl(0, 100%, 40%);">- rtc_1khz_selection: false</span><br><span style="color: hsl(0, 100%, 40%);">- rtc_source_oscillator: 32kHz External Crystal Oscillator (XOSC32K)</span><br><span style="color: hsl(120, 100%, 40%);">+ rtc_1khz_selection: true</span><br><span style="color: hsl(120, 100%, 40%);">+ rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)</span><br><span> xosc32k_arch_cfden: false</span><br><span> xosc32k_arch_cfdeo: false</span><br><span> xosc32k_arch_cgm: Standard mode</span><br><span> xosc32k_arch_en1k: true</span><br><span> xosc32k_arch_en32k: true</span><br><span style="color: hsl(0, 100%, 40%);">- xosc32k_arch_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ xosc32k_arch_enable: false</span><br><span> xosc32k_arch_ondemand: false</span><br><span> xosc32k_arch_runstdby: true</span><br><span> xosc32k_arch_startup: 62592us</span><br><span>diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h</span><br><span>index 158fc93..f2b75bf 100644</span><br><span>--- a/sysmoOCTSIM/config/hpl_gclk_config.h</span><br><span>+++ b/sysmoOCTSIM/config/hpl_gclk_config.h</span><br><span>@@ -252,7 +252,7 @@</span><br><span> // <i> This defines the clock source for generic clock generator 3</span><br><span> // <id> gclk_gen_3_oscillator</span><br><span> #ifndef CONF_GCLK_GEN_3_SOURCE</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_OSCULP32K</span><br><span> #endif</span><br><span> </span><br><span> // <q> Run in Standby</span><br><span>diff --git a/sysmoOCTSIM/config/hpl_osc32kctrl_config.h b/sysmoOCTSIM/config/hpl_osc32kctrl_config.h</span><br><span>index f41861e..7bcb41b 100644</span><br><span>--- a/sysmoOCTSIM/config/hpl_osc32kctrl_config.h</span><br><span>+++ b/sysmoOCTSIM/config/hpl_osc32kctrl_config.h</span><br><span>@@ -7,7 +7,7 @@</span><br><span> // <e> RTC Source configuration</span><br><span> // <id> enable_rtc_source</span><br><span> #ifndef CONF_RTCCTRL_CONFIG</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_RTCCTRL_CONFIG 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_RTCCTRL_CONFIG 0</span><br><span> #endif</span><br><span> </span><br><span> // <h> RTC source control</span><br><span>@@ -17,7 +17,7 @@</span><br><span> // <i> This defines the clock source for RTC</span><br><span> // <id> rtc_source_oscillator</span><br><span> #ifndef CONF_RTCCTRL_SRC</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K</span><br><span> #endif</span><br><span> </span><br><span> // <q> Use 1 kHz output</span><br><span>@@ -43,7 +43,7 @@</span><br><span> // <i> Indicates whether configuration for External 32K Osc is enabled or not</span><br><span> // <id> enable_xosc32k</span><br><span> #ifndef CONF_XOSC32K_CONFIG</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_XOSC32K_CONFIG 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_XOSC32K_CONFIG 0</span><br><span> #endif</span><br><span> </span><br><span> // <h> 32kHz External Crystal Oscillator Control</span><br><span>@@ -51,7 +51,7 @@</span><br><span> // <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not</span><br><span> // <id> xosc32k_arch_enable</span><br><span> #ifndef CONF_XOSC32K_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_XOSC32K_ENABLE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_XOSC32K_ENABLE 0</span><br><span> #endif</span><br><span> </span><br><span> // <o> Start-Up Time</span><br><span>diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>index 205e33e..0231d7d 100644</span><br><span>--- a/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>+++ b/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>@@ -25,7 +25,7 @@</span><br><span> * \brief RTC's Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_RTC_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_RTC_FREQUENCY 32768</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_RTC_FREQUENCY 1024</span><br><span> #endif</span><br><span> </span><br><span> // <y> Core Clock Source</span><br><span></span><br></pre><p>To view, visit <a href="https://gerrit.osmocom.org/c/osmo-ccid-firmware/+/25613">change 25613</a>. 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<div style="display:none"> Gerrit-Project: osmo-ccid-firmware </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I257b8854e1860ed698c4007efeb5d16e842b519a </div>
<div style="display:none"> Gerrit-Change-Number: 25613 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Hoernchen <ewild@sysmocom.de> </div>
<div style="display:none"> Gerrit-Reviewer: Jenkins Builder </div>
<div style="display:none"> Gerrit-Reviewer: laforge <laforge@osmocom.org> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>