<p>pespin has uploaded this change for <strong>review</strong>.</p><p><a href="https://gerrit.osmocom.org/c/osmo-trx/+/14998">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Move inband-signaling-usb documentation to UserManual<br><br>Change-Id: I4d6ef1f54f3d6c5a73ce00dc4640bd698f96842b<br>---<br>D Transceiver52M/inband-signaling-usb<br>A doc/manuals/chapters/device-usrp-inband-signaling-usb.adoc<br>M doc/manuals/chapters/trx-devices.adoc<br>3 files changed, 306 insertions(+), 314 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://gerrit.osmocom.org:29418/osmo-trx refs/changes/98/14998/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/Transceiver52M/inband-signaling-usb b/Transceiver52M/inband-signaling-usb</span><br><span>deleted file mode 100644</span><br><span>index 14f8347..0000000</span><br><span>--- a/Transceiver52M/inband-signaling-usb</span><br><span>+++ /dev/null</span><br><span>@@ -1,314 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-This file specifies the format of USB packets used for in-band data</span><br><span style="color: hsl(0, 100%, 40%);">-transmission and signaling on the USRP. All packets are 512-byte long,</span><br><span style="color: hsl(0, 100%, 40%);">-and are transfered using USB "bulk" transfers.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-IN packets are sent towards the host.</span><br><span style="color: hsl(0, 100%, 40%);">-OUT packets are sent away from the host.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-The layout is 32-bits wide. All data is transmitted in little-endian</span><br><span style="color: hsl(0, 100%, 40%);">-format across the USB.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- |O|U|D|S|E| RSSI | Chan | mbz | Tag | Payload Len |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Timestamp |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | |</span><br><span style="color: hsl(0, 100%, 40%);">- + +</span><br><span style="color: hsl(0, 100%, 40%);">- | Payload |</span><br><span style="color: hsl(0, 100%, 40%);">- . .</span><br><span style="color: hsl(0, 100%, 40%);">- . .</span><br><span style="color: hsl(0, 100%, 40%);">- . .</span><br><span style="color: hsl(0, 100%, 40%);">- | |</span><br><span style="color: hsl(0, 100%, 40%);">- + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | ... | .</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+ .</span><br><span style="color: hsl(0, 100%, 40%);">- . .</span><br><span style="color: hsl(0, 100%, 40%);">- . Padding .</span><br><span style="color: hsl(0, 100%, 40%);">- . .</span><br><span style="color: hsl(0, 100%, 40%);">- | |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- mbz Must be Zero: these bits must be zero in both IN and OUT packets.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- O Overrun Flag: set in an IN packet if an overrun condition was</span><br><span style="color: hsl(0, 100%, 40%);">- detected. Must be zero in OUT packets. Overrun occurs when</span><br><span style="color: hsl(0, 100%, 40%);">- the FPGA has data to transmit to the host and there is no</span><br><span style="color: hsl(0, 100%, 40%);">- buffer space available. This generally indicates a problem on</span><br><span style="color: hsl(0, 100%, 40%);">- the host. Either it is not keeping up, or it has configured</span><br><span style="color: hsl(0, 100%, 40%);">- the FPGA to transmit data at a higher rate than the transport</span><br><span style="color: hsl(0, 100%, 40%);">- (USB) can support.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- U Underrun Flag: set in an IN packet if an underrun condition</span><br><span style="color: hsl(0, 100%, 40%);">- was detected. Must be zero in OUT packets. Underrun occurs</span><br><span style="color: hsl(0, 100%, 40%);">- when the FPGA runs out of samples, and it's not between</span><br><span style="color: hsl(0, 100%, 40%);">- bursts. See the "End of Burst flag" below.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- D Dropped Packet Flag: Set in an IN packet if the FPGA</span><br><span style="color: hsl(0, 100%, 40%);">- discarded an OUT packet because its timestamp had already</span><br><span style="color: hsl(0, 100%, 40%);">- passed.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- S Start of Burst Flag: Set in an OUT packet if the data is the</span><br><span style="color: hsl(0, 100%, 40%);">- first segment of what is logically a continuous burst of data.</span><br><span style="color: hsl(0, 100%, 40%);">- Must be zero in IN packets.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- E End of Burst Flag: Set in an OUT packet if the data is the</span><br><span style="color: hsl(0, 100%, 40%);">- last segment of what is logically a continuous burst of data.</span><br><span style="color: hsl(0, 100%, 40%);">- Must be zero in IN packets. Underruns are not reported</span><br><span style="color: hsl(0, 100%, 40%);">- when the FPGA runs out of samples between bursts.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- RSSI 6-bit Received Strength Signal Indicator: Must be zero in OUT</span><br><span style="color: hsl(0, 100%, 40%);">- packets. In IN packets, indicates RSSI as reported by front end.</span><br><span style="color: hsl(0, 100%, 40%);">- FIXME The format and interpretation are to be determined.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Chan 5-bit logical channel number. Channel number 0x1f is reserved</span><br><span style="color: hsl(0, 100%, 40%);">- for control information. See "Control Channel" below. Other</span><br><span style="color: hsl(0, 100%, 40%);">- channels are "data channels." Each data channel is logically</span><br><span style="color: hsl(0, 100%, 40%);">- independent of the others. A data channel payload field</span><br><span style="color: hsl(0, 100%, 40%);">- contains a sequence of homogeneous samples. The format of the</span><br><span style="color: hsl(0, 100%, 40%);">- samples is determined by the configuration associated with the</span><br><span style="color: hsl(0, 100%, 40%);">- given channel. It is often the case that the payload field</span><br><span style="color: hsl(0, 100%, 40%);">- contains 32-bit complex samples, each containing 16-bit real</span><br><span style="color: hsl(0, 100%, 40%);">- and imaginary components.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Tag 4-bit tag for matching IN packets with OUT packets.</span><br><span style="color: hsl(0, 100%, 40%);">- [FIXME, write more...]</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Payload Len: 9-bit field that specifies the length of the payload</span><br><span style="color: hsl(0, 100%, 40%);">- field in bytes. Must be in the range 0 to 504 inclusive.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Timestamp: 32-bit timestamp.</span><br><span style="color: hsl(0, 100%, 40%);">- On IN packets, the timestamp indicates the time at which the</span><br><span style="color: hsl(0, 100%, 40%);">- first sample of the packet was produced by the A/D converter(s)</span><br><span style="color: hsl(0, 100%, 40%);">- for that channel. On OUT packets, the timestamp specifies the</span><br><span style="color: hsl(0, 100%, 40%);">- time at which the first sample in the packet should go out the</span><br><span style="color: hsl(0, 100%, 40%);">- D/A converter(s) for that channel. If a packet reaches the</span><br><span style="color: hsl(0, 100%, 40%);">- head of the transmit queue, and the current time is later than</span><br><span style="color: hsl(0, 100%, 40%);">- the timestamp, an error is assumed to have occurred and the</span><br><span style="color: hsl(0, 100%, 40%);">- packet is discarded. As a special case, the timestamp</span><br><span style="color: hsl(0, 100%, 40%);">- 0xffffffff is interpreted as "Now".</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- The time base is a free running 32-bit counter that is</span><br><span style="color: hsl(0, 100%, 40%);">- incremented by the A/D sample-clock.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Payload: Variable length field. Length is specified by the</span><br><span style="color: hsl(0, 100%, 40%);">- Payload Len field.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Padding: This field is 504 - Payload Len bytes long, and its content</span><br><span style="color: hsl(0, 100%, 40%);">- is unspecified. This field pads the packet out to a constant</span><br><span style="color: hsl(0, 100%, 40%);">- 512 bytes.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-"Data Channel" payload format:</span><br><span>--------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-If Chan != 0x1f, the packet is a "data packet" and the payload is a</span><br><span style="color: hsl(0, 100%, 40%);">-sequence of homogeneous samples. The format of the samples is</span><br><span style="color: hsl(0, 100%, 40%);">-determined by the configuration associated with the given channel. </span><br><span style="color: hsl(0, 100%, 40%);">-It is often the case that the payload field contains 32-bit complex</span><br><span style="color: hsl(0, 100%, 40%);">-samples, each containing 16-bit real and imaginary components.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-"Control Channel" payload format:</span><br><span>----------------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-If Chan == 0x1f, the packet is a "control packet". The control channel</span><br><span style="color: hsl(0, 100%, 40%);">-payload consists of a sequence of 0 or more sub-packets.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Each sub-packet starts on a 32-bit boundary, and consists of an 8-bit</span><br><span style="color: hsl(0, 100%, 40%);">-Opcode field, an 8-bit Length field, Length bytes of arguments, and 0,</span><br><span style="color: hsl(0, 100%, 40%);">-1, 2 or 3 bytes of padding to align the tail of the sub-packet to</span><br><span style="color: hsl(0, 100%, 40%);">-a 32-bit boundary.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Control channel packets shall be processed at the head of the queue,</span><br><span style="color: hsl(0, 100%, 40%);">-and shall observe the timestamp semantics described above.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-General sub-packet format:</span><br><span>---------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-//-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Opcode | Length | <length bytes> ... |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-//-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Specific sub-packet formats:</span><br><span>-----------------------------</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- RID: 6-bit Request-ID. Copied from request sub-packet into corresponding</span><br><span style="color: hsl(0, 100%, 40%);">- reply sub-packet. RID allows the host to match requests and replies.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Reg Number: 10-bit Register Number.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Ping Fixed Length:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Opcode: OP_PING_FIXED</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Opcode | 2 | RID | Ping Value |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Ping Fixed Length Reply:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Opcode: OP_PING_FIXED_REPLY</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Opcode | 2 | RID | Ping Value |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Write Register:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Opcode: OP_WRITE_REG</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Opcode | 6 | mbz | Reg Number |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Register Value |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Write Register Masked:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Opcode: OP_WRITE_REG_MASKED</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- REG[Num] = (REG[Num] & ~Mask) | (Value & Mask)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- That is, only the register bits that correspond to 1's in the</span><br><span style="color: hsl(0, 100%, 40%);">- mask are written with the new value.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Opcode | 10 | mbz | Reg Number |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Register Value |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Mask Value |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Read Register:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Opcode: OP_READ_REG</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Opcode | 2 | RID | Reg Number |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Read Register Reply:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Opcode: OP_READ_REG_REPLY</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Opcode | 6 | RID | Reg Number |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Register Value |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-I2C Write:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Opcode: OP_I2C_WRITE</span><br><span style="color: hsl(0, 100%, 40%);">- I2C Addr: 7-bit I2C address</span><br><span style="color: hsl(0, 100%, 40%);">- Data: The bytes to write to the I2C bus</span><br><span style="color: hsl(0, 100%, 40%);">- Length: Length of Data + 2</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Opcode | Length | mbz | I2C Addr |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Data ... .</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-I2C Read:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Opcode: OP_I2C_READ</span><br><span style="color: hsl(0, 100%, 40%);">- I2C Addr: 7-bit I2C address</span><br><span style="color: hsl(0, 100%, 40%);">- Nbytes: Number of bytes to read from I2C bus</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Opcode | 3 | RID | mbz | I2C Addr |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Nbytes | unspecified padding |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-I2C Read Reply:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Opcode: OP_I2C_READ_REPLY</span><br><span style="color: hsl(0, 100%, 40%);">- I2C Addr: 7-bit I2C address</span><br><span style="color: hsl(0, 100%, 40%);">- Data: Length - 2 bytes of data read from I2C bus.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Opcode | Length | RID | mbz | I2C Addr |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Data ... .</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-SPI Write:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Opcode: OP_SPI_WRITE</span><br><span style="color: hsl(0, 100%, 40%);">- Enables: Which SPI enables to assert (mask)</span><br><span style="color: hsl(0, 100%, 40%);">- Format: Specifies format of SPI data and Opt Header Bytes</span><br><span style="color: hsl(0, 100%, 40%);">- Opt Header Bytes: 2-byte field containing optional Tx bytes; see Format</span><br><span style="color: hsl(0, 100%, 40%);">- Data: The bytes to write to the SPI bus</span><br><span style="color: hsl(0, 100%, 40%);">- Length: Length of Data + 6</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Opcode | Length | mbz |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Enables | Format | Opt Header Bytes |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Data ... .</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-SPI Read:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Opcode: OP_SPI_READ</span><br><span style="color: hsl(0, 100%, 40%);">- Enables: Which SPI enables to assert (mask)</span><br><span style="color: hsl(0, 100%, 40%);">- Format: Specifies format of SPI data and Opt Header Bytes</span><br><span style="color: hsl(0, 100%, 40%);">- Opt Header Bytes: 2-byte field containing optional Tx bytes; see Format</span><br><span style="color: hsl(0, 100%, 40%);">- Nbytes: Number of bytes to read from SPI bus.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Opcode | 7 | RID | mbz |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Enables | Format | Opt Header Bytes |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Nbytes | unspecified padding |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-SPI Read Reply:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Opcode: OP_SPI_READ_REPLY</span><br><span style="color: hsl(0, 100%, 40%);">- Data: Length - 2 bytes of data read from SPI bus.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Opcode | Length | RID | mbz |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Data ... .</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-Delay:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Opcode: OP_DELAY</span><br><span style="color: hsl(0, 100%, 40%);">- Ticks: 16-bit unsigned delay count</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- Delay Ticks clock ticks before executing next operation.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">- | Opcode | 2 | Ticks |</span><br><span style="color: hsl(0, 100%, 40%);">- +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span>diff --git a/doc/manuals/chapters/device-usrp-inband-signaling-usb.adoc b/doc/manuals/chapters/device-usrp-inband-signaling-usb.adoc</span><br><span>new file mode 100644</span><br><span>index 0000000..7a4352f</span><br><span>--- /dev/null</span><br><span>+++ b/doc/manuals/chapters/device-usrp-inband-signaling-usb.adoc</span><br><span>@@ -0,0 +1,304 @@</span><br><span style="color: hsl(120, 100%, 40%);">+[[dev_usrp_inband_signaling_usb]]</span><br><span style="color: hsl(120, 100%, 40%);">+==== USRP in-band USB protocol</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+This section specifies the format of USB packets used for in-band data</span><br><span style="color: hsl(120, 100%, 40%);">+transmission and signaling on the USRP. All packets are 512-byte long,</span><br><span style="color: hsl(120, 100%, 40%);">+and are transfered using USB "bulk" transfers.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+IN packets are sent towards the host.</span><br><span style="color: hsl(120, 100%, 40%);">+OUT packets are sent away from the host.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+The layout is 32-bits wide. All data is transmitted in little-endian</span><br><span style="color: hsl(120, 100%, 40%);">+format across the USB.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+|O|U|D|S|E| RSSI | Chan | mbz | Tag | Payload Len |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Timestamp |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| |</span><br><span style="color: hsl(120, 100%, 40%);">++ +</span><br><span style="color: hsl(120, 100%, 40%);">+| Payload |</span><br><span style="color: hsl(120, 100%, 40%);">+. .</span><br><span style="color: hsl(120, 100%, 40%);">+. .</span><br><span style="color: hsl(120, 100%, 40%);">+. .</span><br><span style="color: hsl(120, 100%, 40%);">+| |</span><br><span style="color: hsl(120, 100%, 40%);">++ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| ... | .</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+ .</span><br><span style="color: hsl(120, 100%, 40%);">+. .</span><br><span style="color: hsl(120, 100%, 40%);">+. Padding .</span><br><span style="color: hsl(120, 100%, 40%);">+. .</span><br><span style="color: hsl(120, 100%, 40%);">+| |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+mbz: Must be Zero::</span><br><span style="color: hsl(120, 100%, 40%);">+These bits must be zero in both IN and OUT packets.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+O: Overrun Flag::</span><br><span style="color: hsl(120, 100%, 40%);">+Set in an IN packet if an overrun condition was detected. Must be zero in OUT</span><br><span style="color: hsl(120, 100%, 40%);">+packets. Overrun occurs when the FPGA has data to transmit to the host and there</span><br><span style="color: hsl(120, 100%, 40%);">+is no buffer space available. This generally indicates a problem on the host.</span><br><span style="color: hsl(120, 100%, 40%);">+Either it is not keeping up, or it has configured the FPGA to transmit data at a</span><br><span style="color: hsl(120, 100%, 40%);">+higher rate than the transport (USB) can support.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+U: Underrun Flag::</span><br><span style="color: hsl(120, 100%, 40%);">+Set in an IN packet if an underrun condition was detected. Must be zero in OUT</span><br><span style="color: hsl(120, 100%, 40%);">+packets. Underrun occurs when the FPGA runs out of samples, and it's not between</span><br><span style="color: hsl(120, 100%, 40%);">+bursts. See the "End of Burst flag" below.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+D: Dropped Packet Flag::</span><br><span style="color: hsl(120, 100%, 40%);">+Set in an IN packet if the FPGA discarded an OUT packet because its timestamp</span><br><span style="color: hsl(120, 100%, 40%);">+had already passed.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+S: Start of Burst Flag::</span><br><span style="color: hsl(120, 100%, 40%);">+Set in an OUT packet if the data is the first segment of what is logically a</span><br><span style="color: hsl(120, 100%, 40%);">+continuous burst of data. Must be zero in IN packets.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+E: End of Burst Flag::</span><br><span style="color: hsl(120, 100%, 40%);">+Set in an OUT packet if the data is the last segment of what is logically a</span><br><span style="color: hsl(120, 100%, 40%);">+continuous burst of data. Must be zero in IN packets. Underruns are not</span><br><span style="color: hsl(120, 100%, 40%);">+reported when the FPGA runs out of samples between bursts.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+RSSI: 6-bit Received Strength Signal Indicator::</span><br><span style="color: hsl(120, 100%, 40%);">+Must be zero in OUT packets. In IN packets, indicates RSSI as reported by front</span><br><span style="color: hsl(120, 100%, 40%);">+end. FIXME The format and interpretation are to be determined.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Chan: 5-bit logical channel number::</span><br><span style="color: hsl(120, 100%, 40%);">+Channel number 0x1f is reserved for control information. See "Control Channel"</span><br><span style="color: hsl(120, 100%, 40%);">+below. Other channels are "data channels". Each data channel is logically</span><br><span style="color: hsl(120, 100%, 40%);">+independent of the others. A data channel payload field contains a sequence of</span><br><span style="color: hsl(120, 100%, 40%);">+homogeneous samples. The format of the samples is determined by the</span><br><span style="color: hsl(120, 100%, 40%);">+configuration associated with the given channel. It is often the case that the</span><br><span style="color: hsl(120, 100%, 40%);">+payload field contains 32-bit complex samples, each containing 16-bit real and</span><br><span style="color: hsl(120, 100%, 40%);">+imaginary components.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Tag::</span><br><span style="color: hsl(120, 100%, 40%);">+4-bit tag for matching IN packets with OUT packets.</span><br><span style="color: hsl(120, 100%, 40%);">+//FIXME, write more...</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Payload Len::</span><br><span style="color: hsl(120, 100%, 40%);">+9-bit field that specifies the length of the payload field in bytes. Must be in</span><br><span style="color: hsl(120, 100%, 40%);">+the range 0 to 504 inclusive.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Timestamp: 32-bit timestamp::</span><br><span style="color: hsl(120, 100%, 40%);">+On IN packets, the timestamp indicates the time at which the first sample of the</span><br><span style="color: hsl(120, 100%, 40%);">+packet was produced by the A/D converter(s) for that channel. On OUT packets,</span><br><span style="color: hsl(120, 100%, 40%);">+the timestamp specifies the time at which the first sample in the packet should</span><br><span style="color: hsl(120, 100%, 40%);">+go out the D/A converter(s) for that channel. If a packet reaches the head of</span><br><span style="color: hsl(120, 100%, 40%);">+the transmit queue, and the current time is later than the timestamp, an error</span><br><span style="color: hsl(120, 100%, 40%);">+is assumed to have occurred and the packet is discarded. As a special case, the</span><br><span style="color: hsl(120, 100%, 40%);">+timestamp 0xffffffff is interpreted as "Now".</span><br><span style="color: hsl(120, 100%, 40%);">+The time base is a free running 32-bit counter that is incremented by the A/D</span><br><span style="color: hsl(120, 100%, 40%);">+sample-clock.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Payload::</span><br><span style="color: hsl(120, 100%, 40%);">+Variable length field Length is specified by the Payload Len field.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Padding::</span><br><span style="color: hsl(120, 100%, 40%);">+This field is 504 - Payload Len bytes long, and its content is unspecified.</span><br><span style="color: hsl(120, 100%, 40%);">+This field pads the packet out to a constant 512 bytes.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+===== "Data Channel" payload format</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+If `Chan != 0x1f`, the packet is a "data packet" and the payload is a sequence of</span><br><span style="color: hsl(120, 100%, 40%);">+homogeneous samples. The format of the samples is determined by the</span><br><span style="color: hsl(120, 100%, 40%);">+configuration associated with the given channel. It is often the case that the</span><br><span style="color: hsl(120, 100%, 40%);">+payload field contains 32-bit complex samples, each containing 16-bit real and</span><br><span style="color: hsl(120, 100%, 40%);">+imaginary components.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+===== "Control Channel" payload format</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+If `Chan == 0x1f`, the packet is a "control packet". The control channel payload</span><br><span style="color: hsl(120, 100%, 40%);">+consists of a sequence of 0 or more sub-packets.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Each sub-packet starts on a 32-bit boundary, and consists of an 8-bit Opcode</span><br><span style="color: hsl(120, 100%, 40%);">+field, an 8-bit Length field, Length bytes of arguments, and 0, 1, 2 or 3 bytes</span><br><span style="color: hsl(120, 100%, 40%);">+of padding to align the tail of the sub-packet to a 32-bit boundary.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Control channel packets shall be processed at the head of the queue, and shall</span><br><span style="color: hsl(120, 100%, 40%);">+observe the timestamp semantics described above.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+===== General sub-packet format</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-//-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Opcode | Length | <length bytes> ... |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-//-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+===== Specific sub-packet formats</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+RID: 6-bit Request-ID::</span><br><span style="color: hsl(120, 100%, 40%);">+Copied from request sub-packet into corresponding reply sub-packet. RID allows</span><br><span style="color: hsl(120, 100%, 40%);">+the host to match requests and replies.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Reg Number::</span><br><span style="color: hsl(120, 100%, 40%);">+10-bit Register Number.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Ping Fixed Length::</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Opcode: OP_PING_FIXED</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Opcode | 2 | RID | Ping Value |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Ping Fixed Length Reply::</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Opcode: OP_PING_FIXED_REPLY</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Opcode | 2 | RID | Ping Value |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Write Register::</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Opcode: OP_WRITE_REG</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Opcode | 6 | mbz | Reg Number |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Register Value |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Write Register Masked::</span><br><span style="color: hsl(120, 100%, 40%);">+Only the register bits that correspond to 1's in the mask are written</span><br><span style="color: hsl(120, 100%, 40%);">+with the new value. `REG[Num] = (REG[Num] & ~Mask) | (Value & Mask)`</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Opcode: OP_WRITE_REG_MASKED</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Opcode | 10 | mbz | Reg Number |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Register Value |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Mask Value |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Read Register::</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Opcode: OP_READ_REG</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Opcode | 2 | RID | Reg Number |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Read Register Reply::</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Opcode: OP_READ_REG_REPLY</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Opcode | 6 | RID | Reg Number |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Register Value |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+I2C Write::</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Opcode: OP_I2C_WRITE</span><br><span style="color: hsl(120, 100%, 40%);">+* I2C Addr: 7-bit I2C address</span><br><span style="color: hsl(120, 100%, 40%);">+* Data: The bytes to write to the I2C bus</span><br><span style="color: hsl(120, 100%, 40%);">+* Length: Length of Data + 2</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Opcode | Length | mbz | I2C Addr |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Data ... .</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+I2C Read::</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Opcode: OP_I2C_READ</span><br><span style="color: hsl(120, 100%, 40%);">+* I2C Addr: 7-bit I2C address</span><br><span style="color: hsl(120, 100%, 40%);">+* Nbytes: Number of bytes to read from I2C bus</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Opcode | 3 | RID | mbz | I2C Addr |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Nbytes | unspecified padding |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+I2C Read Reply::</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Opcode: OP_I2C_READ_REPLY</span><br><span style="color: hsl(120, 100%, 40%);">+* I2C Addr: 7-bit I2C address</span><br><span style="color: hsl(120, 100%, 40%);">+* Data: Length - 2 bytes of data read from I2C bus.</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Opcode | Length | RID | mbz | I2C Addr |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Data ... .</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPI Write::</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Opcode: OP_SPI_WRITE</span><br><span style="color: hsl(120, 100%, 40%);">+* Enables: Which SPI enables to assert (mask)</span><br><span style="color: hsl(120, 100%, 40%);">+* Format: Specifies format of SPI data and Opt Header Bytes</span><br><span style="color: hsl(120, 100%, 40%);">+* Opt Header Bytes: 2-byte field containing optional Tx bytes; see Format</span><br><span style="color: hsl(120, 100%, 40%);">+* Data: The bytes to write to the SPI bus</span><br><span style="color: hsl(120, 100%, 40%);">+* Length: Length of Data + 6</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Opcode | Length | mbz |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Enables | Format | Opt Header Bytes |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Data ... .</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPI Read::</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Opcode: OP_SPI_READ</span><br><span style="color: hsl(120, 100%, 40%);">+* Enables: Which SPI enables to assert (mask)</span><br><span style="color: hsl(120, 100%, 40%);">+* Format: Specifies format of SPI data and Opt Header Bytes</span><br><span style="color: hsl(120, 100%, 40%);">+* Opt Header Bytes: 2-byte field containing optional Tx bytes; see Format</span><br><span style="color: hsl(120, 100%, 40%);">+* Nbytes: Number of bytes to read from SPI bus.</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Opcode | 7 | RID | mbz |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Enables | Format | Opt Header Bytes |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Nbytes | unspecified padding |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+SPI Read Reply::</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Opcode: OP_SPI_READ_REPLY</span><br><span style="color: hsl(120, 100%, 40%);">+* Data: Length - 2 bytes of data read from SPI bus.</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Opcode | Length | RID | mbz |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Data ... .</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Delay::</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+* Opcode: OP_DELAY</span><br><span style="color: hsl(120, 100%, 40%);">+* Ticks: 16-bit unsigned delay count</span><br><span style="color: hsl(120, 100%, 40%);">+* Delay Ticks clock ticks before executing next operation.</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+| Opcode | 2 | Ticks |</span><br><span style="color: hsl(120, 100%, 40%);">++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</span><br><span style="color: hsl(120, 100%, 40%);">+----</span><br><span>diff --git a/doc/manuals/chapters/trx-devices.adoc b/doc/manuals/chapters/trx-devices.adoc</span><br><span>index 10c8529..3c21e59 100644</span><br><span>--- a/doc/manuals/chapters/trx-devices.adoc</span><br><span>+++ b/doc/manuals/chapters/trx-devices.adoc</span><br><span>@@ -29,6 +29,8 @@</span><br><span> </span><br><span> The binary _osmo-trx-usrp1_ is used to drive this device, see <<backend_usrp1>>.</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+include::./device-usrp-inband-signaling-usb.adoc[]</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> [[dev_ettus_b200]]</span><br><span> === Ettus B200</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://gerrit.osmocom.org/c/osmo-trx/+/14998">change 14998</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://gerrit.osmocom.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://gerrit.osmocom.org/c/osmo-trx/+/14998"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: osmo-trx </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I4d6ef1f54f3d6c5a73ce00dc4640bd698f96842b </div>
<div style="display:none"> Gerrit-Change-Number: 14998 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: pespin <pespin@sysmocom.de> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>