<p>osmith <strong>merged</strong> this change.</p><p><a href="https://gerrit.osmocom.org/c/osmo-ttcn3-hacks/+/14903">View Change</a></p><div style="white-space:pre-wrap">Approvals:
Jenkins Builder: Verified
pespin: Looks good to me, but someone else must approve
fixeria: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">msc/expected-results.xml: update from jenkins<br><br>Change-Id: I9110f7bcda2919ff04c63a99d554b53a793f0037<br>---<br>M msc/expected-results.xml<br>1 file changed, 102 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/msc/expected-results.xml b/msc/expected-results.xml</span><br><span>index ca8edd2..28a6728 100644</span><br><span>--- a/msc/expected-results.xml</span><br><span>+++ b/msc/expected-results.xml</span><br><span>@@ -1,11 +1,12 @@</span><br><span> <?xml version="1.0"?></span><br><span style="color: hsl(0, 100%, 40%);">-<testsuite name='Titan' tests='96' failures='2' errors='3' skipped='0' inconc='0' time='MASKED'></span><br><span style="color: hsl(120, 100%, 40%);">+<testsuite name='Titan' tests='154' failures='9' errors='2' skipped='0' inconc='0' time='MASKED'></span><br><span> <testcase classname='MSC_Tests' name='TC_cr_before_reset' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_tmsi' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_notmsi' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_imsi_reject' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_imsi_timeout_gsup' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_lu_imsi_auth3g_tmsi' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_cmserv_imsi_unknown' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_and_mo_call' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_auth_sai_timeout' time='MASKED'/></span><br><span>@@ -31,12 +32,7 @@</span><br><span> <testcase classname='MSC_Tests' name='TC_mo_setup_and_nothing' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_mo_crcx_ran_timeout' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_mo_crcx_ran_reject' time='MASKED'/></span><br><span style="color: hsl(0, 100%, 40%);">- <testcase classname='MSC_Tests' name='TC_mt_crcx_ran_reject' time='MASKED'></span><br><span style="color: hsl(0, 100%, 40%);">- <failure type='fail-verdict'>Timeout waiting for channel release</span><br><span style="color: hsl(0, 100%, 40%);">- MSC_Tests.ttcn:MASKED MSC_Tests control part</span><br><span style="color: hsl(0, 100%, 40%);">- MSC_Tests.ttcn:MASKED TC_mt_crcx_ran_reject testcase</span><br><span style="color: hsl(0, 100%, 40%);">- </failure></span><br><span style="color: hsl(0, 100%, 40%);">- </testcase></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_mt_crcx_ran_reject' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_mo_setup_and_dtmf_dup' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_gsup_cancel' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_1_13' time='MASKED'/></span><br><span>@@ -60,6 +56,7 @@</span><br><span> <testcase classname='MSC_Tests' name='TC_gsup_mt_sms_err' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_gsup_mt_sms_rp_mr' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_gsup_mo_mt_sms_rp_mr' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_gsup_mt_multi_part_sms' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_and_mo_ussd_single_request' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_and_mt_ussd_notification' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_and_mo_ussd_during_mt_call' time='MASKED'/></span><br><span>@@ -72,6 +69,10 @@</span><br><span> <testcase classname='MSC_Tests' name='TC_proc_ss_paging_fail' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_proc_ss_abort' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_cipher_complete_with_invalid_cipher' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_cipher_complete_1_without_cipher' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_cipher_complete_3_without_cipher' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_cipher_complete_13_without_cipher' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_lu_with_invalid_mcc_mnc' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_sgsap_reset' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_sgsap_lu' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_sgsap_lu_imsi_reject' time='MASKED'/></span><br><span>@@ -94,17 +95,17 @@</span><br><span> <testcase classname='MSC_Tests' name='TC_bssap_lu_sgsap_lu_and_mt_call' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_sgsap_lu_and_mt_call' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_sgsap_vlr_failure' time='MASKED'/></span><br><span style="color: hsl(0, 100%, 40%);">- <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_1_log_msc_debug' time='MASKED'/></span><br><span style="color: hsl(0, 100%, 40%);">- <testcase classname='MSC_Tests' name='TC_gsup_mt_multi_part_sms' time='MASKED'/></span><br><span style="color: hsl(0, 100%, 40%);">- <testcase classname='MSC_Tests' name='TC_mo_cc_bssmap_clear' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_ho_inter_bsc_unknown_cell' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_ho_inter_bsc' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_ho_inter_msc_out' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_imsi_auth3g_tmsi_check_imei' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_tmsi_check_imei' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_notmsi_check_imei' time='MASKED'/></span><br><span style="color: hsl(0, 100%, 40%);">- <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_nack' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_nack' time='MASKED'></span><br><span> <error type='DTE'></error></span><br><span> </testcase></span><br><span style="color: hsl(0, 100%, 40%);">- <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_err' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_err' time='MASKED'></span><br><span> <error type='DTE'></error></span><br><span> </testcase></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_early' time='MASKED'/></span><br><span>@@ -113,4 +114,93 @@</span><br><span> <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_notmsi_check_imei_early' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_early_nack' time='MASKED'/></span><br><span> <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_early_err' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_1_log_msc_debug' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_mo_cc_bssmap_clear' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_lu_and_mt_call_osmux' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_reject' time='MASKED'></span><br><span style="color: hsl(120, 100%, 40%);">+ <failure type='fail-verdict'>Tguard timeout</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_imsi_reject testcase</span><br><span style="color: hsl(120, 100%, 40%);">+ </failure></span><br><span style="color: hsl(120, 100%, 40%);">+ </testcase></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_timeout_gsup' time='MASKED'></span><br><span style="color: hsl(120, 100%, 40%);">+ <failure type='fail-verdict'>Tguard timeout</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_imsi_timeout_gsup testcase</span><br><span style="color: hsl(120, 100%, 40%);">+ </failure></span><br><span style="color: hsl(120, 100%, 40%);">+ </testcase></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_auth3g_tmsi' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_cmserv_imsi_unknown' time='MASKED'></span><br><span style="color: hsl(120, 100%, 40%);">+ <failure type='fail-verdict'>Tguard timeout</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED TC_iu_cmserv_imsi_unknown testcase</span><br><span style="color: hsl(120, 100%, 40%);">+ </failure></span><br><span style="color: hsl(120, 100%, 40%);">+ </testcase></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_call' time='MASKED'></span><br><span style="color: hsl(120, 100%, 40%);">+ <failure type='fail-verdict'>Tguard timeout</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_and_mo_call testcase</span><br><span style="color: hsl(120, 100%, 40%);">+ </failure></span><br><span style="color: hsl(120, 100%, 40%);">+ </testcase></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_auth_sai_timeout' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_auth_sai_err' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_release_request' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_disconnect' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_by_imei' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_imsi_detach_by_imsi' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_imsi_detach_by_tmsi' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_imsi_detach_by_imei' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_emerg_call_imei_reject' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_emerg_call_imsi' time='MASKED'></span><br><span style="color: hsl(120, 100%, 40%);">+ <failure type='fail-verdict'>Tguard timeout</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED TC_iu_emerg_call_imsi testcase</span><br><span style="color: hsl(120, 100%, 40%);">+ </failure></span><br><span style="color: hsl(120, 100%, 40%);">+ </testcase></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_establish_and_nothing' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_setup_and_nothing' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_crcx_ran_timeout' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_crcx_ran_reject' time='MASKED'></span><br><span style="color: hsl(120, 100%, 40%);">+ <failure type='fail-verdict'>Timeout waiting for channel release</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED TC_iu_mo_crcx_ran_reject testcase</span><br><span style="color: hsl(120, 100%, 40%);">+ </failure></span><br><span style="color: hsl(120, 100%, 40%);">+ </testcase></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_mt_crcx_ran_reject' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_cancel' time='MASKED'></span><br><span style="color: hsl(120, 100%, 40%);">+ <failure type='fail-verdict'>Tguard timeout</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED TC_iu_gsup_cancel testcase</span><br><span style="color: hsl(120, 100%, 40%);">+ </failure></span><br><span style="color: hsl(120, 100%, 40%);">+ </testcase></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_release_timeout' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests' name='TC_reset_two_1iu' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_sms' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_sms' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_sms_paging_and_nothing' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_smpp_mo_sms' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mo_sms' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mo_smma' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mt_sms_ack' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mt_sms_err' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mt_sms_rp_mr' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mo_mt_sms_rp_mr' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_ussd_single_request' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_ussd_notification' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_ussd_during_mt_call' time='MASKED'></span><br><span style="color: hsl(120, 100%, 40%);">+ <failure type='fail-verdict'>Tguard timeout</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_and_mo_ussd_during_mt_call testcase</span><br><span style="color: hsl(120, 100%, 40%);">+ </failure></span><br><span style="color: hsl(120, 100%, 40%);">+ </testcase></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_ussd_during_mt_call' time='MASKED'></span><br><span style="color: hsl(120, 100%, 40%);">+ <failure type='fail-verdict'>Tguard timeout</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part</span><br><span style="color: hsl(120, 100%, 40%);">+ MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_and_mt_ussd_during_mt_call testcase</span><br><span style="color: hsl(120, 100%, 40%);">+ </failure></span><br><span style="color: hsl(120, 100%, 40%);">+ </testcase></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_ussd_mo_release' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_ss_session_timeout' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_with_invalid_mcc_mnc' time='MASKED'/></span><br><span style="color: hsl(120, 100%, 40%);">+ <testcase classname='MSC_Tests_Iu' name='TC_mo_cc_iu_release' time='MASKED'/></span><br><span> </testsuite></span><br><span></span><br></pre><p>To view, visit <a href="https://gerrit.osmocom.org/c/osmo-ttcn3-hacks/+/14903">change 14903</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://gerrit.osmocom.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://gerrit.osmocom.org/c/osmo-ttcn3-hacks/+/14903"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: osmo-ttcn3-hacks </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I9110f7bcda2919ff04c63a99d554b53a793f0037 </div>
<div style="display:none"> Gerrit-Change-Number: 14903 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: osmith <osmith@sysmocom.de> </div>
<div style="display:none"> Gerrit-Reviewer: Jenkins Builder </div>
<div style="display:none"> Gerrit-Reviewer: fixeria <axilirator@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: osmith <osmith@sysmocom.de> </div>
<div style="display:none"> Gerrit-Reviewer: pespin <pespin@sysmocom.de> </div>
<div style="display:none"> Gerrit-MessageType: merged </div>