<p>Kévin Redon has uploaded this change for <strong>review</strong>.</p><p><a href="https://gerrit.osmocom.org/13686">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">minor: update atmel start project configuration<br><br>Change-Id: I8e719f1687befb9a3657a2e582165dec3cd00094<br>---<br>M sysmoOCTSIM/atmel_start_config.atstart<br>1 file changed, 13 insertions(+), 13 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://gerrit.osmocom.org:29418/osmo-ccid-firmware refs/changes/86/13686/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>index 51ec4f4..f40c43a 100644</span><br><span>--- a/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>+++ b/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>@@ -664,7 +664,7 @@</span><br><span> enable_gclk_gen_11: true</span><br><span> enable_gclk_gen_2: true</span><br><span> enable_gclk_gen_3: true</span><br><span style="color: hsl(0, 100%, 40%);">- enable_gclk_gen_4: false</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_4: true</span><br><span> enable_gclk_gen_5: true</span><br><span> enable_gclk_gen_6: false</span><br><span> enable_gclk_gen_7: false</span><br><span>@@ -700,7 +700,7 @@</span><br><span> gclk_arch_gen_3_oe: false</span><br><span> gclk_arch_gen_3_oov: false</span><br><span> gclk_arch_gen_3_runstdby: false</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_arch_gen_4_enable: false</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_arch_gen_4_enable: true</span><br><span> gclk_arch_gen_4_idc: false</span><br><span> gclk_arch_gen_4_oe: false</span><br><span> gclk_arch_gen_4_oov: false</span><br><span>@@ -742,7 +742,7 @@</span><br><span> gclk_gen_1_div: 1</span><br><span> gclk_gen_1_div_sel: false</span><br><span> gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M)</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_gen_2_div: 1</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_gen_2_div: 30</span><br><span> gclk_gen_2_div_sel: false</span><br><span> gclk_gen_2_oscillator: Digital Phase Locked Loop (DPLL1)</span><br><span> gclk_gen_3_div: 1</span><br><span>@@ -750,7 +750,7 @@</span><br><span> gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K)</span><br><span> gclk_gen_4_div: 1</span><br><span> gclk_gen_4_div_sel: false</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_gen_4_oscillator: Digital Phase Locked Loop (DPLL1)</span><br><span> gclk_gen_5_div: 5</span><br><span> gclk_gen_5_div_sel: false</span><br><span> gclk_gen_5_oscillator: Digital Phase Locked Loop (DPLL1)</span><br><span>@@ -976,7 +976,7 @@</span><br><span> usart_arch_ibon: false</span><br><span> usart_arch_runstdby: false</span><br><span> usart_arch_sfde: false</span><br><span style="color: hsl(0, 100%, 40%);">- usart_baud_rate: 9600</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_baud_rate: 6720</span><br><span> usart_character_size: 8 bits</span><br><span> usart_dsnack: The successive receive NACK is disable.</span><br><span> usart_gtime: 2-bit times</span><br><span>@@ -1023,7 +1023,7 @@</span><br><span> usart_arch_ibon: false</span><br><span> usart_arch_runstdby: false</span><br><span> usart_arch_sfde: false</span><br><span style="color: hsl(0, 100%, 40%);">- usart_baud_rate: 9600</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_baud_rate: 6720</span><br><span> usart_character_size: 8 bits</span><br><span> usart_dsnack: The successive receive NACK is disable.</span><br><span> usart_gtime: 2-bit times</span><br><span>@@ -1070,7 +1070,7 @@</span><br><span> usart_arch_ibon: false</span><br><span> usart_arch_runstdby: false</span><br><span> usart_arch_sfde: false</span><br><span style="color: hsl(0, 100%, 40%);">- usart_baud_rate: 9600</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_baud_rate: 6720</span><br><span> usart_character_size: 8 bits</span><br><span> usart_dsnack: The successive receive NACK is disable.</span><br><span> usart_gtime: 2-bit times</span><br><span>@@ -1117,7 +1117,7 @@</span><br><span> usart_arch_ibon: false</span><br><span> usart_arch_runstdby: false</span><br><span> usart_arch_sfde: false</span><br><span style="color: hsl(0, 100%, 40%);">- usart_baud_rate: 9600</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_baud_rate: 6720</span><br><span> usart_character_size: 8 bits</span><br><span> usart_dsnack: The successive receive NACK is disable.</span><br><span> usart_gtime: 2-bit times</span><br><span>@@ -1164,7 +1164,7 @@</span><br><span> usart_arch_ibon: false</span><br><span> usart_arch_runstdby: false</span><br><span> usart_arch_sfde: false</span><br><span style="color: hsl(0, 100%, 40%);">- usart_baud_rate: 9600</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_baud_rate: 6720</span><br><span> usart_character_size: 8 bits</span><br><span> usart_dsnack: The successive receive NACK is disable.</span><br><span> usart_gtime: 2-bit times</span><br><span>@@ -1211,7 +1211,7 @@</span><br><span> usart_arch_ibon: false</span><br><span> usart_arch_runstdby: false</span><br><span> usart_arch_sfde: false</span><br><span style="color: hsl(0, 100%, 40%);">- usart_baud_rate: 9600</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_baud_rate: 6720</span><br><span> usart_character_size: 8 bits</span><br><span> usart_dsnack: The successive receive NACK is disable.</span><br><span> usart_gtime: 2-bit times</span><br><span>@@ -1258,7 +1258,7 @@</span><br><span> usart_arch_ibon: false</span><br><span> usart_arch_runstdby: false</span><br><span> usart_arch_sfde: false</span><br><span style="color: hsl(0, 100%, 40%);">- usart_baud_rate: 9600</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_baud_rate: 6720</span><br><span> usart_character_size: 8 bits</span><br><span> usart_dsnack: The successive receive NACK is disable.</span><br><span> usart_gtime: 2-bit times</span><br><span>@@ -1330,7 +1330,7 @@</span><br><span> domain_group:</span><br><span> nodes:</span><br><span> - name: Core</span><br><span style="color: hsl(0, 100%, 40%);">- input: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 4</span><br><span> external: false</span><br><span> external_frequency: 0</span><br><span> - name: Slow</span><br><span>@@ -1338,7 +1338,7 @@</span><br><span> external: false</span><br><span> external_frequency: 0</span><br><span> configuration:</span><br><span style="color: hsl(0, 100%, 40%);">- core_gclk_selection: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ core_gclk_selection: Generic clock generator 4</span><br><span> slow_gclk_selection: Generic clock generator 3</span><br><span> USB_DEVICE_INSTANCE:</span><br><span> user_label: USB_DEVICE_INSTANCE</span><br><span></span><br></pre><p>To view, visit <a href="https://gerrit.osmocom.org/13686">change 13686</a>. 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<div style="display:none"> Gerrit-Project: osmo-ccid-firmware </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8e719f1687befb9a3657a2e582165dec3cd00094 </div>
<div style="display:none"> Gerrit-Change-Number: 13686 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kévin Redon <kredon@sysmocom.de> </div>