<p>Harald Welte <strong>merged</strong> this change.</p><p><a href="https://gerrit.osmocom.org/12797">View Change</a></p><div style="white-space:pre-wrap">Approvals:
Jenkins Builder: Verified
Harald Welte: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">switch CPU clock to 120 MHz<br><br>use GCLK11 to bring external crystal oscillator XOSC1 from 12 MHz<br>to 2MHz<br>use DPLL0 to multiply 2 MHz to 120 MHz.<br>the division is first needed because the DPLL0 maximum input<br>frequency is 3.2 MHz<br><br>Change-Id: I642e724ec56a376addf21cc58ecd2ef1b40bd116<br>---<br>M sysmoOCTSIM/atmel_start_config.atstart<br>M sysmoOCTSIM/config/hpl_gclk_config.h<br>M sysmoOCTSIM/config/hpl_oscctrl_config.h<br>M sysmoOCTSIM/config/peripheral_clk_config.h<br>M sysmoOCTSIM/hpl/core/hpl_init.c<br>5 files changed, 28 insertions(+), 27 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>index 385c890..5e27536 100644</span><br><span>--- a/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>+++ b/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>@@ -646,7 +646,7 @@</span><br><span> enable_gclk_gen_0: true</span><br><span> enable_gclk_gen_1: true</span><br><span> enable_gclk_gen_10: false</span><br><span style="color: hsl(0, 100%, 40%);">- enable_gclk_gen_11: false</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_11: true</span><br><span> enable_gclk_gen_2: false</span><br><span> enable_gclk_gen_3: true</span><br><span> enable_gclk_gen_4: false</span><br><span>@@ -665,7 +665,7 @@</span><br><span> gclk_arch_gen_10_oe: false</span><br><span> gclk_arch_gen_10_oov: false</span><br><span> gclk_arch_gen_10_runstdby: false</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_arch_gen_11_enable: false</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_arch_gen_11_enable: true</span><br><span> gclk_arch_gen_11_idc: false</span><br><span> gclk_arch_gen_11_oe: false</span><br><span> gclk_arch_gen_11_oov: false</span><br><span>@@ -717,13 +717,13 @@</span><br><span> gclk_arch_gen_9_runstdby: false</span><br><span> gclk_gen_0_div: 1</span><br><span> gclk_gen_0_div_sel: false</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_gen_0_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0)</span><br><span> gclk_gen_10_div: 1</span><br><span> gclk_gen_10_div_sel: false</span><br><span> gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC0)</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_gen_11_div: 1</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_gen_11_div: 6</span><br><span> gclk_gen_11_div_sel: false</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC0)</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)</span><br><span> gclk_gen_1_div: 1</span><br><span> gclk_gen_1_div_sel: false</span><br><span> gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M)</span><br><span>@@ -829,24 +829,24 @@</span><br><span> dfll_mul: 48000</span><br><span> dfll_ref_clock: Generic clock generator 3</span><br><span> enable_dfll: true</span><br><span style="color: hsl(0, 100%, 40%);">- enable_fdpll0: false</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_fdpll0: true</span><br><span> enable_fdpll1: false</span><br><span> enable_xosc0: false</span><br><span> enable_xosc1: true</span><br><span> fdpll0_arch_dcoen: false</span><br><span style="color: hsl(0, 100%, 40%);">- fdpll0_arch_enable: false</span><br><span style="color: hsl(120, 100%, 40%);">+ fdpll0_arch_enable: true</span><br><span> fdpll0_arch_filter: 0</span><br><span> fdpll0_arch_lbypass: false</span><br><span> fdpll0_arch_ltime: No time-out, automatic lock</span><br><span> fdpll0_arch_ondemand: false</span><br><span style="color: hsl(0, 100%, 40%);">- fdpll0_arch_refclk: XOSC32K clock reference</span><br><span style="color: hsl(120, 100%, 40%);">+ fdpll0_arch_refclk: XOSC1 clock reference</span><br><span> fdpll0_arch_runstdby: false</span><br><span> fdpll0_arch_wuf: false</span><br><span> fdpll0_clock_dcofilter: 0</span><br><span style="color: hsl(0, 100%, 40%);">- fdpll0_clock_div: 0</span><br><span style="color: hsl(0, 100%, 40%);">- fdpll0_ldr: 1463</span><br><span style="color: hsl(0, 100%, 40%);">- fdpll0_ldrfrac: 13</span><br><span style="color: hsl(0, 100%, 40%);">- fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)</span><br><span style="color: hsl(120, 100%, 40%);">+ fdpll0_clock_div: 6</span><br><span style="color: hsl(120, 100%, 40%);">+ fdpll0_ldr: 59</span><br><span style="color: hsl(120, 100%, 40%);">+ fdpll0_ldrfrac: 0</span><br><span style="color: hsl(120, 100%, 40%);">+ fdpll0_ref_clock: Generic clock generator 11</span><br><span> fdpll1_arch_dcoen: false</span><br><span> fdpll1_arch_enable: false</span><br><span> fdpll1_arch_filter: 0</span><br><span>diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h</span><br><span>index 306d90e..8d10f38 100644</span><br><span>--- a/sysmoOCTSIM/config/hpl_gclk_config.h</span><br><span>+++ b/sysmoOCTSIM/config/hpl_gclk_config.h</span><br><span>@@ -25,7 +25,7 @@</span><br><span> // <i> This defines the clock source for generic clock generator 0</span><br><span> // <id> gclk_gen_0_oscillator</span><br><span> #ifndef CONF_GCLK_GEN_0_SOURCE</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_XOSC1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0</span><br><span> #endif</span><br><span> </span><br><span> // <q> Run in Standby</span><br><span>@@ -843,7 +843,7 @@</span><br><span> // <i> Indicates whether generic clock 11 configuration is enabled or not</span><br><span> // <id> enable_gclk_gen_11</span><br><span> #ifndef CONF_GCLK_GENERATOR_11_CONFIG</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GENERATOR_11_CONFIG 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GENERATOR_11_CONFIG 1</span><br><span> #endif</span><br><span> </span><br><span> // <h> Generic Clock Generator Control</span><br><span>@@ -860,7 +860,7 @@</span><br><span> // <i> This defines the clock source for generic clock generator 11</span><br><span> // <id> gclk_gen_11_oscillator</span><br><span> #ifndef CONF_GCLK_GEN_11_SOURCE</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1</span><br><span> #endif</span><br><span> </span><br><span> // <q> Run in Standby</span><br><span>@@ -902,7 +902,7 @@</span><br><span> // <i> Indicates whether Generic Clock Generator Enable is enabled or not</span><br><span> // <id> gclk_arch_gen_11_enable</span><br><span> #ifndef CONF_GCLK_GEN_11_GENEN</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GEN_11_GENEN 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GEN_11_GENEN 1</span><br><span> #endif</span><br><span> // </h></span><br><span> </span><br><span>@@ -910,7 +910,7 @@</span><br><span> //<o> Generic clock generator 11 division <0x0000-0xFFFF></span><br><span> // <id> gclk_gen_11_div</span><br><span> #ifndef CONF_GCLK_GEN_11_DIV</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GEN_11_DIV 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GEN_11_DIV 6</span><br><span> #endif</span><br><span> // </h></span><br><span> // </e></span><br><span>diff --git a/sysmoOCTSIM/config/hpl_oscctrl_config.h b/sysmoOCTSIM/config/hpl_oscctrl_config.h</span><br><span>index 11e4a24..d59ac43 100644</span><br><span>--- a/sysmoOCTSIM/config/hpl_oscctrl_config.h</span><br><span>+++ b/sysmoOCTSIM/config/hpl_oscctrl_config.h</span><br><span>@@ -382,7 +382,7 @@</span><br><span> // <i> Indicates whether configuration for FDPLL0 is enabled or not</span><br><span> // <id> enable_fdpll0</span><br><span> #ifndef CONF_FDPLL0_CONFIG</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL0_CONFIG 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL0_CONFIG 1</span><br><span> #endif</span><br><span> </span><br><span> // <y> Reference Clock Source</span><br><span>@@ -404,7 +404,7 @@</span><br><span> // <i> Select the clock source.</span><br><span> // <id> fdpll0_ref_clock</span><br><span> #ifndef CONF_FDPLL0_GCLK</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL0_GCLK GCLK_PCHCTRL_GEN_GCLK11_Val</span><br><span> #endif</span><br><span> </span><br><span> // <h> Digital Phase Locked Loop Control</span><br><span>@@ -412,7 +412,7 @@</span><br><span> // <i> Indicates whether Digital Phase Locked Loop is enabled or not</span><br><span> // <id> fdpll0_arch_enable</span><br><span> #ifndef CONF_FDPLL0_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL0_ENABLE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL0_ENABLE 1</span><br><span> #endif</span><br><span> </span><br><span> // <q> On Demand Control</span><br><span>@@ -432,19 +432,19 @@</span><br><span> // <o> Loop Divider Ratio Fractional Part <0x0-0x1F></span><br><span> // <id> fdpll0_ldrfrac</span><br><span> #ifndef CONF_FDPLL0_LDRFRAC</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL0_LDRFRAC 0xd</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL0_LDRFRAC 0x0</span><br><span> #endif</span><br><span> </span><br><span> // <o> Loop Divider Ratio Integer Part <0x0-0x1FFF></span><br><span> // <id> fdpll0_ldr</span><br><span> #ifndef CONF_FDPLL0_LDR</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL0_LDR 0x5b7</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL0_LDR 0x3b</span><br><span> #endif</span><br><span> </span><br><span> // <o> Clock Divider <0x0-0x7FF></span><br><span> // <id> fdpll0_clock_div</span><br><span> #ifndef CONF_FDPLL0_DIV</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL0_DIV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL0_DIV 0x6</span><br><span> #endif</span><br><span> </span><br><span> // <q> DCO Filter Enable</span><br><span>@@ -485,7 +485,7 @@</span><br><span> // <0x3=>XOSC1 clock reference</span><br><span> // <id> fdpll0_arch_refclk</span><br><span> #ifndef CONF_FDPLL0_REFCLK</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL0_REFCLK 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL0_REFCLK 0x3</span><br><span> #endif</span><br><span> </span><br><span> // <q> Wake Up Fast</span><br><span>diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>index 9a9c30f..8078e4b 100644</span><br><span>--- a/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>+++ b/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>@@ -9,7 +9,7 @@</span><br><span> * \brief CPU's Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_CPU_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_CPU_FREQUENCY 12000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_CPU_FREQUENCY 120000000</span><br><span> #endif</span><br><span> </span><br><span> // <y> USB Clock Source</span><br><span>diff --git a/sysmoOCTSIM/hpl/core/hpl_init.c b/sysmoOCTSIM/hpl/core/hpl_init.c</span><br><span>index be0db93..6f3dc20 100644</span><br><span>--- a/sysmoOCTSIM/hpl/core/hpl_init.c</span><br><span>+++ b/sysmoOCTSIM/hpl/core/hpl_init.c</span><br><span>@@ -42,10 +42,11 @@</span><br><span> #include <hal_cache.h></span><br><span> </span><br><span> /* Referenced GCLKs (out of 0~11), should be initialized firstly</span><br><span style="color: hsl(120, 100%, 40%);">+ * - GCLK 11 for FDPLL0</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define _GCLK_INIT_1ST 0x00000000</span><br><span style="color: hsl(120, 100%, 40%);">+#define _GCLK_INIT_1ST 0x00000800</span><br><span> /* Not referenced GCLKs, initialized last */</span><br><span style="color: hsl(0, 100%, 40%);">-#define _GCLK_INIT_LAST 0x00000FFF</span><br><span style="color: hsl(120, 100%, 40%);">+#define _GCLK_INIT_LAST 0x000007FF</span><br><span> </span><br><span> /**</span><br><span> * \brief Initialize the hardware abstraction layer</span><br><span></span><br></pre><p>To view, visit <a href="https://gerrit.osmocom.org/12797">change 12797</a>. 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<div style="display:none"> Gerrit-Project: osmo-ccid-firmware </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I642e724ec56a376addf21cc58ecd2ef1b40bd116 </div>
<div style="display:none"> Gerrit-Change-Number: 12797 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Kévin Redon <kredon@sysmocom.de> </div>
<div style="display:none"> Gerrit-Reviewer: Harald Welte <laforge@gnumonks.org> </div>
<div style="display:none"> Gerrit-Reviewer: Jenkins Builder (1000002) </div>