<p>Kévin Redon has uploaded this change for <strong>review</strong>.</p><p><a href="https://gerrit.osmocom.org/12799">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">set DPLL1 to 100 MHz<br><br>use GCLK11 to bring external crystal oscillator XOSC1 from 12 MHz<br>to 2MHz<br>use DPLL1 to multiply 2 MHz to 100 MHz.<br>the division is first needed because the DPLL0 maximum input<br>frequency is 3.2 MHz<br>100 MHz is the maximum input frequency for the SERCOM peripherals<br><br>Change-Id: I0482c39cc0db999904c585d21738dbce57ca3b55<br>---<br>M sysmoOCTSIM/atmel_start_config.atstart<br>M sysmoOCTSIM/config/hpl_gclk_config.h<br>M sysmoOCTSIM/config/hpl_oscctrl_config.h<br>M sysmoOCTSIM/hpl/core/hpl_init.c<br>4 files changed, 22 insertions(+), 21 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://gerrit.osmocom.org:29418/osmo-ccid-firmware refs/changes/99/12799/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>index 5e27536..3899d79 100644</span><br><span>--- a/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>+++ b/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>@@ -647,7 +647,7 @@</span><br><span> enable_gclk_gen_1: true</span><br><span> enable_gclk_gen_10: false</span><br><span> enable_gclk_gen_11: true</span><br><span style="color: hsl(0, 100%, 40%);">- enable_gclk_gen_2: false</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_2: true</span><br><span> enable_gclk_gen_3: true</span><br><span> enable_gclk_gen_4: false</span><br><span> enable_gclk_gen_5: false</span><br><span>@@ -675,7 +675,7 @@</span><br><span> gclk_arch_gen_1_oe: false</span><br><span> gclk_arch_gen_1_oov: false</span><br><span> gclk_arch_gen_1_runstdby: false</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_arch_gen_2_enable: false</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_arch_gen_2_enable: true</span><br><span> gclk_arch_gen_2_idc: false</span><br><span> gclk_arch_gen_2_oe: false</span><br><span> gclk_arch_gen_2_oov: false</span><br><span>@@ -728,8 +728,8 @@</span><br><span> gclk_gen_1_div_sel: false</span><br><span> gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M)</span><br><span> gclk_gen_2_div: 1</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_gen_2_div_sel: true</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC0)</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_gen_2_div_sel: false</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_gen_2_oscillator: Digital Phase Locked Loop (DPLL1)</span><br><span> gclk_gen_3_div: 1</span><br><span> gclk_gen_3_div_sel: false</span><br><span> gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K)</span><br><span>@@ -830,7 +830,7 @@</span><br><span> dfll_ref_clock: Generic clock generator 3</span><br><span> enable_dfll: true</span><br><span> enable_fdpll0: true</span><br><span style="color: hsl(0, 100%, 40%);">- enable_fdpll1: false</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_fdpll1: true</span><br><span> enable_xosc0: false</span><br><span> enable_xosc1: true</span><br><span> fdpll0_arch_dcoen: false</span><br><span>@@ -848,19 +848,19 @@</span><br><span> fdpll0_ldrfrac: 0</span><br><span> fdpll0_ref_clock: Generic clock generator 11</span><br><span> fdpll1_arch_dcoen: false</span><br><span style="color: hsl(0, 100%, 40%);">- fdpll1_arch_enable: false</span><br><span style="color: hsl(120, 100%, 40%);">+ fdpll1_arch_enable: true</span><br><span> fdpll1_arch_filter: 0</span><br><span> fdpll1_arch_lbypass: false</span><br><span> fdpll1_arch_ltime: No time-out, automatic lock</span><br><span> fdpll1_arch_ondemand: false</span><br><span style="color: hsl(0, 100%, 40%);">- fdpll1_arch_refclk: XOSC32K clock reference</span><br><span style="color: hsl(120, 100%, 40%);">+ fdpll1_arch_refclk: XOSC1 clock reference</span><br><span> fdpll1_arch_runstdby: false</span><br><span> fdpll1_arch_wuf: false</span><br><span> fdpll1_clock_dcofilter: 0</span><br><span style="color: hsl(0, 100%, 40%);">- fdpll1_clock_div: 0</span><br><span style="color: hsl(0, 100%, 40%);">- fdpll1_ldr: 1463</span><br><span style="color: hsl(0, 100%, 40%);">- fdpll1_ldrfrac: 13</span><br><span style="color: hsl(0, 100%, 40%);">- fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K)</span><br><span style="color: hsl(120, 100%, 40%);">+ fdpll1_clock_div: 6</span><br><span style="color: hsl(120, 100%, 40%);">+ fdpll1_ldr: 49</span><br><span style="color: hsl(120, 100%, 40%);">+ fdpll1_ldrfrac: 0</span><br><span style="color: hsl(120, 100%, 40%);">+ fdpll1_ref_clock: Generic clock generator 11</span><br><span> xosc0_arch_cfden: false</span><br><span> xosc0_arch_enable: false</span><br><span> xosc0_arch_enalc: false</span><br><span>diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h</span><br><span>index fbaa9b7..398a617 100644</span><br><span>--- a/sysmoOCTSIM/config/hpl_gclk_config.h</span><br><span>+++ b/sysmoOCTSIM/config/hpl_gclk_config.h</span><br><span>@@ -159,7 +159,7 @@</span><br><span> // <i> Indicates whether generic clock 2 configuration is enabled or not</span><br><span> // <id> enable_gclk_gen_2</span><br><span> #ifndef CONF_GCLK_GENERATOR_2_CONFIG</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GENERATOR_2_CONFIG 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GENERATOR_2_CONFIG 1</span><br><span> #endif</span><br><span> </span><br><span> // <h> Generic Clock Generator Control</span><br><span>@@ -176,7 +176,7 @@</span><br><span> // <i> This defines the clock source for generic clock generator 2</span><br><span> // <id> gclk_gen_2_oscillator</span><br><span> #ifndef CONF_GCLK_GEN_2_SOURCE</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_DPLL1</span><br><span> #endif</span><br><span> </span><br><span> // <q> Run in Standby</span><br><span>@@ -190,7 +190,7 @@</span><br><span> // <i> Indicates whether Divide Selection is enabled or not</span><br><span> //<id> gclk_gen_2_div_sel</span><br><span> #ifndef CONF_GCLK_GEN_2_DIVSEL</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GEN_2_DIVSEL 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GEN_2_DIVSEL 0</span><br><span> #endif</span><br><span> </span><br><span> // <q> Output Enable</span><br><span>@@ -218,7 +218,7 @@</span><br><span> // <i> Indicates whether Generic Clock Generator Enable is enabled or not</span><br><span> // <id> gclk_arch_gen_2_enable</span><br><span> #ifndef CONF_GCLK_GEN_2_GENEN</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GEN_2_GENEN 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GEN_2_GENEN 1</span><br><span> #endif</span><br><span> // </h></span><br><span> </span><br><span>diff --git a/sysmoOCTSIM/config/hpl_oscctrl_config.h b/sysmoOCTSIM/config/hpl_oscctrl_config.h</span><br><span>index 6b3cc19..06ee571 100644</span><br><span>--- a/sysmoOCTSIM/config/hpl_oscctrl_config.h</span><br><span>+++ b/sysmoOCTSIM/config/hpl_oscctrl_config.h</span><br><span>@@ -529,7 +529,7 @@</span><br><span> // <i> Select the clock source.</span><br><span> // <id> fdpll1_ref_clock</span><br><span> #ifndef CONF_FDPLL1_GCLK</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL1_GCLK GCLK_PCHCTRL_GEN_GCLK11_Val</span><br><span> #endif</span><br><span> </span><br><span> // <h> Digital Phase Locked Loop Control</span><br><span>@@ -537,7 +537,7 @@</span><br><span> // <i> Indicates whether Digital Phase Locked Loop is enabled or not</span><br><span> // <id> fdpll1_arch_enable</span><br><span> #ifndef CONF_FDPLL1_ENABLE</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL1_ENABLE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL1_ENABLE 1</span><br><span> #endif</span><br><span> </span><br><span> // <q> On Demand Control</span><br><span>@@ -557,19 +557,19 @@</span><br><span> // <o> Loop Divider Ratio Fractional Part <0x0-0x1F></span><br><span> // <id> fdpll1_ldrfrac</span><br><span> #ifndef CONF_FDPLL1_LDRFRAC</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL1_LDRFRAC 0xd</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL1_LDRFRAC 0x0</span><br><span> #endif</span><br><span> </span><br><span> // <o> Loop Divider Ratio Integer Part <0x0-0x1FFF></span><br><span> // <id> fdpll1_ldr</span><br><span> #ifndef CONF_FDPLL1_LDR</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL1_LDR 0x5b7</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL1_LDR 0x31</span><br><span> #endif</span><br><span> </span><br><span> // <o> Clock Divider <0x0-0x7FF></span><br><span> // <id> fdpll1_clock_div</span><br><span> #ifndef CONF_FDPLL1_DIV</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL1_DIV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL1_DIV 0x6</span><br><span> #endif</span><br><span> </span><br><span> // <q> DCO Filter Enable</span><br><span>@@ -610,7 +610,7 @@</span><br><span> // <0x3=>XOSC1 clock reference</span><br><span> // <id> fdpll1_arch_refclk</span><br><span> #ifndef CONF_FDPLL1_REFCLK</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_FDPLL1_REFCLK 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_FDPLL1_REFCLK 0x3</span><br><span> #endif</span><br><span> </span><br><span> // <q> Wake Up Fast</span><br><span>diff --git a/sysmoOCTSIM/hpl/core/hpl_init.c b/sysmoOCTSIM/hpl/core/hpl_init.c</span><br><span>index 6f3dc20..bb8425c 100644</span><br><span>--- a/sysmoOCTSIM/hpl/core/hpl_init.c</span><br><span>+++ b/sysmoOCTSIM/hpl/core/hpl_init.c</span><br><span>@@ -42,6 +42,7 @@</span><br><span> #include <hal_cache.h></span><br><span> </span><br><span> /* Referenced GCLKs (out of 0~11), should be initialized firstly</span><br><span style="color: hsl(120, 100%, 40%);">+ * - GCLK 11 for FDPLL1</span><br><span> * - GCLK 11 for FDPLL0</span><br><span> */</span><br><span> #define _GCLK_INIT_1ST 0x00000800</span><br><span></span><br></pre><p>To view, visit <a href="https://gerrit.osmocom.org/12799">change 12799</a>. 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<div style="display:none"> Gerrit-Project: osmo-ccid-firmware </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0482c39cc0db999904c585d21738dbce57ca3b55 </div>
<div style="display:none"> Gerrit-Change-Number: 12799 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kévin Redon <kredon@sysmocom.de> </div>