This is merely a historical archive of years 2008-2021, before the migration to mailman3.
A maintained and still updated list archive can be found at https://lists.osmocom.org/hyperkitty/list/gerrit-log@lists.osmocom.org/.
laforge gerrit-no-reply at lists.osmocom.orglaforge has submitted this change. ( https://gerrit.osmocom.org/c/osmo-ccid-firmware/+/25612 )
Change subject: sychronize atmel start config with the headers
......................................................................
sychronize atmel start config with the headers
Change-Id: Ib21847f6726920e3f97600a347f2a16f957a5e8e
---
M sysmoOCTSIM/atmel_start_config.atstart
M sysmoOCTSIM/config/hpl_oscctrl_config.h
M sysmoOCTSIM/config/hpl_rtc_config.h
M sysmoOCTSIM/config/peripheral_clk_config.h
M sysmoOCTSIM/hpl/core/hpl_init.c
5 files changed, 105 insertions(+), 56 deletions(-)
Approvals:
Jenkins Builder: Verified
laforge: Looks good to me, approved
diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart
index 73ad9bd..92ef0bb 100644
--- a/sysmoOCTSIM/atmel_start_config.atstart
+++ b/sysmoOCTSIM/atmel_start_config.atstart
@@ -2,12 +2,17 @@
name: sysmoOCTSIM
versions:
api: '1.0'
- backend: 1.5.122
- commit: 820baecf7dd115d94b0d42ee3b0b9d6ba2da7113
- content: 1.0.1507
- content_pack_name: acme-packs-all
+ backend: 1.8.580
+ commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c
+ content: unknown
+ content_pack_name: unknown
format: '2'
- frontend: 1.5.1877
+ frontend: 1.8.580
+ packs_version_avr8: 1.0.1463
+ packs_version_qtouch: unknown
+ packs_version_sam: 1.0.1726
+ version_backend: 1.8.580
+ version_frontend: ''
board:
identifier: CustomBoard
device: SAME54N19A-AF
@@ -658,18 +663,46 @@
functionality: System
api: HAL:HPL:GCLK
configuration:
+ $input: 100000000
+ $input_id: Digital Phase Locked Loop (DPLL1)
+ RESERVED_InputFreq: 100000000
+ RESERVED_InputFreq_id: Digital Phase Locked Loop (DPLL1)
+ _$freq_output_Generic clock generator 0: 120000000
+ _$freq_output_Generic clock generator 1: 48000000
+ _$freq_output_Generic clock generator 10: 12000000
+ _$freq_output_Generic clock generator 11: 2000000
+ _$freq_output_Generic clock generator 2: 12500000
+ _$freq_output_Generic clock generator 3: 32768
+ _$freq_output_Generic clock generator 4: 50000000
+ _$freq_output_Generic clock generator 5: 20000000
+ _$freq_output_Generic clock generator 6: 7058823.529411765
+ _$freq_output_Generic clock generator 7: 12000000
+ _$freq_output_Generic clock generator 8: 12000000
+ _$freq_output_Generic clock generator 9: 12000000
enable_gclk_gen_0: true
+ enable_gclk_gen_0__externalclock: 1000000
enable_gclk_gen_1: true
enable_gclk_gen_10: false
- enable_gclk_gen_11: true
+ enable_gclk_gen_10__externalclock: 1000000
+ enable_gclk_gen_11: false
+ enable_gclk_gen_11__externalclock: 1000000
+ enable_gclk_gen_1__externalclock: 1000000
enable_gclk_gen_2: true
+ enable_gclk_gen_2__externalclock: 1000000
enable_gclk_gen_3: true
+ enable_gclk_gen_3__externalclock: 1000000
enable_gclk_gen_4: true
+ enable_gclk_gen_4__externalclock: 1000000
enable_gclk_gen_5: true
+ enable_gclk_gen_5__externalclock: 1000000
enable_gclk_gen_6: true
+ enable_gclk_gen_6__externalclock: 1000000
enable_gclk_gen_7: false
+ enable_gclk_gen_7__externalclock: 1000000
enable_gclk_gen_8: false
+ enable_gclk_gen_8__externalclock: 1000000
enable_gclk_gen_9: false
+ enable_gclk_gen_9__externalclock: 1000000
gclk_arch_gen_0_enable: true
gclk_arch_gen_0_idc: false
gclk_arch_gen_0_oe: false
@@ -680,7 +713,7 @@
gclk_arch_gen_10_oe: false
gclk_arch_gen_10_oov: false
gclk_arch_gen_10_runstdby: false
- gclk_arch_gen_11_enable: true
+ gclk_arch_gen_11_enable: false
gclk_arch_gen_11_idc: false
gclk_arch_gen_11_oe: false
gclk_arch_gen_11_oov: false
@@ -776,6 +809,11 @@
functionality: System
api: HAL:HPL:MCLK
configuration:
+ $input: 120000000
+ $input_id: Generic clock generator 0
+ RESERVED_InputFreq: 120000000
+ RESERVED_InputFreq_id: Generic clock generator 0
+ _$freq_output_CPU: 120000000
cpu_clock_source: Generic clock generator 0
cpu_div: '1'
enable_cpu_clock: true
@@ -799,6 +837,11 @@
functionality: System
api: HAL:HPL:OSC32KCTRL
configuration:
+ $input: 32768
+ $input_id: 32kHz External Crystal Oscillator (XOSC32K)
+ RESERVED_InputFreq: 32768
+ RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K)
+ _$freq_output_RTC source: 32768
enable_osculp32k: true
enable_rtc_source: false
enable_xosc32k: true
@@ -809,11 +852,11 @@
xosc32k_arch_cfden: false
xosc32k_arch_cfdeo: false
xosc32k_arch_cgm: Standard mode
- xosc32k_arch_en1k: false
+ xosc32k_arch_en1k: true
xosc32k_arch_en32k: true
xosc32k_arch_enable: true
- xosc32k_arch_ondemand: true
- xosc32k_arch_runstdby: false
+ xosc32k_arch_ondemand: false
+ xosc32k_arch_runstdby: true
xosc32k_arch_startup: 62592us
xosc32k_arch_swben: false
xosc32k_arch_xtalen: true
@@ -827,19 +870,28 @@
functionality: System
api: HAL:HPL:OSCCTRL
configuration:
- dfll_arch_bplckc: false
+ $input: 32768
+ $input_id: Generic clock generator 3
+ RESERVED_InputFreq: 32768
+ RESERVED_InputFreq_id: Generic clock generator 3
+ _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
+ _$freq_output_Digital Phase Locked Loop (DPLL0): 120000000
+ _$freq_output_Digital Phase Locked Loop (DPLL1): 100000000
+ _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000
+ _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000
+ dfll_arch_bplckc: true
dfll_arch_calibration: false
dfll_arch_ccdis: true
dfll_arch_coarse: 31
dfll_arch_cstep: 1
dfll_arch_enable: true
dfll_arch_fine: 128
- dfll_arch_fstep: 1
+ dfll_arch_fstep: 10
dfll_arch_llaw: false
dfll_arch_ondemand: false
dfll_arch_qldis: false
dfll_arch_runstdby: false
- dfll_arch_stable: false
+ dfll_arch_stable: true
dfll_arch_usbcrm: true
dfll_arch_waitlock: false
dfll_mode: Closed Loop Mode
@@ -863,7 +915,7 @@
fdpll0_clock_div: 2
fdpll0_ldr: 59
fdpll0_ldrfrac: 0
- fdpll0_ref_clock: Generic clock generator 11
+ fdpll0_ref_clock: External Crystal Oscillator 8-48MHz (XOSC1)
fdpll1_arch_dcoen: false
fdpll1_arch_enable: true
fdpll1_arch_filter: 0
@@ -877,7 +929,7 @@
fdpll1_clock_div: 2
fdpll1_ldr: 49
fdpll1_ldrfrac: 0
- fdpll1_ref_clock: Generic clock generator 11
+ fdpll1_ref_clock: External Crystal Oscillator 8-48MHz (XOSC1)
xosc0_arch_cfden: false
xosc0_arch_enable: false
xosc0_arch_enalc: false
@@ -969,7 +1021,7 @@
api: HAL:Driver:Calendar
configuration:
rtc_arch_init_reset: true
- rtc_arch_prescaler: Peripheral clock divided by 1
+ rtc_arch_prescaler: Peripheral clock divided by 1024
rtc_cmpeo0: false
rtc_cmpeo1: false
rtc_event_control: false
@@ -1037,11 +1089,11 @@
usart_gtime: 2-bit times
usart_inack: NACK is transmitted when a parity error is received.
usart_inverse_enabled: false
- usart_iso7816_type: T=0
+ usart_iso7816_type: T=1
usart_maxiter: 7
usart_parity: Even parity
usart_rx_enable: true
- usart_stop_bit: One stop bit
+ usart_stop_bit: Two stop bits
usart_tx_enable: true
optional_signals: []
variant:
@@ -1084,11 +1136,11 @@
usart_gtime: 2-bit times
usart_inack: NACK is transmitted when a parity error is received.
usart_inverse_enabled: false
- usart_iso7816_type: T=0
+ usart_iso7816_type: T=1
usart_maxiter: 7
usart_parity: Even parity
usart_rx_enable: true
- usart_stop_bit: One stop bit
+ usart_stop_bit: Two stop bits
usart_tx_enable: true
optional_signals: []
variant:
@@ -1131,11 +1183,11 @@
usart_gtime: 2-bit times
usart_inack: NACK is transmitted when a parity error is received.
usart_inverse_enabled: false
- usart_iso7816_type: T=0
+ usart_iso7816_type: T=1
usart_maxiter: 7
usart_parity: Even parity
usart_rx_enable: true
- usart_stop_bit: One stop bit
+ usart_stop_bit: Two stop bits
usart_tx_enable: true
optional_signals: []
variant:
@@ -1178,11 +1230,11 @@
usart_gtime: 2-bit times
usart_inack: NACK is transmitted when a parity error is received.
usart_inverse_enabled: false
- usart_iso7816_type: T=0
+ usart_iso7816_type: T=1
usart_maxiter: 7
usart_parity: Even parity
usart_rx_enable: true
- usart_stop_bit: One stop bit
+ usart_stop_bit: Two stop bits
usart_tx_enable: true
optional_signals: []
variant:
@@ -1225,11 +1277,11 @@
usart_gtime: 2-bit times
usart_inack: NACK is transmitted when a parity error is received.
usart_inverse_enabled: false
- usart_iso7816_type: T=0
+ usart_iso7816_type: T=1
usart_maxiter: 7
usart_parity: Even parity
usart_rx_enable: true
- usart_stop_bit: One stop bit
+ usart_stop_bit: Two stop bits
usart_tx_enable: true
optional_signals: []
variant:
@@ -1272,11 +1324,11 @@
usart_gtime: 2-bit times
usart_inack: NACK is transmitted when a parity error is received.
usart_inverse_enabled: false
- usart_iso7816_type: T=0
+ usart_iso7816_type: T=1
usart_maxiter: 7
usart_parity: Even parity
usart_rx_enable: true
- usart_stop_bit: One stop bit
+ usart_stop_bit: Two stop bits
usart_tx_enable: true
optional_signals: []
variant:
@@ -1319,11 +1371,11 @@
usart_gtime: 2-bit times
usart_inack: NACK is transmitted when a parity error is received.
usart_inverse_enabled: false
- usart_iso7816_type: T=0
+ usart_iso7816_type: T=1
usart_maxiter: 7
usart_parity: Even parity
usart_rx_enable: true
- usart_stop_bit: One stop bit
+ usart_stop_bit: Two stop bits
usart_tx_enable: true
optional_signals: []
variant:
@@ -1416,9 +1468,9 @@
usb_ep5_I_CACHE: No cache
usb_ep6_I_CACHE: No cache
usb_ep7_I_CACHE: No cache
- usbd_arch_max_ep_n: 2 (EP 0x82 or 0x02)
+ usbd_arch_max_ep_n: 4 (EP 0x84 or 0x04)
usbd_arch_speed: Full speed
- usbd_num_ep_sp: 4 (EP0 + 3 endpoints)
+ usbd_num_ep_sp: 7 (EP0 + 6 endpoints)
optional_signals: []
variant:
specification: default
@@ -1664,3 +1716,4 @@
user_label: SDA2
configuration: null
toolchain_options: []
+static_files: []
diff --git a/sysmoOCTSIM/config/hpl_oscctrl_config.h b/sysmoOCTSIM/config/hpl_oscctrl_config.h
index a7bc9b9..d27c869 100644
--- a/sysmoOCTSIM/config/hpl_oscctrl_config.h
+++ b/sysmoOCTSIM/config/hpl_oscctrl_config.h
@@ -404,7 +404,6 @@
// <i> Select the clock source.
// <id> fdpll0_ref_clock
#ifndef CONF_FDPLL0_GCLK
-// directly use XOSC1 as clock input (no need to use an additional GCLK)
#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC1
#endif
@@ -431,23 +430,24 @@
#endif
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
+// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
// <id> fdpll0_ldrfrac
#ifndef CONF_FDPLL0_LDRFRAC
#define CONF_FDPLL0_LDRFRAC 0x0
#endif
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
+// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
// <id> fdpll0_ldr
#ifndef CONF_FDPLL0_LDR
-// 2 MHz input clock * ( <59> + 1 = 60 ) = 120 MHz output clock
-#define CONF_FDPLL0_LDR 59
+#define CONF_FDPLL0_LDR 0x3b
#endif
// <o> Clock Divider <0x0-0x7FF>
+// <i> This Clock divider is only for XOSC clock input to DPLL
// <id> fdpll0_clock_div
#ifndef CONF_FDPLL0_DIV
-// XOSC1 = 12 MHz, divide by 2 * ( <2> + 1 ) = 6 to have a 2 MHz clock input (maximum is 3.4 MHz)
-#define CONF_FDPLL0_DIV 2
+#define CONF_FDPLL0_DIV 0x2
#endif
// <q> DCO Filter Enable
@@ -488,7 +488,6 @@
// <0x3=>XOSC1 clock reference
// <id> fdpll0_arch_refclk
#ifndef CONF_FDPLL0_REFCLK
-// XOSC1 is used as input signal, thus also use it as reference
#define CONF_FDPLL0_REFCLK 0x3
#endif
@@ -533,7 +532,6 @@
// <i> Select the clock source.
// <id> fdpll1_ref_clock
#ifndef CONF_FDPLL1_GCLK
-// directly use XOSC1 as clock input (no need to use an additional GCLK)
#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC1
#endif
@@ -560,23 +558,24 @@
#endif
// <o> Loop Divider Ratio Fractional Part <0x0-0x1F>
+// <i> Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
// <id> fdpll1_ldrfrac
#ifndef CONF_FDPLL1_LDRFRAC
#define CONF_FDPLL1_LDRFRAC 0x0
#endif
// <o> Loop Divider Ratio Integer Part <0x0-0x1FFF>
+// <i> Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register
// <id> fdpll1_ldr
#ifndef CONF_FDPLL1_LDR
-// 2 MHz input clock * ( <49> + 1 = 50 ) = 100 MHz output clock
-#define CONF_FDPLL1_LDR 49
+#define CONF_FDPLL1_LDR 0x31
#endif
// <o> Clock Divider <0x0-0x7FF>
+// <i> This Clock divider is only for XOSC clock input to DPLL
// <id> fdpll1_clock_div
#ifndef CONF_FDPLL1_DIV
-// XOSC1 = 12 MHz, divide by 2 * ( <2> + 1 ) = 6 to have a 2 MHz clock input (maximum is 3.4 MHz)
-#define CONF_FDPLL1_DIV 2
+#define CONF_FDPLL1_DIV 0x2
#endif
// <q> DCO Filter Enable
@@ -617,7 +616,6 @@
// <0x3=>XOSC1 clock reference
// <id> fdpll1_arch_refclk
#ifndef CONF_FDPLL1_REFCLK
-// XOSC1 is used as input signal, thus also use it as reference
#define CONF_FDPLL1_REFCLK 0x3
#endif
diff --git a/sysmoOCTSIM/config/hpl_rtc_config.h b/sysmoOCTSIM/config/hpl_rtc_config.h
index 3961d40..0e795ba 100644
--- a/sysmoOCTSIM/config/hpl_rtc_config.h
+++ b/sysmoOCTSIM/config/hpl_rtc_config.h
@@ -35,7 +35,7 @@
// <id> rtc_arch_prescaler
#ifndef CONF_RTC_PRESCALER
-#define CONF_RTC_PRESCALER 0xB
+#define CONF_RTC_PRESCALER 0xb
#endif
diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h
index 6d8ba10..205e33e 100644
--- a/sysmoOCTSIM/config/peripheral_clk_config.h
+++ b/sysmoOCTSIM/config/peripheral_clk_config.h
@@ -97,7 +97,7 @@
* \brief SERCOM0's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 500000
+#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 12500000
#endif
/**
@@ -177,7 +177,7 @@
* \brief SERCOM1's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 500000
+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 12500000
#endif
/**
@@ -257,7 +257,7 @@
* \brief SERCOM2's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 500000
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 12500000
#endif
/**
@@ -337,7 +337,7 @@
* \brief SERCOM3's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 500000
+#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 12500000
#endif
/**
@@ -417,7 +417,7 @@
* \brief SERCOM4's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 500000
+#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 12500000
#endif
/**
@@ -497,7 +497,7 @@
* \brief SERCOM5's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 500000
+#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 12500000
#endif
/**
@@ -577,7 +577,7 @@
* \brief SERCOM6's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM6_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 500000
+#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 12500000
#endif
/**
diff --git a/sysmoOCTSIM/hpl/core/hpl_init.c b/sysmoOCTSIM/hpl/core/hpl_init.c
index bb8425c..be0db93 100644
--- a/sysmoOCTSIM/hpl/core/hpl_init.c
+++ b/sysmoOCTSIM/hpl/core/hpl_init.c
@@ -42,12 +42,10 @@
#include <hal_cache.h>
/* Referenced GCLKs (out of 0~11), should be initialized firstly
- * - GCLK 11 for FDPLL1
- * - GCLK 11 for FDPLL0
*/
-#define _GCLK_INIT_1ST 0x00000800
+#define _GCLK_INIT_1ST 0x00000000
/* Not referenced GCLKs, initialized last */
-#define _GCLK_INIT_LAST 0x000007FF
+#define _GCLK_INIT_LAST 0x00000FFF
/**
* \brief Initialize the hardware abstraction layer
--
To view, visit https://gerrit.osmocom.org/c/osmo-ccid-firmware/+/25612
To unsubscribe, or for help writing mail filters, visit https://gerrit.osmocom.org/settings
Gerrit-Project: osmo-ccid-firmware
Gerrit-Branch: master
Gerrit-Change-Id: Ib21847f6726920e3f97600a347f2a16f957a5e8e
Gerrit-Change-Number: 25612
Gerrit-PatchSet: 2
Gerrit-Owner: Hoernchen <ewild at sysmocom.de>
Gerrit-Reviewer: Jenkins Builder
Gerrit-Reviewer: laforge <laforge at osmocom.org>
Gerrit-MessageType: merged
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.osmocom.org/pipermail/gerrit-log/attachments/20211008/ebfeb803/attachment.htm>