Change in osmo-ccid-firmware[master]: use XOSC1 directly for DPLL1

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Harald Welte gerrit-no-reply at lists.osmocom.org
Thu Feb 7 15:28:28 UTC 2019


Harald Welte has submitted this change and it was merged. ( https://gerrit.osmocom.org/12800 )

Change subject: use XOSC1 directly for DPLL1
......................................................................

use XOSC1 directly for DPLL1

DPLL1 can take directly XOSC1 as input and divide it to 2 MHz.
thus the intermediate GCLK11 is not needed.
we now also completely de-configure GCLK11
this configuration is not supported by Atmel START since it does
not know about the division and thinks the input frequency
exceeds the maximum
GCLK2 is also disabled for now because it is not used

Change-Id: Icee7f5a13019c47cebc23376cabb18cb31178ece
---
M sysmoOCTSIM/config/hpl_gclk_config.h
M sysmoOCTSIM/config/hpl_oscctrl_config.h
2 files changed, 4 insertions(+), 4 deletions(-)

Approvals:
  Jenkins Builder: Verified
  Harald Welte: Looks good to me, approved



diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h
index 398a617..0ad8ead 100644
--- a/sysmoOCTSIM/config/hpl_gclk_config.h
+++ b/sysmoOCTSIM/config/hpl_gclk_config.h
@@ -218,7 +218,7 @@
 // <i> Indicates whether Generic Clock Generator Enable is enabled or not
 // <id> gclk_arch_gen_2_enable
 #ifndef CONF_GCLK_GEN_2_GENEN
-#define CONF_GCLK_GEN_2_GENEN 1
+#define CONF_GCLK_GEN_2_GENEN 0
 #endif
 // </h>
 
@@ -843,7 +843,7 @@
 // <i> Indicates whether generic clock 11 configuration is enabled or not
 // <id> enable_gclk_gen_11
 #ifndef CONF_GCLK_GENERATOR_11_CONFIG
-#define CONF_GCLK_GENERATOR_11_CONFIG 1
+#define CONF_GCLK_GENERATOR_11_CONFIG 0
 #endif
 
 // <h> Generic Clock Generator Control
diff --git a/sysmoOCTSIM/config/hpl_oscctrl_config.h b/sysmoOCTSIM/config/hpl_oscctrl_config.h
index 06ee571..0676cb5 100644
--- a/sysmoOCTSIM/config/hpl_oscctrl_config.h
+++ b/sysmoOCTSIM/config/hpl_oscctrl_config.h
@@ -507,7 +507,7 @@
 // <i> Indicates whether configuration for FDPLL1 is enabled or not
 // <id> enable_fdpll1
 #ifndef CONF_FDPLL1_CONFIG
-#define CONF_FDPLL1_CONFIG 0
+#define CONF_FDPLL1_CONFIG 1
 #endif
 
 // <y> Reference Clock Source
@@ -529,7 +529,7 @@
 // <i> Select the clock source.
 // <id> fdpll1_ref_clock
 #ifndef CONF_FDPLL1_GCLK
-#define CONF_FDPLL1_GCLK GCLK_PCHCTRL_GEN_GCLK11_Val
+#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC1
 #endif
 
 // <h> Digital Phase Locked Loop Control

-- 
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Gerrit-Project: osmo-ccid-firmware
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Icee7f5a13019c47cebc23376cabb18cb31178ece
Gerrit-Change-Number: 12800
Gerrit-PatchSet: 2
Gerrit-Owner: Kévin Redon <kredon at sysmocom.de>
Gerrit-Reviewer: Harald Welte <laforge at gnumonks.org>
Gerrit-Reviewer: Jenkins Builder (1000002)
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