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Harald Welte gerrit-no-reply at lists.osmocom.orgHarald Welte has submitted this change and it was merged. ( https://gerrit.osmocom.org/12797 ) Change subject: switch CPU clock to 120 MHz ...................................................................... switch CPU clock to 120 MHz use GCLK11 to bring external crystal oscillator XOSC1 from 12 MHz to 2MHz use DPLL0 to multiply 2 MHz to 120 MHz. the division is first needed because the DPLL0 maximum input frequency is 3.2 MHz Change-Id: I642e724ec56a376addf21cc58ecd2ef1b40bd116 --- M sysmoOCTSIM/atmel_start_config.atstart M sysmoOCTSIM/config/hpl_gclk_config.h M sysmoOCTSIM/config/hpl_oscctrl_config.h M sysmoOCTSIM/config/peripheral_clk_config.h M sysmoOCTSIM/hpl/core/hpl_init.c 5 files changed, 28 insertions(+), 27 deletions(-) Approvals: Jenkins Builder: Verified Harald Welte: Looks good to me, approved diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart index 385c890..5e27536 100644 --- a/sysmoOCTSIM/atmel_start_config.atstart +++ b/sysmoOCTSIM/atmel_start_config.atstart @@ -646,7 +646,7 @@ enable_gclk_gen_0: true enable_gclk_gen_1: true enable_gclk_gen_10: false - enable_gclk_gen_11: false + enable_gclk_gen_11: true enable_gclk_gen_2: false enable_gclk_gen_3: true enable_gclk_gen_4: false @@ -665,7 +665,7 @@ gclk_arch_gen_10_oe: false gclk_arch_gen_10_oov: false gclk_arch_gen_10_runstdby: false - gclk_arch_gen_11_enable: false + gclk_arch_gen_11_enable: true gclk_arch_gen_11_idc: false gclk_arch_gen_11_oe: false gclk_arch_gen_11_oov: false @@ -717,13 +717,13 @@ gclk_arch_gen_9_runstdby: false gclk_gen_0_div: 1 gclk_gen_0_div_sel: false - gclk_gen_0_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0) gclk_gen_10_div: 1 gclk_gen_10_div_sel: false gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC0) - gclk_gen_11_div: 1 + gclk_gen_11_div: 6 gclk_gen_11_div_sel: false - gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC0) + gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) gclk_gen_1_div: 1 gclk_gen_1_div_sel: false gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) @@ -829,24 +829,24 @@ dfll_mul: 48000 dfll_ref_clock: Generic clock generator 3 enable_dfll: true - enable_fdpll0: false + enable_fdpll0: true enable_fdpll1: false enable_xosc0: false enable_xosc1: true fdpll0_arch_dcoen: false - fdpll0_arch_enable: false + fdpll0_arch_enable: true fdpll0_arch_filter: 0 fdpll0_arch_lbypass: false fdpll0_arch_ltime: No time-out, automatic lock fdpll0_arch_ondemand: false - fdpll0_arch_refclk: XOSC32K clock reference + fdpll0_arch_refclk: XOSC1 clock reference fdpll0_arch_runstdby: false fdpll0_arch_wuf: false fdpll0_clock_dcofilter: 0 - fdpll0_clock_div: 0 - fdpll0_ldr: 1463 - fdpll0_ldrfrac: 13 - fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + fdpll0_clock_div: 6 + fdpll0_ldr: 59 + fdpll0_ldrfrac: 0 + fdpll0_ref_clock: Generic clock generator 11 fdpll1_arch_dcoen: false fdpll1_arch_enable: false fdpll1_arch_filter: 0 diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h index 306d90e..8d10f38 100644 --- a/sysmoOCTSIM/config/hpl_gclk_config.h +++ b/sysmoOCTSIM/config/hpl_gclk_config.h @@ -25,7 +25,7 @@ // <i> This defines the clock source for generic clock generator 0 // <id> gclk_gen_0_oscillator #ifndef CONF_GCLK_GEN_0_SOURCE -#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0 #endif // <q> Run in Standby @@ -843,7 +843,7 @@ // <i> Indicates whether generic clock 11 configuration is enabled or not // <id> enable_gclk_gen_11 #ifndef CONF_GCLK_GENERATOR_11_CONFIG -#define CONF_GCLK_GENERATOR_11_CONFIG 0 +#define CONF_GCLK_GENERATOR_11_CONFIG 1 #endif // <h> Generic Clock Generator Control @@ -860,7 +860,7 @@ // <i> This defines the clock source for generic clock generator 11 // <id> gclk_gen_11_oscillator #ifndef CONF_GCLK_GEN_11_SOURCE -#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC0 +#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1 #endif // <q> Run in Standby @@ -902,7 +902,7 @@ // <i> Indicates whether Generic Clock Generator Enable is enabled or not // <id> gclk_arch_gen_11_enable #ifndef CONF_GCLK_GEN_11_GENEN -#define CONF_GCLK_GEN_11_GENEN 0 +#define CONF_GCLK_GEN_11_GENEN 1 #endif // </h> @@ -910,7 +910,7 @@ //<o> Generic clock generator 11 division <0x0000-0xFFFF> // <id> gclk_gen_11_div #ifndef CONF_GCLK_GEN_11_DIV -#define CONF_GCLK_GEN_11_DIV 1 +#define CONF_GCLK_GEN_11_DIV 6 #endif // </h> // </e> diff --git a/sysmoOCTSIM/config/hpl_oscctrl_config.h b/sysmoOCTSIM/config/hpl_oscctrl_config.h index 11e4a24..d59ac43 100644 --- a/sysmoOCTSIM/config/hpl_oscctrl_config.h +++ b/sysmoOCTSIM/config/hpl_oscctrl_config.h @@ -382,7 +382,7 @@ // <i> Indicates whether configuration for FDPLL0 is enabled or not // <id> enable_fdpll0 #ifndef CONF_FDPLL0_CONFIG -#define CONF_FDPLL0_CONFIG 0 +#define CONF_FDPLL0_CONFIG 1 #endif // <y> Reference Clock Source @@ -404,7 +404,7 @@ // <i> Select the clock source. // <id> fdpll0_ref_clock #ifndef CONF_FDPLL0_GCLK -#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K +#define CONF_FDPLL0_GCLK GCLK_PCHCTRL_GEN_GCLK11_Val #endif // <h> Digital Phase Locked Loop Control @@ -412,7 +412,7 @@ // <i> Indicates whether Digital Phase Locked Loop is enabled or not // <id> fdpll0_arch_enable #ifndef CONF_FDPLL0_ENABLE -#define CONF_FDPLL0_ENABLE 0 +#define CONF_FDPLL0_ENABLE 1 #endif // <q> On Demand Control @@ -432,19 +432,19 @@ // <o> Loop Divider Ratio Fractional Part <0x0-0x1F> // <id> fdpll0_ldrfrac #ifndef CONF_FDPLL0_LDRFRAC -#define CONF_FDPLL0_LDRFRAC 0xd +#define CONF_FDPLL0_LDRFRAC 0x0 #endif // <o> Loop Divider Ratio Integer Part <0x0-0x1FFF> // <id> fdpll0_ldr #ifndef CONF_FDPLL0_LDR -#define CONF_FDPLL0_LDR 0x5b7 +#define CONF_FDPLL0_LDR 0x3b #endif // <o> Clock Divider <0x0-0x7FF> // <id> fdpll0_clock_div #ifndef CONF_FDPLL0_DIV -#define CONF_FDPLL0_DIV 0x0 +#define CONF_FDPLL0_DIV 0x6 #endif // <q> DCO Filter Enable @@ -485,7 +485,7 @@ // <0x3=>XOSC1 clock reference // <id> fdpll0_arch_refclk #ifndef CONF_FDPLL0_REFCLK -#define CONF_FDPLL0_REFCLK 0x1 +#define CONF_FDPLL0_REFCLK 0x3 #endif // <q> Wake Up Fast diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h index 9a9c30f..8078e4b 100644 --- a/sysmoOCTSIM/config/peripheral_clk_config.h +++ b/sysmoOCTSIM/config/peripheral_clk_config.h @@ -9,7 +9,7 @@ * \brief CPU's Clock frequency */ #ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 12000000 +#define CONF_CPU_FREQUENCY 120000000 #endif // <y> USB Clock Source diff --git a/sysmoOCTSIM/hpl/core/hpl_init.c b/sysmoOCTSIM/hpl/core/hpl_init.c index be0db93..6f3dc20 100644 --- a/sysmoOCTSIM/hpl/core/hpl_init.c +++ b/sysmoOCTSIM/hpl/core/hpl_init.c @@ -42,10 +42,11 @@ #include <hal_cache.h> /* Referenced GCLKs (out of 0~11), should be initialized firstly + * - GCLK 11 for FDPLL0 */ -#define _GCLK_INIT_1ST 0x00000000 +#define _GCLK_INIT_1ST 0x00000800 /* Not referenced GCLKs, initialized last */ -#define _GCLK_INIT_LAST 0x00000FFF +#define _GCLK_INIT_LAST 0x000007FF /** * \brief Initialize the hardware abstraction layer -- To view, visit https://gerrit.osmocom.org/12797 To unsubscribe, or for help writing mail filters, visit https://gerrit.osmocom.org/settings Gerrit-Project: osmo-ccid-firmware Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I642e724ec56a376addf21cc58ecd2ef1b40bd116 Gerrit-Change-Number: 12797 Gerrit-PatchSet: 2 Gerrit-Owner: Kévin Redon <kredon at sysmocom.de> Gerrit-Reviewer: Harald Welte <laforge at gnumonks.org> Gerrit-Reviewer: Jenkins Builder (1000002) -------------- next part -------------- An HTML attachment was scrubbed... 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