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Kévin Redon gerrit-no-reply at lists.osmocom.orgKévin Redon has uploaded this change for review. ( https://gerrit.osmocom.org/12799 Change subject: set DPLL1 to 100 MHz ...................................................................... set DPLL1 to 100 MHz use GCLK11 to bring external crystal oscillator XOSC1 from 12 MHz to 2MHz use DPLL1 to multiply 2 MHz to 100 MHz. the division is first needed because the DPLL0 maximum input frequency is 3.2 MHz 100 MHz is the maximum input frequency for the SERCOM peripherals Change-Id: I0482c39cc0db999904c585d21738dbce57ca3b55 --- M sysmoOCTSIM/atmel_start_config.atstart M sysmoOCTSIM/config/hpl_gclk_config.h M sysmoOCTSIM/config/hpl_oscctrl_config.h M sysmoOCTSIM/hpl/core/hpl_init.c 4 files changed, 22 insertions(+), 21 deletions(-) git pull ssh://gerrit.osmocom.org:29418/osmo-ccid-firmware refs/changes/99/12799/1 diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart index 5e27536..3899d79 100644 --- a/sysmoOCTSIM/atmel_start_config.atstart +++ b/sysmoOCTSIM/atmel_start_config.atstart @@ -647,7 +647,7 @@ enable_gclk_gen_1: true enable_gclk_gen_10: false enable_gclk_gen_11: true - enable_gclk_gen_2: false + enable_gclk_gen_2: true enable_gclk_gen_3: true enable_gclk_gen_4: false enable_gclk_gen_5: false @@ -675,7 +675,7 @@ gclk_arch_gen_1_oe: false gclk_arch_gen_1_oov: false gclk_arch_gen_1_runstdby: false - gclk_arch_gen_2_enable: false + gclk_arch_gen_2_enable: true gclk_arch_gen_2_idc: false gclk_arch_gen_2_oe: false gclk_arch_gen_2_oov: false @@ -728,8 +728,8 @@ gclk_gen_1_div_sel: false gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) gclk_gen_2_div: 1 - gclk_gen_2_div_sel: true - gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC0) + gclk_gen_2_div_sel: false + gclk_gen_2_oscillator: Digital Phase Locked Loop (DPLL1) gclk_gen_3_div: 1 gclk_gen_3_div_sel: false gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) @@ -830,7 +830,7 @@ dfll_ref_clock: Generic clock generator 3 enable_dfll: true enable_fdpll0: true - enable_fdpll1: false + enable_fdpll1: true enable_xosc0: false enable_xosc1: true fdpll0_arch_dcoen: false @@ -848,19 +848,19 @@ fdpll0_ldrfrac: 0 fdpll0_ref_clock: Generic clock generator 11 fdpll1_arch_dcoen: false - fdpll1_arch_enable: false + fdpll1_arch_enable: true fdpll1_arch_filter: 0 fdpll1_arch_lbypass: false fdpll1_arch_ltime: No time-out, automatic lock fdpll1_arch_ondemand: false - fdpll1_arch_refclk: XOSC32K clock reference + fdpll1_arch_refclk: XOSC1 clock reference fdpll1_arch_runstdby: false fdpll1_arch_wuf: false fdpll1_clock_dcofilter: 0 - fdpll1_clock_div: 0 - fdpll1_ldr: 1463 - fdpll1_ldrfrac: 13 - fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + fdpll1_clock_div: 6 + fdpll1_ldr: 49 + fdpll1_ldrfrac: 0 + fdpll1_ref_clock: Generic clock generator 11 xosc0_arch_cfden: false xosc0_arch_enable: false xosc0_arch_enalc: false diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h index fbaa9b7..398a617 100644 --- a/sysmoOCTSIM/config/hpl_gclk_config.h +++ b/sysmoOCTSIM/config/hpl_gclk_config.h @@ -159,7 +159,7 @@ // <i> Indicates whether generic clock 2 configuration is enabled or not // <id> enable_gclk_gen_2 #ifndef CONF_GCLK_GENERATOR_2_CONFIG -#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#define CONF_GCLK_GENERATOR_2_CONFIG 1 #endif // <h> Generic Clock Generator Control @@ -176,7 +176,7 @@ // <i> This defines the clock source for generic clock generator 2 // <id> gclk_gen_2_oscillator #ifndef CONF_GCLK_GEN_2_SOURCE -#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC0 +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_DPLL1 #endif // <q> Run in Standby @@ -190,7 +190,7 @@ // <i> Indicates whether Divide Selection is enabled or not //<id> gclk_gen_2_div_sel #ifndef CONF_GCLK_GEN_2_DIVSEL -#define CONF_GCLK_GEN_2_DIVSEL 1 +#define CONF_GCLK_GEN_2_DIVSEL 0 #endif // <q> Output Enable @@ -218,7 +218,7 @@ // <i> Indicates whether Generic Clock Generator Enable is enabled or not // <id> gclk_arch_gen_2_enable #ifndef CONF_GCLK_GEN_2_GENEN -#define CONF_GCLK_GEN_2_GENEN 0 +#define CONF_GCLK_GEN_2_GENEN 1 #endif // </h> diff --git a/sysmoOCTSIM/config/hpl_oscctrl_config.h b/sysmoOCTSIM/config/hpl_oscctrl_config.h index 6b3cc19..06ee571 100644 --- a/sysmoOCTSIM/config/hpl_oscctrl_config.h +++ b/sysmoOCTSIM/config/hpl_oscctrl_config.h @@ -529,7 +529,7 @@ // <i> Select the clock source. // <id> fdpll1_ref_clock #ifndef CONF_FDPLL1_GCLK -#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K +#define CONF_FDPLL1_GCLK GCLK_PCHCTRL_GEN_GCLK11_Val #endif // <h> Digital Phase Locked Loop Control @@ -537,7 +537,7 @@ // <i> Indicates whether Digital Phase Locked Loop is enabled or not // <id> fdpll1_arch_enable #ifndef CONF_FDPLL1_ENABLE -#define CONF_FDPLL1_ENABLE 0 +#define CONF_FDPLL1_ENABLE 1 #endif // <q> On Demand Control @@ -557,19 +557,19 @@ // <o> Loop Divider Ratio Fractional Part <0x0-0x1F> // <id> fdpll1_ldrfrac #ifndef CONF_FDPLL1_LDRFRAC -#define CONF_FDPLL1_LDRFRAC 0xd +#define CONF_FDPLL1_LDRFRAC 0x0 #endif // <o> Loop Divider Ratio Integer Part <0x0-0x1FFF> // <id> fdpll1_ldr #ifndef CONF_FDPLL1_LDR -#define CONF_FDPLL1_LDR 0x5b7 +#define CONF_FDPLL1_LDR 0x31 #endif // <o> Clock Divider <0x0-0x7FF> // <id> fdpll1_clock_div #ifndef CONF_FDPLL1_DIV -#define CONF_FDPLL1_DIV 0x0 +#define CONF_FDPLL1_DIV 0x6 #endif // <q> DCO Filter Enable @@ -610,7 +610,7 @@ // <0x3=>XOSC1 clock reference // <id> fdpll1_arch_refclk #ifndef CONF_FDPLL1_REFCLK -#define CONF_FDPLL1_REFCLK 0x1 +#define CONF_FDPLL1_REFCLK 0x3 #endif // <q> Wake Up Fast diff --git a/sysmoOCTSIM/hpl/core/hpl_init.c b/sysmoOCTSIM/hpl/core/hpl_init.c index 6f3dc20..bb8425c 100644 --- a/sysmoOCTSIM/hpl/core/hpl_init.c +++ b/sysmoOCTSIM/hpl/core/hpl_init.c @@ -42,6 +42,7 @@ #include <hal_cache.h> /* Referenced GCLKs (out of 0~11), should be initialized firstly + * - GCLK 11 for FDPLL1 * - GCLK 11 for FDPLL0 */ #define _GCLK_INIT_1ST 0x00000800 -- To view, visit https://gerrit.osmocom.org/12799 To unsubscribe, or for help writing mail filters, visit https://gerrit.osmocom.org/settings Gerrit-Project: osmo-ccid-firmware Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0482c39cc0db999904c585d21738dbce57ca3b55 Gerrit-Change-Number: 12799 Gerrit-PatchSet: 1 Gerrit-Owner: Kévin Redon <kredon at sysmocom.de> -------------- next part -------------- An HTML attachment was scrubbed... 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